/external/v8/src/arm64/ |
H A D | assembler-arm64-inl.h | 50 return reg_size; 57 return reg_size / 8; 63 return reg_size == 32; 69 return reg_size == 64; 86 ((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)) && 93 ((reg_size == kSRegSizeInBits) || (reg_size == kDRegSizeInBits)) && 101 DCHECK((reg_type != kNoRegister) || (reg_size == 0)); 109 return Aliases(other) && (reg_size 1026 ImmS(unsigned imms, unsigned reg_size) argument 1034 ImmR(unsigned immr, unsigned reg_size) argument 1043 ImmSetBits(unsigned imms, unsigned reg_size) argument 1052 ImmRotate(unsigned immr, unsigned reg_size) argument 1067 BitN(unsigned bitn, unsigned reg_size) argument [all...] |
H A D | instructions-arm64.cc | 75 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, argument 80 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); 82 for (unsigned i = width; i < reg_size; i *= 2) { 93 unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits; local 132 return RepeatBitsAcrossReg(reg_size,
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H A D | disasm-arm64.h | 64 bool IsMovzMovnImm(unsigned reg_size, uint64_t value);
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H A D | assembler-arm64.h | 131 int reg_size; member in struct:v8::internal::CPURegister 143 reg_size = 0; 149 reg_size = r.reg_size; 156 reg_size = r.reg_size; 219 reg_size = 0; 225 reg_size = r.reg_size; 232 reg_size 1191 int reg_size = rd.SizeInBits(); local [all...] |
H A D | disasm-arm64.cc | 231 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits local 233 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) { 256 bool DisassemblingDecoder::IsMovzMovnImm(unsigned reg_size, uint64_t value) { argument 257 DCHECK((reg_size == kXRegSizeInBits) || 258 ((reg_size == kWRegSizeInBits) && (value <= 0xffffffff))); 269 if ((reg_size == kXRegSizeInBits) && 276 if ((reg_size == kWRegSizeInBits) && 1510 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits local 1512 AppendToOutput("#%d", reg_size - r);
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H A D | macro-assembler-arm64.cc | 68 unsigned reg_size = rd.SizeInBits(); local 123 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) { 186 unsigned reg_size = rd.SizeInBits(); local 197 if (CountClearHalfWords(~imm, reg_size) > 198 CountClearHalfWords(imm, reg_size)) { 210 DCHECK((reg_size % 16) == 0); 320 unsigned MacroAssembler::CountClearHalfWords(uint64_t imm, unsigned reg_size) { argument 321 DCHECK((reg_size % 8) == 0); 323 for (unsigned i = 0; i < (reg_size / 16); i++) { 335 bool MacroAssembler::IsImmMovz(uint64_t imm, unsigned reg_size) { argument 343 IsImmMovn(uint64_t imm, unsigned reg_size) argument 418 int reg_size = dst.SizeInBits(); local 440 int reg_size = dst.SizeInBits(); local [all...] |
H A D | macro-assembler-arm64.h | 260 static bool IsImmMovn(uint64_t imm, unsigned reg_size); 261 static bool IsImmMovz(uint64_t imm, unsigned reg_size); 262 static unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size); 636 inline void PushSizeRegList(RegList registers, unsigned reg_size, argument 638 PushCPURegList(CPURegList(type, reg_size, registers)); 640 inline void PopSizeRegList(RegList registers, unsigned reg_size, argument 642 PopCPURegList(CPURegList(type, reg_size, registers));
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H A D | simulator-arm64.cc | 2172 T reg_size = sizeof(T) * 8; 2178 mask = diff < reg_size - 1 ? (static_cast<T>(1) << (diff + 1)) - 1 2182 umask = (umask >> R) | (umask << (reg_size - R)); 2184 diff += reg_size; 2212 T result = (static_cast<unsignedT>(src) >> R) | (src << (reg_size - R)); 2214 T topbits_preshift = (static_cast<T>(1) << (reg_size - diff - 1)) - 1; 2431 unsigned reg_size = (instr->Mask(FP64) == FP64) ? kDRegSizeInBits 2433 double fn_val = fpreg(reg_size, instr->Rn()); 2437 case FCMP_d: FPCompare(fn_val, fpreg(reg_size, instr->Rm())); break; 2454 unsigned reg_size [all...] |
/external/jemalloc/src/ |
H A D | android_je_mallinfo.c | 37 mi.uordblks += arena_bin_info[j].reg_size * bin->stats.curregs; 73 mi.fsmblks += arena_bin_info[j].reg_size * bin->stats.curregs; 92 mi.ordblks = arena_bin_info[bidx].reg_size * bin->stats.curregs;
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H A D | android_je_iterate.c | 143 callback(ptr, bin_info->reg_size, arg);
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H A D | stats.c | 69 size_t reg_size, run_size, curregs; local 85 CTL_M2_GET("arenas.bin.0.size", j, ®_size, size_t); 159 reg_size, j, curregs * reg_size, nmalloc, 169 reg_size, j, curregs * reg_size, nmalloc,
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/external/vixl/src/ |
H A D | utils-vixl.cc | 131 unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size) { argument 132 VIXL_ASSERT((reg_size % 8) == 0); 134 for (unsigned i = 0; i < (reg_size / 16); i++) {
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/external/vixl/src/aarch64/ |
H A D | simulator-aarch64.cc | 298 uint64_t Simulator::AddWithCarry(unsigned reg_size, 304 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize)); 306 uint64_t max_uint = (reg_size == kWRegSize) ? kWMaxUInt : kXMaxUInt; 307 uint64_t reg_mask = (reg_size == kWRegSize) ? kWRegMask : kXRegMask; 308 uint64_t sign_mask = (reg_size == kWRegSize) ? kWSignMask : kXSignMask; 315 ReadNzcv().SetN(CalcNFlag(result, reg_size)); 337 int64_t Simulator::ShiftOperand(unsigned reg_size, argument 341 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size 383 ExtendValue(unsigned reg_size, int64_t value, Extend extend_type, unsigned left_shift) const argument 471 GetPrintRegisterFormatForSize( unsigned reg_size, unsigned lane_size) argument 950 int reg_size = GetPrintRegSizeInBytes(format); local 1084 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1124 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1141 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1151 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1171 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1191 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1232 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1244 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1857 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1940 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 2110 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 2159 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 2213 unsigned reg_size = (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize; local 3928 int reg_size = RegisterSizeInBytesFromFormat(vf); local [all...] |
H A D | instructions-aarch64.cc | 51 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, argument 56 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); 58 for (unsigned i = width; i < reg_size; i *= 2) { 128 unsigned reg_size = GetSixtyFourBits() ? kXRegSize : kWRegSize; local 167 return RepeatBitsAcrossReg(reg_size,
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H A D | macro-assembler-aarch64.cc | 444 unsigned reg_size = rd.GetSizeInBits(); local 455 if (CountClearHalfWords(~imm, reg_size) > 456 CountClearHalfWords(imm, reg_size)) { 472 VIXL_ASSERT((reg_size % 16) == 0); 474 for (unsigned i = 0; i < (reg_size / 16); i++) { 512 int reg_size = dst.GetSizeInBits(); local 514 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { 521 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { 528 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) { 813 unsigned reg_size local 1571 int reg_size = dst.GetSizeInBits(); local 1990 int reg_size = registers.GetRegisterSizeInBytes(); local 2022 int reg_size = registers.GetRegisterSizeInBytes(); local 2321 const int reg_size = registers.GetRegisterSizeInBytes(); local 2372 int reg_size = registers.GetRegisterSizeInBytes(); local [all...] |
H A D | assembler-aarch64.h | 768 unsigned reg_size = rd.GetSizeInBits(); local 769 VIXL_ASSERT(shift < reg_size); 770 ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1); 2705 static Instr ImmS(unsigned imms, unsigned reg_size) { argument 2706 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(imms)) || 2707 ((reg_size == kWRegSize) && IsUint5(imms))); 2708 USE(reg_size); 2712 static Instr ImmR(unsigned immr, unsigned reg_size) { argument 2720 ImmSetBits(unsigned imms, unsigned reg_size) argument 2728 ImmRotate(unsigned immr, unsigned reg_size) argument 2741 BitN(unsigned bitn, unsigned reg_size) argument [all...] |
H A D | disasm-aarch64.h | 148 bool IsMovzMovnImm(unsigned reg_size, uint64_t value);
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/external/jemalloc/test/unit/ |
H A D | junk.c | 31 for (i = 0; i < bin_info->reg_size; i++) { 34 i, bin_info->reg_size);
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/external/vixl/test/aarch64/ |
H A D | test-utils-aarch64.h | 225 // r array will be populated with <reg_size>-sized registers, 237 int reg_size, 245 int reg_size,
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H A D | test-utils-aarch64.cc | 276 int reg_size, 285 r[i] = Register(n, reg_size); 307 int reg_size, 316 v[i] = FPRegister(n, reg_size); 273 PopulateRegisterArray(Register* w, Register* x, Register* r, int reg_size, int reg_count, RegList allowed) argument 304 PopulateFPRegisterArray(FPRegister* s, FPRegister* d, FPRegister* v, int reg_size, int reg_count, RegList allowed) argument
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H A D | test-simulator-aarch64.cc | 322 unsigned reg_size) { 323 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); 337 bool double_op = reg_size == kDRegSize; 455 unsigned reg_size) { 456 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); 471 bool double_op = reg_size == kDRegSize; 604 unsigned reg_size) { 605 VIXL_ASSERT((reg_size 318 Test2Op_Helper(Test2OpFPHelper_t helper, uintptr_t inputs, unsigned inputs_length, uintptr_t results, unsigned reg_size) argument 451 Test3Op_Helper(Test3OpFPHelper_t helper, uintptr_t inputs, unsigned inputs_length, uintptr_t results, unsigned reg_size) argument 600 TestCmp_Helper(TestFPCmpHelper_t helper, uintptr_t inputs, unsigned inputs_length, uintptr_t results, unsigned reg_size) argument 739 TestCmpZero_Helper(TestFPCmpZeroHelper_t helper, uintptr_t inputs, unsigned inputs_length, uintptr_t results, unsigned reg_size) argument [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_fs_reg_allocate.cpp | 758 const unsigned reg_size = dst.component_size(bld.dispatch_width()) / local 760 assert(count % reg_size == 0); 762 for (unsigned i = 0; i < count / reg_size; i++) { 783 dst.offset += reg_size * REG_SIZE; 784 spill_offset += reg_size * REG_SIZE; 792 const unsigned reg_size = src.component_size(bld.dispatch_width()) / local 794 assert(count % reg_size == 0); 796 for (unsigned i = 0; i < count / reg_size; i++) { 799 src.offset += reg_size * REG_SIZE; 800 spill_inst->offset = spill_offset + i * reg_size * REG_SIZ [all...] |
H A D | brw_ir_fs.h | 443 const unsigned reg_size = 445 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + 448 reg_size);
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H A D | brw_ir_vec4.h | 402 const unsigned reg_size = local 404 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), 405 reg_size);
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/external/mesa3d/src/gallium/drivers/etnaviv/ |
H A D | etnaviv_compiler.c | 130 size_t reg_size; member in struct:etna_compile_file 256 for (int idx = 0; idx < file->reg_size; ++idx) { 302 for (int idx = 0; idx < file->reg_size; ++idx) 512 c->file[x].reg_size = c->info.file_max[x] + 1; 514 for (int sub = 0; sub < c->file[x].reg_size; ++sub) { 1864 for (int idx = 0; idx < c->file[file].reg_size; ++idx) { 1930 for (int idx = 0; idx < file->reg_size; ++idx) { 1949 c->imm_base = c->file[TGSI_FILE_CONSTANT].reg_size * 4; 1964 for (int idx = 0; idx < c->file[TGSI_FILE_SAMPLER].reg_size; ++idx) { 2022 for (int idx = 0; idx < c->file[TGSI_FILE_INPUT].reg_size; [all...] |