/external/capstone/suite/MC/ARM/ |
H A D | thumb.s.cs | 11 0x1a,0xb2 = sxth r2, r3
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H A D | basic-thumb-instructions.s.cs | 127 0x2b,0xb2 = sxth r3, r5
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H A D | basic-thumb2-instructions.s.cs | 1026 0x31,0xb2 = sxth r1, r6 1027 0x0f,0xfa,0x98,0xf3 = sxth.w r3, r8, ror #8 1028 0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #24 1032 0x0f,0xfa,0x88,0xf7 = sxth.w r7, r8 1045 0x31,0xb2 = sxth r1, r6 1046 0x0f,0xfa,0x98,0xf3 = sxth.w r3, r8, ror #8 1047 0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #24
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H A D | basic-arm-instructions.s.cs | 873 0x76,0x10,0xbf,0xe6 = sxth r1, r6 874 0x78,0x34,0xbf,0xe6 = sxth r3, r8, ror #8 876 0x73,0x9c,0xbf,0xe6 = sxth r9, r3, ror #24
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/external/llvm/test/MC/ARM/ |
H A D | thumb.s | 26 sxth r2, r3 28 @ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]
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H A D | basic-thumb-instructions.s | 641 sxth r3, r5 644 @ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2]
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H A D | basic-thumb2-instructions.s | 3169 sxth r1, r6, ror #0 3170 sxth r3, r8, ror #8 3171 sxth r9, r3, ror #24 3175 sxth.w r7, r8 3177 @ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2] 3178 @ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3] 3179 @ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9] 3183 @ CHECK: sxth.w r7, r8 @ encoding: [0x0f,0xfa,0x88,0xf7] 3225 sxth r1, r6, ror #0 3226 sxth [all...] |
/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | thumb.s | 26 sxth r2, r3 28 @ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]
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H A D | basic-thumb-instructions.s | 590 sxth r3, r5 593 @ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2]
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H A D | basic-thumb2-instructions.s | 2672 sxth r1, r6, ror #0 2673 sxth r3, r8, ror #8 2674 sxth r9, r3, ror #24 2678 sxth.w r7, r8 2680 @ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2] 2681 @ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3] 2682 @ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9] 2686 @ CHECK: sxth.w r7, r8 @ encoding: [0x0f,0xfa,0x88,0xf7] 2728 sxth r1, r6, ror #0 2729 sxth [all...] |
H A D | basic-arm-instructions.s | 2226 sxth r1, r6, ror #0 2227 sxth r3, r8, ror #8 2229 sxth r9, r3, ror #24 2232 @ CHECK: sxth r1, r6 @ encoding: [0x76,0x10,0xbf,0xe6] 2233 @ CHECK: sxth r3, r8, ror #8 @ encoding: [0x78,0x34,0xbf,0xe6] 2235 @ CHECK: sxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xbf,0xe6]
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/external/llvm/test/MC/AArch64/ |
H A D | arm64-arithmetic-encoding.s | 175 add w1, w2, w3, sxth 184 ; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b] 192 add x1, x2, w3, sxth 199 ; CHECK: add x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x8b] 219 sub w1, w2, w3, sxth 228 ; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b] 236 sub x1, x2, w3, sxth 243 ; CHECK: sub x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xcb] 263 adds w1, w2, w3, sxth 272 ; CHECK: adds w1, w2, w3, sxth ; encodin [all...] |
H A D | basic-a64-instructions.s | 23 add x18, x13, w19, sxth 31 // CHECK: add x18, x13, w19, sxth // encoding: [0xb2,0xa1,0x33,0x8b] 41 add w26, w17, w19, sxth 49 // CHECK: add w26, w17, w19, sxth // encoding: [0x3a,0xa2,0x33,0x0b] 69 sub x18, x13, w19, sxth 77 // CHECK: sub x18, x13, w19, sxth // encoding: [0xb2,0xa1,0x33,0xcb] 86 sub w26, wsp, w19, sxth 94 // CHECK: sub w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x4b] 104 adds x18, sp, w19, sxth 112 // CHECK: adds x18, sp, w19, sxth // encodin [all...] |
H A D | basic-a64-diagnostics.s | 38 sub x3, xzr, w9, sxth #1 44 // CHECK-ERROR: sub x3, xzr, w9, sxth #1 833 sxth xzr, xzr 839 // CHECK-ERROR-AARCH64-NEXT: sxth xzr, xzr
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/external/libxaac/decoder/armv8/ |
H A D | ixheaacd_fft32x32_ld2_armv8.s | 270 sxth w11, w11 272 sxth w21, w21 275 sxth w12, w12 277 sxth w22, w22 280 sxth w14, w14 282 sxth w24, w24
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H A D | ixheaacd_apply_scale_factors.s | 80 sxth w17, w17 //16-bit value stored as 32-bit,so SMULWB can still be used
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H A D | ixheaacd_post_twiddle_overlap.s | 103 sxth x19, w19 129 sxth x19, w19 133 sxth x19, w19 142 sxth x11, w11 147 sxth x19, w19 282 sxth x5, w5 284 sxth x19, w19
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/external/libhevc/decoder/arm64/ |
H A D | ihevcd_itrans_recon_dc_chroma.s | 65 sxth x5, w5 // since the argument is of word16, sign extend to x register
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H A D | ihevcd_itrans_recon_dc_luma.s | 64 sxth x5,w5
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/external/valgrind/none/tests/arm64/ |
H A D | integer.stdout.exp | 942 add x21,x22,x23,sxth #0 :: rd a3ca7e66297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 00000000 943 add x21,x22,x23,sxth #1 :: rd 09fb0ab6a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 944 add x21,x22,x23,sxth #2 :: rd 52d448b3d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 945 add x21,x22,x23,sxth #3 :: rd a7e754e8ff36f596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv 00000000 946 add x21,x22,x23,sxth #4 :: rd 2e10f2a4055782ae rm 2e10f2a4055bec0e, rn 77f3b8dcc730b96a, cin 0, nzcv 00000000 982 adds x21,x22,x23,sxth #0 :: rd a3ca7e66297ca007 rm a3ca7e66297c469b, rn a67e09b8e126596c, cin 0, nzcv 80000000 N 983 adds x21,x22,x23,sxth #1 :: rd 09fb0ab6a60b470b rm 09fb0ab6a60b34c3, rn 2584971088d90924, cin 0, nzcv 00000000 984 adds x21,x22,x23,sxth #2 :: rd 52d448b3d5712e15 rm 52d448b3d56f5369, rn d98d2022a9b876ab, cin 0, nzcv 00000000 985 adds x21,x22,x23,sxth #3 :: rd a7e754e8ff36f596 rm a7e754e8ff3a554e, rn 7ab2520302849409, cin 0, nzcv a0000000 N C 986 adds x21,x22,x23,sxth # [all...] |
/external/v8/src/arm/ |
H A D | disasm-arm.cc | 1133 Format(instr, "sxth'cond 'rd, 'rm"); 1136 Format(instr, "sxth'cond 'rd, 'rm, ror #8"); 1139 Format(instr, "sxth'cond 'rd, 'rm, ror #16"); 1142 Format(instr, "sxth'cond 'rd, 'rm, ror #24");
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/external/vixl/test/aarch32/ |
H A D | test-assembler-cond-rd-operand-rn-t32.cc | 62 M(sxth) \ 344 #include "aarch32/traces/assembler-cond-rd-operand-rn-sxth-t32.h"
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/external/capstone/suite/MC/AArch64/ |
H A D | basic-a64-instructions.s.cs | 7 0xb2,0xa1,0x33,0x8b = add x18, x13, w19, sxth 15 0x3a,0xa2,0x33,0x0b = add w26, w17, w19, sxth 27 0xb2,0xa1,0x33,0xcb = sub x18, x13, w19, sxth 35 0xfa,0xa3,0x33,0x4b = sub w26, wsp, w19, sxth 43 0xf2,0xa3,0x33,0xab = adds x18, sp, w19, sxth 51 0xfa,0xa3,0x33,0x2b = adds w26, wsp, w19, sxth 59 0xf2,0xa3,0x33,0xeb = subs x18, sp, w19, sxth 67 0xfa,0xa3,0x33,0x6b = subs w26, wsp, w19, sxth 75 0xff,0xa3,0x33,0xeb = cmp sp, w19, sxth 83 0xff,0xa3,0x33,0x6b = cmp wsp, w19, sxth [all...] |
/external/valgrind/none/tests/arm/ |
H A D | v6intARM.stdout.exp | 657 sxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 658 sxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 659 sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, carryin 0, cpsr 0x00000000 660 sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, carryin 0, cpsr 0x00000000 661 sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, carryin 0, cpsr 0x00000000 662 sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, carryin 0, cpsr 0x00000000 663 sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
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/external/vixl/src/aarch32/ |
H A D | assembler-aarch32.h | 3545 void sxth(Condition cond, 3549 void sxth(Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler 3550 sxth(al, Best, rd, operand); 3552 void sxth(Condition cond, Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler 3553 sxth(cond, Best, rd, operand); 3555 void sxth(EncodingSize size, Register rd, const Operand& operand) { function in class:vixl::aarch32::Assembler 3556 sxth(al, size, rd, operand);
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