/external/mesa3d/src/intel/isl/ |
H A D | isl_gen4.h | 36 enum isl_tiling tiling, 42 enum isl_tiling tiling,
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H A D | isl_gen6.h | 36 enum isl_tiling tiling, 42 enum isl_tiling tiling,
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H A D | isl_gen8.h | 36 enum isl_tiling tiling, 42 enum isl_tiling tiling,
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H A D | isl_gen4.c | 30 enum isl_tiling tiling, 43 enum isl_tiling tiling, 50 assert(!isl_tiling_is_std_y(tiling)); 28 isl_gen4_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) argument 41 isl_gen4_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, enum isl_msaa_layout msaa_layout, struct isl_extent3d *image_align_el) argument
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H A D | isl_gen9.h | 36 enum isl_tiling tiling,
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H A D | isl_gen7.h | 41 enum isl_tiling tiling, 47 enum isl_tiling tiling,
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H A D | isl_gen9.c | 30 * for the standard tiling formats Yf and Ys. 35 enum isl_tiling tiling, 41 assert(isl_tiling_is_std_y(tiling)); 44 const uint32_t is_Ys = tiling == ISL_TILING_Ys; 102 enum isl_tiling tiling, 168 if (isl_tiling_is_std_y(tiling)) { 170 gen9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout, 199 isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout, 33 gen9_calc_std_image_alignment_sa(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_msaa_layout msaa_layout, struct isl_extent3d *align_sa) argument 100 isl_gen9_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, enum isl_msaa_layout msaa_layout, struct isl_extent3d *image_align_el) argument
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H A D | isl_gen6.c | 30 enum isl_tiling tiling, 59 if (tiling == ISL_TILING_LINEAR) 71 enum isl_tiling tiling, 28 isl_gen6_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) argument 69 isl_gen6_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, enum isl_msaa_layout msaa_layout, struct isl_extent3d *image_align_el) argument
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H A D | isl.c | 128 enum isl_tiling tiling, 135 if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) { 139 * This really only works on legacy X and Y tiling formats. 141 assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0); 143 return isl_tiling_get_info(dev, tiling, format_bpb / 3, tile_info); 146 switch (tiling) { 190 bool is_Ys = tiling == ISL_TILING_Ys; 203 * 128bpb format. The tiling has the same physical dimensions as 204 * Y-tiling bu 127 isl_tiling_get_info(const struct isl_device *dev, enum isl_tiling tiling, uint32_t format_bpb, struct isl_tile_info *tile_info) argument 252 isl_surf_choose_tiling(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling *tiling) argument 316 isl_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) argument 476 isl_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, enum isl_msaa_layout msaa_layout, struct isl_extent3d *image_align_el) argument 511 isl_surf_choose_dim_layout(const struct isl_device *dev, enum isl_surf_dim logical_dim, enum isl_tiling tiling) argument 559 isl_calc_phys_level0_extent_sa(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_dim_layout dim_layout, enum isl_tiling tiling, enum isl_msaa_layout msaa_layout, struct isl_extent4d *phys_level0_sa) argument 1192 enum isl_tiling tiling; local 1784 isl_tiling_get_intratile_offset_el(const struct isl_device *dev, enum isl_tiling tiling, uint8_t bs, uint32_t row_pitch, uint32_t total_x_offset_el, uint32_t total_y_offset_el, uint32_t *base_address_offset, uint32_t *x_offset_el, uint32_t *y_offset_el) argument [all...] |
H A D | isl_gen7.c | 30 enum isl_tiling tiling, 86 if (tiling == ISL_TILING_LINEAR) 174 * @brief Filter out tiling flags that are incompatible with the surface. 181 * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling 209 /* Separate stencil requires W tiling, and W tiling requires separate 245 /* FINISHME[SKL]: Y tiling for display surfaces */ 262 * As usual, though, stencil is special and requires W-tiling. 272 /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1, 323 enum isl_tiling tiling) 28 isl_gen7_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) argument 321 gen7_choose_valign_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling) argument 391 isl_gen7_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, enum isl_msaa_layout msaa_layout, struct isl_extent3d *image_align_el) argument [all...] |
H A D | isl_gen8.c | 30 enum isl_tiling tiling, 185 enum isl_tiling tiling, 193 assert(!isl_tiling_is_std_y(tiling)); 223 * - Vertical alignment restrictions vary with memory tiling type: 28 isl_gen8_choose_msaa_layout(const struct isl_device *dev, const struct isl_surf_init_info *info, enum isl_tiling tiling, enum isl_msaa_layout *msaa_layout) argument 183 isl_gen8_choose_image_alignment_el(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, enum isl_tiling tiling, enum isl_dim_layout dim_layout, enum isl_msaa_layout msaa_layout, struct isl_extent3d *image_align_el) argument
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/external/mesa3d/src/mesa/drivers/dri/i915/ |
H A D | intel_regions.c | 111 uint32_t tiling, drm_intel_bo *buffer) 125 region->tiling = tiling; 133 uint32_t tiling, 147 &tiling, &aligned_pitch, flags); 152 aligned_pitch, tiling, buffer); 183 uint32_t bit_6_swizzle, tiling; local 188 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle); 190 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", 197 width, height, pitch, tiling, buffe 108 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument 132 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument 218 uint32_t bit_6_swizzle, tiling; local 291 uint32_t tiling = region->tiling; local 324 uint32_t tiling = region->tiling; local [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | intel_tiled_memcpy.h | 46 uint32_t tiling, 55 uint32_t tiling,
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/external/mesa3d/src/gallium/drivers/i915/ |
H A D | i915_screen.h | 50 boolean tiling; member in struct:i915_screen::__anon16202
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/external/drm_gralloc/ |
H A D | gralloc_drm_radeon.c | 81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) argument 86 if (tiling & RADEON_TILING_MACRO) { 92 } else if (tiling & RADEON_TILING_MICRO) { 112 if (tiling) 122 static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling) argument 127 if (tiling & RADEON_TILING_MACRO) 129 else if (tiling & RADEON_TILING_MICRO) 135 if (tiling) 146 int bpe, uint32_t tiling) 148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling); 145 radeon_get_base_align(struct radeon_info *info, int bpe, uint32_t tiling) argument 191 uint32_t tiling, domain; local [all...] |
H A D | gralloc_drm_intel.c | 72 uint32_t tiling; member in struct:intel_buffer 244 uint32_t *tiling, unsigned long *stride) 276 *tiling = I915_TILING_X; 279 *tiling = I915_TILING_NONE; 288 bpp, tiling, stride, flags); 295 if (*tiling != I915_TILING_NONE) { 297 *tiling = I915_TILING_NONE; 310 *tiling = I915_TILING_NONE; 314 *tiling = I915_TILING_X; 316 *tiling 242 alloc_ibo(struct intel_info *info, const struct gralloc_drm_handle_t *handle, uint32_t *tiling, unsigned long *stride) argument [all...] |
/external/mesa3d/src/gallium/drivers/ilo/core/ |
H A D | ilo_builder_blt.h | 57 enum gen_surface_tiling tiling; member in struct:gen6_blt_xy_bo 174 if (dst->tiling != GEN6_TILING_NONE) { 177 assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y); 178 dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512; 278 if (dst->tiling != GEN6_TILING_NONE) { 281 assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y); 282 dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512; 287 if (src->tiling ! [all...] |
H A D | intel_winsys.h | 157 enum intel_tiling_mode *tiling, 161 * Export \p bo as a winsys handle for inter-process sharing. \p tiling and 167 enum intel_tiling_mode tiling, 219 * Set the tiling of \p bo. The info is used by GTT mapping and bo export. 223 enum intel_tiling_mode tiling, 231 * but the caller needs to handle tiling or swizzling manually if the bo is
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/external/libdrm/tegra/ |
H A D | tegra.h | 61 struct drm_tegra_bo_tiling *tiling); 63 const struct drm_tegra_bo_tiling *tiling);
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/external/mesa3d/src/gallium/drivers/vc4/ |
H A D | vc4_resource.h | 45 uint8_t tiling; member in struct:vc4_resource_slice 51 uint8_t tiling; member in struct:vc4_surface
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | radeon_mipmap_tree.h | 94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, unsigned target); 101 unsigned tiling);
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_mipmap_tree.h | 94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, unsigned target); 101 unsigned tiling);
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/external/skia/src/gpu/vk/ |
H A D | GrVkImage.h | 92 void setNewResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling); 106 Resource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) argument 109 , fImageTiling(tiling) {} 142 BorrowedResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) argument 143 : Resource(image, alloc, tiling) {
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/external/skqp/src/gpu/vk/ |
H A D | GrVkImage.h | 93 void setNewResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling); 107 Resource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) argument 110 , fImageTiling(tiling) {} 143 BorrowedResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) argument 144 : Resource(image, alloc, tiling) {
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/external/mesa3d/src/gallium/drivers/ilo/ |
H A D | ilo_resource.c | 220 winsys_to_surface_tiling(enum intel_tiling_mode tiling) argument 222 switch (tiling) { 230 assert(!"unknown tiling"); 236 surface_to_winsys_tiling(enum gen_surface_tiling tiling) argument 238 switch (tiling) { 246 assert(!"unknown tiling"); 300 /* set the tiling for transfer and export */ 301 if (bo && (tex->image.tiling == GEN6_TILING_X || 302 tex->image.tiling == GEN6_TILING_Y)) { 303 const enum intel_tiling_mode tiling local 442 enum intel_tiling_mode tiling; local 579 enum intel_tiling_mode tiling; local [all...] |