Searched refs:txc (Results 1 - 23 of 23) sorted by relevance

/external/linux-kselftest/tools/testing/selftests/timers/
H A Dfreq-step.c90 struct timex txc; local
92 txc.modes = ADJ_SETOFFSET;
93 txc.time.tv_sec = 0;
94 txc.time.tv_usec = 0;
96 if (adjtimex(&txc) < 0) {
104 struct timex txc; local
109 txc.modes = ADJ_TICK | ADJ_FREQUENCY;
110 txc.tick = 1000000 / user_hz + tick_offset;
111 txc.freq = (1e6 * freq - user_hz * tick_offset) * (1 << 16);
113 if (adjtimex(&txc) <
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/external/mesa3d/src/intel/isl/
H A Disl_gen7.c221 if (isl_format_get_layout(info->format)->txc == ISL_TXC_ASTC)
225 if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS)
H A Disl_gen8.c196 if (fmtl->txc == ISL_TXC_CCS) {
H A Disl_gen9.c111 if (fmtl->txc == ISL_TXC_CCS) {
H A Dgen_format_layout.py85 .txc = ISL_TXC_${format.txc},
158 self.txc = line[13].strip().upper() or 'NONE'
H A Disl_format.c384 if (fmtl->txc == ISL_TXC_ETC1 || fmtl->txc == ISL_TXC_ETC2)
391 if (fmtl->txc == ISL_TXC_ASTC)
410 if (fmtl->txc == ISL_TXC_ETC1 || fmtl->txc == ISL_TXC_ETC2)
417 if (fmtl->txc == ISL_TXC_ASTC)
H A Disl.h737 enum isl_txc txc; member in struct:isl_format_layout
1085 return fmtl->txc != ISL_TXC_NONE;
1091 switch (isl_format_get_layout(fmt)->txc) {
H A Disl.c268 assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS);
946 if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
H A Dnv50_compute.c133 PUSH_DATAh(push, screen->txc->offset);
134 PUSH_DATA (push, screen->txc->offset);
140 PUSH_DATAh(push, screen->txc->offset + 65536);
141 PUSH_DATA (push, screen->txc->offset + 65536);
H A Dnv50_tex.c243 struct nouveau_bo *txc = nv50->screen->txc; local
270 PUSH_DATAh(push, txc->offset);
271 PUSH_DATA (push, txc->offset);
367 nv50_sifc_linear_u8(&nv50->base, nv50->screen->txc,
H A Dnv50_screen.h69 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */ member in struct:nv50_screen
H A Dnv50_screen.c470 nouveau_bo_ref(NULL, &screen->txc);
682 PUSH_DATAh(push, screen->txc->offset);
683 PUSH_DATA (push, screen->txc->offset);
687 PUSH_DATAh(push, screen->txc->offset + 65536);
688 PUSH_DATA (push, screen->txc->offset + 65536);
1000 &screen->txc);
H A Dnv50_context.c368 BCTX_REFN_bo(nv50->bufctx_3d, 3D_SCREEN, flags, screen->txc);
372 BCTX_REFN_bo(nv50->bufctx_cp, CP_SCREEN, flags, screen->txc);
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
H A Dnve4_compute.c110 PUSH_DATAh(push, screen->txc->offset);
111 PUSH_DATA (push, screen->txc->offset);
114 PUSH_DATAh(push, screen->txc->offset + 65536);
115 PUSH_DATA (push, screen->txc->offset + 65536);
197 struct nouveau_bo *txc = nvc0->screen->txc; local
213 PUSH_DATAh(push, txc->offset + (tic->id * 32));
214 PUSH_DATA (push, txc->offset + (tic->id * 32));
701 struct nouveau_bo *txc = nvc0->screen->txc; local
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H A Dnvc0_compute.c106 PUSH_DATAh(push, screen->txc->offset);
107 PUSH_DATA (push, screen->txc->offset);
112 PUSH_DATAh(push, screen->txc->offset + 65536);
113 PUSH_DATA (push, screen->txc->offset + 65536);
H A Dnvc0_screen.h71 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */ member in struct:nvc0_screen
H A Dnvc0_screen.c536 nouveau_bo_ref(NULL, &screen->txc);
1074 &screen->txc);
1076 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1079 PUSH_DATAh(push, screen->txc->offset);
1080 PUSH_DATA (push, screen->txc->offset);
1092 PUSH_DATAh(push, screen->txc->offset + 65536);
1093 PUSH_DATA (push, screen->txc->offset + 65536);
H A Dnvc0_context.c444 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_SCREEN, flags, screen->txc);
448 BCTX_REFN_bo(nvc0->bufctx_cp, CP_SCREEN, flags, screen->txc);
H A Dnvc0_tex.c496 nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
562 nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
637 nvc0_m2mf_push_linear(&nvc0->base, nvc0->screen->txc,
679 nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc,
1116 nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
H A Dnvc0_state_validate.c756 nvc0->base.push_data(&nvc0->base, screen->txc, 65536 + tsc->id * 32,
771 nvc0->base.push_data(&nvc0->base, screen->txc, tic->id * 32,
/external/mesa3d/src/intel/blorp/
H A Dblorp_clear.c686 assert(aux_fmtl->txc == ISL_TXC_CCS);
/external/mesa3d/src/intel/vulkan/
H A Danv_formats.c428 if (isl_format_get_layout(linear_fmt.isl_format)->txc == ISL_TXC_ASTC)
H A Danv_blorp.c135 if (fmtl->txc == ISL_TXC_ASTC) {

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