Searched refs:vform (Results 1 - 5 of 5) sorted by relevance

/external/vixl/src/aarch64/
H A Dlogic-aarch64.cc402 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { argument
403 dst.ClearForWrite(vform);
404 for (int i = 0; i < LaneCountFromFormat(vform); i++) {
405 dst.ReadUintFromMem(vform, i, addr);
406 addr += LaneSizeInBytesFromFormat(vform);
411 void Simulator::ld1(VectorFormat vform, argument
415 dst.ReadUintFromMem(vform, index, addr);
419 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { argument
420 dst.ClearForWrite(vform);
421 for (int i = 0; i < LaneCountFromFormat(vform);
427 ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr1) argument
444 ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, int index, uint64_t addr1) argument
457 ld2r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr) argument
471 ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr1) argument
493 ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, int index, uint64_t addr1) argument
510 ld3r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr) argument
528 ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr1) argument
555 ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, int index, uint64_t addr1) argument
576 ld4r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr) argument
598 st1(VectorFormat vform, LogicVRegister src, uint64_t addr) argument
606 st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr) argument
614 st2(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, uint64_t addr) argument
629 st2(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, int index, uint64_t addr) argument
640 st3(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr) argument
659 st3(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, LogicVRegister dst3, int index, uint64_t addr) argument
672 st4(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr) argument
695 st4(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, int index, uint64_t addr) argument
710 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument
754 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) argument
765 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
779 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
810 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
822 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
833 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
844 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
856 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
867 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
878 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
889 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
901 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
913 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
925 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
937 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
949 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
961 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
973 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
985 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
997 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1009 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1021 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1033 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1045 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1057 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1069 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1081 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1093 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1105 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1116 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1139 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1153 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1169 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1186 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1217 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1229 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1241 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1253 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1265 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1277 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, uint64_t imm) argument
1294 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1310 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1326 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1342 sminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument
1363 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1371 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1379 sminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument
1407 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1415 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1423 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1435 addv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1453 saddlv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1470 uaddlv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1487 sminmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool max) argument
1506 smaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1514 sminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1522 uminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument
1543 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1551 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1559 uminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument
1587 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1595 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1603 uminmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool max) argument
1622 umaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1630 uminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1638 shl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1649 sshll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1661 sshll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1673 shll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1681 shll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1689 ushll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1701 ushll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1713 sli(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1730 sqshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1741 uqshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1752 sqshlu(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1763 sri(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1789 ushr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1800 sshr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1811 ssra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1821 usra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1831 srsra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1841 ursra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
1851 cls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1869 clz(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1887 cnt(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
1910 sshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1970 ushl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2009 neg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2025 suqadd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2046 usqadd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2067 abs(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2189 xtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2196 sqxtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2203 sqxtun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2210 uqxtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2217 absdiff(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool issigned) argument
2238 saba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2250 uaba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2262 not_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2273 rbit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2299 rev(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int revSize) argument
2320 rev16(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2327 rev32(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2334 rev64(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2341 addlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool is_signed, bool do_accumulate) argument
2373 saddlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2380 uaddlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2387 sadalp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2394 uadalp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2401 ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
2422 dup_element(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int src_index) argument
2436 dup_immediate(VectorFormat vform, LogicVRegister dst, uint64_t imm) argument
2449 ins_element(VectorFormat vform, LogicVRegister dst, int dst_index, const LogicVRegister& src, int src_index) argument
2459 ins_immediate(VectorFormat vform, LogicVRegister dst, int dst_index, uint64_t imm) argument
2469 movi(VectorFormat vform, LogicVRegister dst, uint64_t imm) argument
2481 mvni(VectorFormat vform, LogicVRegister dst, uint64_t imm) argument
2493 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, uint64_t imm) argument
2510 uxtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2523 sxtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2536 uxtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2550 sxtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
2564 shrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2576 shrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2588 rshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2600 rshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2612 Table(VectorFormat vform, LogicVRegister dst, const LogicVRegister& ind, bool zero_out_of_bounds, const LogicVRegister* tab1, const LogicVRegister* tab2, const LogicVRegister* tab3, const LogicVRegister* tab4) argument
2639 tbl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& ind) argument
2647 tbl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& ind) argument
2656 tbl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& tab3, const LogicVRegister& ind) argument
2666 tbl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& tab3, const LogicVRegister& tab4, const LogicVRegister& ind) argument
2677 tbx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& ind) argument
2685 tbx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& ind) argument
2694 tbx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& tab3, const LogicVRegister& ind) argument
2704 tbx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& tab3, const LogicVRegister& tab4, const LogicVRegister& ind) argument
2715 uqshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2723 uqshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2731 uqrshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2739 uqrshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2747 sqshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2759 sqshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2771 sqrshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2783 sqrshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2795 sqshrun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2807 sqshrun2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2819 sqrshrun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2831 sqrshrun2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) argument
2843 uaddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2855 uaddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2867 uaddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2878 uaddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2889 saddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2901 saddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2913 saddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2924 saddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2935 usubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2947 usubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2959 usubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2970 usubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2981 ssubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2993 ssubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3005 ssubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3016 ssubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3027 uabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3039 uabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3051 sabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3063 sabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3075 uabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3087 uabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3099 sabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3111 sabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3123 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3135 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3147 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3159 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3171 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3183 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3195 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3207 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3219 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3231 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3243 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3255 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3267 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3277 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3287 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3297 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3307 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3317 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3327 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool round) argument
3357 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3365 addhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3376 addhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3387 raddhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3398 raddhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3409 subhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3420 subhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3431 rsubhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3442 rsubhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3453 trn1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3473 trn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3493 zip1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3513 zip2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3533 uzp1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3552 uzp2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3967 fnmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3978 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3993 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4008 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4023 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4038 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument
4077 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument
4092 fcmp_zero(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, Condition cond) argument
4109 fabscmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument
4130 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4146 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4161 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4177 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4192 fneg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4205 fneg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4219 fabs_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4234 fabs_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4247 fabd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4258 fsqrt(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4308 fminmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPMinMaxOp Op) argument
4323 fmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4330 fminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4337 fmaxnmv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4344 fminnmv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4351 fmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
4371 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
4391 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
4411 fmulx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
4431 frint(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, bool inexact_exception) argument
4461 fcvts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, int fbits) argument
4483 fcvtu(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, int fbits) argument
4505 fcvtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4522 fcvtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4540 fcvtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4557 fcvtn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4575 fcvtxn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4587 fcvtxn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4682 frsqrte(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4803 frecpe(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding round) argument
4824 ursqrte(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4857 urecpe(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4879 frecpx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4909 frecpx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) argument
4921 scvtf(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int fbits, FPRounding round) argument
4940 ucvtf(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int fbits, FPRounding round) argument
[all...]
H A Dinstructions-aarch64.cc396 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { argument
397 VIXL_ASSERT(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D ||
398 vform == kFormatH || vform == kFormatS || vform == kFormatD);
399 switch (vform) {
419 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { argument
420 VIXL_ASSERT(vform
442 VectorFormatFillQ(VectorFormat vform) argument
466 VectorFormatHalfWidthDoubleLanes(VectorFormat vform) argument
486 VectorFormatDoubleLanes(VectorFormat vform) argument
502 VectorFormatHalfLanes(VectorFormat vform) argument
535 ScalarFormatFromFormat(VectorFormat vform) argument
540 RegisterSizeInBitsFromFormat(VectorFormat vform) argument
562 RegisterSizeInBytesFromFormat(VectorFormat vform) argument
567 LaneSizeInBitsFromFormat(VectorFormat vform) argument
593 LaneSizeInBytesFromFormat(VectorFormat vform) argument
598 LaneSizeInBytesLog2FromFormat(VectorFormat vform) argument
624 LaneCountFromFormat(VectorFormat vform) argument
651 MaxLaneCountFromFormat(VectorFormat vform) argument
678 IsVectorFormat(VectorFormat vform) argument
692 MaxIntFromFormat(VectorFormat vform) argument
697 MinIntFromFormat(VectorFormat vform) argument
702 MaxUintFromFormat(VectorFormat vform) argument
[all...]
H A Dsimulator-aarch64.h373 int64_t Int(VectorFormat vform, int index) const { argument
375 switch (LaneSizeInBitsFromFormat(vform)) {
395 uint64_t Uint(VectorFormat vform, int index) const { argument
397 switch (LaneSizeInBitsFromFormat(vform)) {
417 uint64_t UintLeftJustified(VectorFormat vform, int index) const { argument
418 return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform));
421 int64_t IntLeftJustified(VectorFormat vform, int index) const { argument
422 uint64_t value = UintLeftJustified(vform, index);
428 void SetInt(VectorFormat vform, in argument
448 SetIntArray(VectorFormat vform, const int64_t* src) const argument
455 SetUint(VectorFormat vform, int index, uint64_t value) const argument
475 SetUintArray(VectorFormat vform, const uint64_t* src) const argument
482 ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const argument
502 WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const argument
579 SignedSaturate(VectorFormat vform) argument
591 UnsignedSaturate(VectorFormat vform) argument
610 Round(VectorFormat vform) argument
619 Uhalve(VectorFormat vform) argument
635 Halve(VectorFormat vform) argument
[all...]
H A Dinstructions-aarch64.h530 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
531 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
532 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
533 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
535 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
536 VectorFormat VectorFormatFillQ(VectorFormat vform);
537 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
538 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
539 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
541 unsigned LaneSizeInBitsFromFormat(VectorFormat vform);
659 static const VectorFormat vform[] = {kFormatUndefined, local
[all...]
H A Dsimulator-aarch64.cc521 VectorFormat vform) {
522 switch (vform) {
556 VectorFormat vform) {
557 switch (vform) {
2623 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; local
2640 fabs_(vform, ReadVRegister(fd), ReadVRegister(fn));
2642 LogVRegister(fd, GetPrintRegisterFormatFP(vform));
2646 fneg(vform, ReadVRegister(fd), ReadVRegister(fn));
2648 LogVRegister(fd, GetPrintRegisterFormatFP(vform));
2670 fsqrt(vform, r
520 GetPrintRegisterFormat( VectorFormat vform) argument
555 GetPrintRegisterFormatFP( VectorFormat vform) argument
2715 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; local
4342 VectorFormat vform = kFormatUndefined; local
[all...]

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