Searched refs:zero_reg (Results 1 - 25 of 36) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/x86/
H A Dvariance_avx2.c180 exp_dst_lo = _mm256_unpacklo_epi8(dst_reg, zero_reg); \
181 exp_dst_hi = _mm256_unpackhi_epi8(dst_reg, zero_reg); \
196 res_cmp = _mm256_cmpgt_epi16(zero_reg, sum_reg); \
219 const __m256i zero_reg = _mm256_setzero_si256(); local
228 exp_src_lo = _mm256_unpacklo_epi8(avg_reg, zero_reg);
229 exp_src_hi = _mm256_unpackhi_epi8(avg_reg, zero_reg);
232 exp_src_lo = _mm256_unpacklo_epi8(src_reg, zero_reg);
233 exp_src_hi = _mm256_unpackhi_epi8(src_reg, zero_reg);
247 const __m256i zero_reg = _mm256_setzero_si256(); local
258 exp_src_lo = _mm256_unpacklo_epi8(avg_reg, zero_reg);
291 const __m256i zero_reg = _mm256_setzero_si256(); local
329 const __m256i zero_reg = _mm256_setzero_si256(); local
380 const __m256i zero_reg = _mm256_setzero_si256(); local
419 const __m256i zero_reg = _mm256_setzero_si256(); local
470 const __m256i zero_reg = _mm256_setzero_si256(); local
525 const __m256i zero_reg = _mm256_setzero_si256(); local
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/external/v8/src/crankshaft/mips64/
H A Dlithium-codegen-mips64.cc782 __ Branch(&no_deopt, ne, a1, Operand(zero_reg));
955 __ Branch(&dividend_is_not_negative, ge, dividend, Operand(zero_reg));
957 __ dsubu(dividend, zero_reg, dividend);
961 Operand(zero_reg));
964 __ dsubu(dividend, zero_reg, dividend);
992 __ Branch(&remainder_not_zero, ne, result, Operand(zero_reg));
994 Operand(zero_reg));
1014 Operand(zero_reg));
1028 __ mov(result_reg, zero_reg);
1034 __ Branch(&done, ge, left_reg, Operand(zero_reg));
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H A Dlithium-codegen-mips64.h232 Register src1 = zero_reg,
233 const Operand& src2 = Operand(zero_reg));
236 Register src1 = zero_reg,
237 const Operand& src2 = Operand(zero_reg));
/external/v8/src/mips64/
H A Dassembler-mips64.cc93 0, // zero_reg
133 zero_reg,
606 // Traditional mips nop == sll(zero_reg, zero_reg, 0)
607 // When marking non-zero type, use sll(zero_reg, at, type)
611 Register nop_rt_reg = (type == 0) ? zero_reg : at;
613 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
1254 beq(zero_reg, zero_reg, offset);
1259 bgezal(zero_reg, offse
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H A Dcode-stubs-mips64.cc98 __ ctc1(zero_reg, FCSR);
116 __ Branch(&error, ne, scratch, Operand(zero_reg));
140 __ Movz(result_reg, zero_reg, scratch);
141 __ Branch(&done, eq, scratch, Operand(zero_reg));
150 __ Branch(&normal_exponent, le, result_reg, Operand(zero_reg));
151 __ mov(result_reg, zero_reg);
168 __ mov(input_high, zero_reg);
187 __ Branch(&pos_shift, ge, scratch, Operand(zero_reg));
190 __ Subu(scratch, zero_reg, scratch);
203 __ Subu(result_reg, zero_reg, input_hig
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H A Dcode-stubs-mips64.h100 masm->instr_at_put(pos, BNE | (zero_reg.code() << kRsShift) |
101 (zero_reg.code() << kRtShift) | (offset & kImm16Mask));
107 masm->instr_at_put(pos, BEQ | (zero_reg.code() << kRsShift) |
108 (zero_reg.code() << kRtShift) | (offset & kImm16Mask));
H A Dcodegen-mips64.cc70 __ bne(a6, zero_reg, &lastb);
79 __ bne(t8, zero_reg, &unaligned);
80 __ subu(a3, zero_reg, a0); // In delay slot.
83 __ beq(a3, zero_reg, &aligned); // Already aligned.
133 __ Branch(USE_DELAY_SLOT, &skip_pref, gt, v1, Operand(zero_reg));
227 __ Branch(&leave, le, a2, Operand(zero_reg));
246 __ beq(a3, zero_reg, &ua_chk16w);
299 __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg));
335 __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg));
534 __ beq(a2, zero_reg,
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H A Dmacro-assembler-mips64.cc238 Branch(&ok, eq, t8, Operand(zero_reg));
306 Branch(&ok, eq, at, Operand(zero_reg));
500 Branch(&done, ne, t8, Operand(zero_reg));
503 Ret(ne, t8, Operand(zero_reg));
536 nor(scratch, reg0, zero_reg);
1521 daddiu(rd, zero_reg, (j.imm64_ & kImm16Mask));
1523 ori(rd, zero_reg, (j.imm64_ & kImm16Mask));
1569 ori(rd, zero_reg, (j.imm64_ >> 16) & kImm16Mask);
1907 Branch(&msb_clear, ge, rs, Operand(zero_reg));
1958 Branch(&positive, ge, rs, Operand(zero_reg));
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H A Dmacro-assembler-mips64.h206 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \
207 const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
227 Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) {
533 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as
548 // Return <n> if we have a sll zero_reg, zero_reg, n
551 rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
552 rs == static_cast<uint32_t>(ToNumber(zero_reg)));
226 Ret(BranchDelaySlot bd, Condition cond = al, Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) argument
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/external/v8/src/crankshaft/mips/
H A Dlithium-codegen-mips.cc794 __ Branch(&no_deopt, ne, a1, Operand(zero_reg));
966 __ Branch(&dividend_is_not_negative, ge, dividend, Operand(zero_reg));
968 __ subu(dividend, zero_reg, dividend);
972 Operand(zero_reg));
975 __ subu(dividend, zero_reg, dividend);
1003 __ Branch(&remainder_not_zero, ne, result, Operand(zero_reg));
1005 Operand(zero_reg));
1025 Operand(zero_reg));
1039 __ mov(result_reg, zero_reg);
1045 __ Branch(&done, ge, left_reg, Operand(zero_reg));
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H A Dlithium-codegen-mips.h230 Register src1 = zero_reg,
231 const Operand& src2 = Operand(zero_reg));
234 Register src1 = zero_reg,
235 const Operand& src2 = Operand(zero_reg));
/external/v8/src/mips/
H A Dmacro-assembler-mips.cc222 Branch(&ok, eq, t8, Operand(zero_reg));
290 Branch(&ok, eq, at, Operand(zero_reg));
483 Branch(&done, ne, t8, Operand(zero_reg));
486 Ret(ne, t8, Operand(zero_reg));
518 nor(scratch, reg0, zero_reg);
993 subu(at, zero_reg, rt.rm());
1012 lw(zero_reg, rs);
1077 or_(tmp, zero_reg, tmp2);
1091 or_(dest, tmp, zero_reg);
1331 addiu(rd, zero_reg,
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H A Dcode-stubs-mips.cc100 __ ctc1(zero_reg, FCSR);
118 __ Branch(&error, ne, scratch, Operand(zero_reg));
142 __ Movz(result_reg, zero_reg, scratch);
143 __ Branch(&done, eq, scratch, Operand(zero_reg));
152 __ Branch(&normal_exponent, le, result_reg, Operand(zero_reg));
153 __ mov(result_reg, zero_reg);
170 __ mov(input_high, zero_reg);
189 __ Branch(&pos_shift, ge, scratch, Operand(zero_reg));
192 __ Subu(scratch, zero_reg, scratch);
205 __ Subu(result_reg, zero_reg, input_hig
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H A Dassembler-mips.cc115 0, // zero_reg
155 zero_reg,
634 // Traditional mips nop == sll(zero_reg, zero_reg, 0)
635 // When marking non-zero type, use sll(zero_reg, at, type)
639 Register nop_rt_reg = (type == 0) ? zero_reg : at;
641 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
1267 beq(zero_reg, zero_reg, offset);
1272 bgezal(zero_reg, offse
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H A Dcode-stubs-mips.h99 masm->instr_at_put(pos, BNE | (zero_reg.code() << kRsShift) |
100 (zero_reg.code() << kRtShift) | (offset & kImm16Mask));
106 masm->instr_at_put(pos, BEQ | (zero_reg.code() << kRsShift) |
107 (zero_reg.code() << kRtShift) | (offset & kImm16Mask));
H A Dcodegen-mips.cc70 __ bne(t2, zero_reg, &lastb);
79 __ bne(t8, zero_reg, &unaligned);
80 __ subu(a3, zero_reg, a0); // In delay slot.
83 __ beq(a3, zero_reg, &aligned); // Already aligned.
132 __ Branch(USE_DELAY_SLOT, &skip_pref, gt, v1, Operand(zero_reg));
226 __ Branch(&leave, le, a2, Operand(zero_reg));
245 __ beq(a3, zero_reg, &ua_chk16w);
298 __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg));
333 __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg));
532 __ beq(a2, zero_reg,
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/external/v8/src/ic/mips/
H A Dic-mips.cc44 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code());
57 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code()))) {
65 // If the delta is 0 the instruction is andi at, zero_reg, #0 which also
81 // Branch <target>, eq, at, Operand(zero_reg)
84 // Branch <target>, ne, at, Operand(zero_reg)
/external/v8/src/ic/mips64/
H A Dic-mips64.cc44 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code());
57 Assembler::GetRt(instr) == static_cast<uint32_t>(zero_reg.code()))) {
65 // If the delta is 0 the instruction is andi at, zero_reg, #0 which also
81 // Branch <target>, eq, at, Operand(zero_reg)
84 // Branch <target>, ne, at, Operand(zero_reg)
/external/v8/src/regexp/mips/
H A Dregexp-macro-assembler-mips.cc227 __ Branch(&fallthrough, eq, a1, Operand(zero_reg));
236 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg));
329 __ mov(a3, zero_reg);
349 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg));
376 __ Branch(&fallthrough, le, a1, Operand(zero_reg));
385 BranchOrBacktrack(on_no_match, gt, t5, Operand(zero_reg));
441 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c);
450 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c);
499 BranchOrBacktrack(on_bit_set, ne, a0, Operand(zero_reg));
579 BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg));
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/external/v8/src/regexp/mips64/
H A Dregexp-macro-assembler-mips64.cc263 __ Branch(&fallthrough, eq, a1, Operand(zero_reg));
272 BranchOrBacktrack(on_no_match, gt, t1, Operand(zero_reg));
365 __ mov(a3, zero_reg);
385 BranchOrBacktrack(on_no_match, eq, v0, Operand(zero_reg));
412 __ Branch(&fallthrough, eq, a1, Operand(zero_reg));
421 BranchOrBacktrack(on_no_match, gt, t1, Operand(zero_reg));
471 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c);
480 Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c);
529 BranchOrBacktrack(on_bit_set, ne, a0, Operand(zero_reg));
609 BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg));
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/external/v8/src/builtins/mips/
H A Dbuiltins-mips.cc80 Operand(zero_reg));
109 Operand(zero_reg));
148 __ Branch(&done_loop, lt, a3, Operand(zero_reg));
254 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg));
302 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg));
376 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg));
391 __ Branch(&symbol_descriptive_string, eq, t1, Operand(zero_reg));
392 __ Branch(&to_string, gt, t1, Operand(zero_reg));
451 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg));
467 __ Branch(&done_convert, eq, t1, Operand(zero_reg));
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/external/v8/src/builtins/mips64/
H A Dbuiltins-mips64.cc80 Operand(zero_reg));
109 Operand(zero_reg));
148 __ Branch(&done_loop, lt, a3, Operand(zero_reg));
252 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg));
300 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg));
375 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg));
390 __ Branch(&symbol_descriptive_string, eq, t1, Operand(zero_reg));
391 __ Branch(&to_string, gt, t1, Operand(zero_reg));
450 __ Branch(USE_DELAY_SLOT, &no_arguments, eq, a0, Operand(zero_reg));
466 __ Branch(&done_convert, eq, t1, Operand(zero_reg));
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/external/v8/src/compiler/mips64/
H A Dcode-generator-mips64.cc59 return zero_reg;
99 return Operand(zero_reg);
181 void Generate() final { __ mov(result_, zero_reg); }
394 Operand(zero_reg)); \
403 __ Or(kScratchReg, zero_reg, Operand(offset)); \
405 __ Branch(out_of_bounds, ne, kScratchReg, Operand(zero_reg)); \
511 __ Branch(USE_DELAY_SLOT, ool->entry(), eq, at, Operand(zero_reg)); \
537 __ Branch(USE_DELAY_SLOT, ool->entry(), eq, at, Operand(zero_reg)); \
1006 __ Nor(i.OutputRegister(), i.InputRegister(0), zero_reg);
1017 __ Nor(i.OutputRegister(), i.InputRegister(0), zero_reg);
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/external/v8/src/full-codegen/mips/
H A Dfull-codegen-mips.cc38 // marker is a andi zero_reg, rx, #yyyy instruction, and rx * 0x0000ffff + yyyy
41 // The marker instruction is effectively a NOP (dest is zero_reg) and will
63 __ BranchShort(target, eq, at, Operand(zero_reg));
74 __ BranchShort(target, ne, at, Operand(zero_reg));
81 __ andi(zero_reg, reg, delta_to_patch_site % kImm16Mask);
181 __ Branch(&loop_header, ne, a2, Operand(zero_reg));
349 __ mov(v0, zero_reg);
388 __ slt(at, a3, zero_reg);
389 __ beq(at, zero_reg, &ok);
418 __ Branch(&ok, ge, a3, Operand(zero_reg));
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/external/v8/src/full-codegen/mips64/
H A Dfull-codegen-mips64.cc38 // marker is a andi zero_reg, rx, #yyyy instruction, and rx * 0x0000ffff + yyyy
41 // The marker instruction is effectively a NOP (dest is zero_reg) and will
63 __ BranchShort(target, eq, at, Operand(zero_reg));
74 __ BranchShort(target, ne, at, Operand(zero_reg));
81 __ andi(zero_reg, reg, delta_to_patch_site % kImm16Mask);
180 __ Branch(&loop_header, ne, a2, Operand(zero_reg));
349 __ mov(v0, zero_reg);
388 __ slt(at, a3, zero_reg);
389 __ beq(at, zero_reg, &ok);
418 __ Branch(&ok, ge, a3, Operand(zero_reg));
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