Searched refs:shamt (Results 1 - 5 of 5) sorted by relevance

/art/compiler/utils/mips64/
H A Dassembler_mips64.h494 void Sll(GpuRegister rd, GpuRegister rt, int shamt);
495 void Srl(GpuRegister rd, GpuRegister rt, int shamt);
496 void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
497 void Sra(GpuRegister rd, GpuRegister rt, int shamt);
502 void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
503 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
504 void Drotr(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
505 void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
506 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
507 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS6
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H A Dassembler_mips64.cc100 int shamt, int funct) {
108 shamt << kShamtShift |
114 int shamt, int funct) {
121 shamt << kShamtShift |
127 int shamt, int funct) {
134 shamt << kShamtShift |
507 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { argument
508 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
511 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { argument
512 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt,
99 EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct) argument
113 EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct) argument
126 EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct) argument
515 Rotr(GpuRegister rd, GpuRegister rt, int shamt) argument
519 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument
539 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument
543 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument
547 Drotr(GpuRegister rd, GpuRegister rt, int shamt) argument
551 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument
555 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument
559 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument
563 Drotr32(GpuRegister rd, GpuRegister rt, int shamt) argument
567 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument
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H A Dassembler_mips64_test.cc2600 void Dsll(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { argument
2601 regs_[rd] = regs_[rt] << (shamt & 0x1f);
2603 void Dsll32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { argument
2604 regs_[rd] = regs_[rt] << (32 + (shamt & 0x1f));
2606 void Dsrl(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { argument
2607 regs_[rd] = regs_[rt] >> (shamt & 0x1f);
2609 void Dsrl32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { argument
2610 regs_[rd] = regs_[rt] >> (32 + (shamt & 0x1f));
/art/compiler/utils/mips/
H A Dassembler_mips.cc259 int shamt,
268 shamt << kShamtShift |
642 void MipsAssembler::Sll(Register rd, Register rt, int shamt) { argument
643 CHECK(IsUint<5>(shamt)) << shamt;
644 DsFsmInstr(EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x00)).GprOuts(rd).GprIns(rt);
647 void MipsAssembler::Srl(Register rd, Register rt, int shamt) { argument
648 CHECK(IsUint<5>(shamt)) << shamt;
649 DsFsmInstr(EmitR(0, static_cast<Register>(0), rt, rd, shamt,
255 EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) argument
652 Rotr(Register rd, Register rt, int shamt) argument
657 Sra(Register rd, Register rt, int shamt) argument
701 ShiftAndAdd(Register dst, Register src_idx, Register src_base, int shamt, Register tmp) argument
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H A Dassembler_mips.h343 void Sll(Register rd, Register rt, int shamt);
344 void Srl(Register rd, Register rt, int shamt);
345 void Rotr(Register rd, Register rt, int shamt); // R2+
346 void Sra(Register rd, Register rt, int shamt);
354 void ShiftAndAdd(Register dst, Register src_idx, Register src_base, int shamt, Register tmp = AT);
1680 uint32_t EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);

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