H A D | assembler_mips64.cc | 100 int shamt, int funct) { 108 shamt << kShamtShift | 114 int shamt, int funct) { 121 shamt << kShamtShift | 127 int shamt, int funct) { 134 shamt << kShamtShift | 507 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { argument 508 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00); 511 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { argument 512 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 99 EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct) argument 113 EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct) argument 126 EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct) argument 515 Rotr(GpuRegister rd, GpuRegister rt, int shamt) argument 519 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument 539 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument 543 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument 547 Drotr(GpuRegister rd, GpuRegister rt, int shamt) argument 551 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument 555 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument 559 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument 563 Drotr32(GpuRegister rd, GpuRegister rt, int shamt) argument 567 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument [all...] |