| a556e6ba500ba54d1ca90d6a947dd962d9c287c7 |
|
13-Dec-2017 |
Lena Djokic <Lena.Djokic@mips.com> |
MIPS: InstructionCodeGeneratorMIPS*::DivRemByPowerOfTwo()
Replace [d]sll+[d]srl with [d]ins on R2+.
Change-Id: I7587e46c47c8ce413d81a5c6c29d91e32a14d855
|
| 72aba71d00dd0c420a6ff196066e9378339d46d8 |
|
30-Oct-2017 |
Lena Djokic <Lena.Djokic@mips.com> |
MIPS: Add asub_s/u.df
These instructions are needed for implementing Sum-of-Abs-Differences
visitor.
Test: mma test-art-host-gtest
Change-Id: Ie708f30a450b0558215f59f21bb49b68c852f247
|
| 3309c01e55821f693e3b9cec0ef24969edf2528f |
|
13-Oct-2017 |
Lena Djokic <Lena.Djokic@imgtec.com> |
MIPS: Introduce a few MSA instructions
These instructions are needed for SIMD reduction.
Also added assembler tests for each instruction.
Test: mma test-art-host-gtest
Change-Id: I0f02618a14b4cbcc3b81ce51dd2586fa4cdbfd18
|
| e764d2e50c544c2cb98ee61a15d613161ac6bd17 |
|
05-Oct-2017 |
Vladimir Marko <vmarko@google.com> |
Use ScopedArenaAllocator for register allocation.
Memory needed to compile the two most expensive methods for
aosp_angler-userdebug boot image:
BatteryStats.dumpCheckinLocked() : 25.1MiB -> 21.1MiB
BatteryStats.dumpLocked(): 49.6MiB -> 42.0MiB
This is because all the memory previously used by Scheduler
is reused by the register allocator; the register allocator
has a higher peak usage of the ArenaStack.
And continue the "arena"->"allocator" renaming.
Test: m test-art-host-gtest
Test: testrunner.py --host
Bug: 64312607
Change-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01
|
| caa31e732bc9bb0007c39c504b109a4867ee5dd9 |
|
15-Sep-2017 |
Aart Bik <ajcbik@google.com> |
Add repeat support for memory addresses.
Rationale:
This enables exhaustive testing of instructions
that use memory addresses. First use case of
the generics is x86.
Bug: 18380245
Bug: 18380559
Bug: 18380348
Test: assembler_x86[_64]_test
Change-Id: Ib0ad6fa65477b0c6fc04642ff980a4b9543d16d5
|
| 2dec927e60395210946e5b9dbaa03111dad2466a |
|
02-Aug-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: Implement HSelect
Test: mma test-art-host-gtest
Test: mma test-art-target-gtest in QEMU (MIPS64R6)
Test: ./testrunner.py --target --optimizing in QEMU (MIPS64R6)
Change-Id: I633fc479e0ca61b7d49b4c36fbe5db9a94da535d
|
| 0cab65610a6a984a94ef4c3f232fe0273e78d95b |
|
26-Jul-2017 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Eliminate hard-coded offsets in branches
The bulk of the change is in the assemblers and their
tests.
The main goal is to introduce "bare" branches to labels
(as opposed to the existing bare branches with relative
offsets, whose direct use we want to eliminate).
These branches' delay/forbidden slots are filled
manually and these branches do not promote to long (the
branch target must be within reach of the individual
branch instruction).
The secondary goal is to add more branch tests (mainly
for bare vs non-bare branches and a few extra) and
refactor and reorganize the branch test code a bit.
The third goal is to improve idiom recognition in the
disassembler, including branch idioms and a few others.
Further details:
- introduce bare branches (R2 and R6) to labels, making
R2 branches available for use on R6
- make use of the above in the code generators
- align beqz/bnez with their GNU assembler encoding to
simplify and shorten the test code
- update the CFI test because of the above
- add trivial tests for bare and non-bare branches
(addressing existing debt as well)
- add MIPS32R6 tests for long beqc/beqzc/bc (debt)
- add MIPS64R6 long beqzc test (debt)
- group branch tests together
- group constant/literal/address-loading tests together
- make the disassembler recognize:
- b/beqz/bnez (beq/bne with $zero reg)
- nal (bltzal with $zero reg)
- bal/bgezal (bal = bgezal with $zero reg)
- move (or with $zero reg)
- li (ori/addiu with $zero reg)
- dli (daddiu with $zero reg)
- disassemble 16-bit immediate operands (in andi, ori,
xori, li, dli) as signed or unsigned as appropriate
- drop unused instructions (bltzl, bltzall, addi) from
the disassembler as there are no plans to use them
Test: test-art-host-gtest
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: test-art-target-gtest
Test: testrunner.py --target --optimizing
Test: same tests as above on CI20
Test: booted MIPS32R2 in QEMU
Change-Id: I62b74a6c00ce0651528114806ba24a59ba564a73
|
| b3d79e430a4c0a447121890514cdee48e4675df4 |
|
25-Jul-2017 |
Lena Djokic <Lena.Djokic@imgtec.com> |
MIPS: Add maddv/msubv MSA instructions
Added maddv.df, msubv.df, fmadd.df and fmsub.df MSA instructions
in assembler, disassembler and tests.
These instructions are needed for multiplyaccumulate support in
ART Vectorizer.
Test: mma test-art-host-gtest
Change-Id: Idef7faaeed47f1fef83fa58676ce664afe24ffe8
|
| 658263ec2fdc7758dd73c41cdcf0babcdef1e48d |
|
07-Jun-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: Add min/max MSA instructions
Added min_s.df, max_s.df, min_u.df, max_u.df, fmin.df and fmax.df MSA
instructions in assembler, disassembler and tests.
These instructions are needed for min/max support in ART Vectorizer.
Test: mma test-art-host-gtest
Change-Id: I4e8dd18ca501ac09d938a49388e4a43116660ec9
|
| 3837011236058617292bee831708449e5100c08c |
|
10-May-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: Add ilvr.df MSA instructions
These instructions are needed for compressed string support
in ART Vectorizer.
Test: mma test-art-host-gtest
Change-Id: I269473bb8bcce5aba72201380bb71860e5498d73
|
| d8b6a53074be7d6b98c651ed8d2127f089da39a6 |
|
20-Apr-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: Saves 128-bit vector registers along SuspendCheckSlowPath
We need to save 128 bits of data. This is only done for vector
registers that are live, so overhead is not too big.
Test: mma test-art-host-gtest
Test: ./testrunner.py --optimizing --target in QEMU (MIPS64)
Change-Id: I2cdfeb8056dc5ef35c92f589d8c0399c41d913b2
|
| 80248d7ba4e952f0e0110c036b48963080ef9470 |
|
20-Apr-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: Add add_a.df, ave_s/u.df and aver_s/u.df MSA instructions
These instructions are needed for implementing VecAbs and
VecHalvingAdd visitors.
Test: mma test-art-host-gtest
Change-Id: Idaec03ea32bbeaba9cb7476dd0f740aa4d9cfa70
|
| 3f44403fb5b6c9c6176339ab5888e97d0b617746 |
|
31-Mar-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: Add ldi.df MSA instruction
Also fixes RepeatTemplatedRegisterImmBits template.
Test: mma test-art-host-gtest
Change-Id: Ib23f8a65ba924623f8c3a2d75d4ec4491d18feb0
|
| 27af937fb4356ed34f175b14c4425fc95f5f8a19 |
|
15-Mar-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: Check for MSA presence in each MSA instruction
Test: mma test-art-host-gtest
Change-Id: I123fe1e33de13af6a2b2a76f37f7ad23004a81c0
|
| 5a9e51d39ed3d1015f20b3d12b35747612cca40e |
|
16-Mar-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
Revert "Revert "Introduce a number of MSA instructions for MIPS64""
This reverts commit 219bf253e5158c4f3438e70864b8bf7235c1e193.
Fixed memory leak in assembler_mips64_test.cc.
Test: mma valgrind-test-art-host-gtest-assembler_mips64_test64
Change-Id: I238833fd4555623c2716432fc67eab7696f1e28e
|
| c3fec0cc6fc9698f9fbd39ea817fd7dc64643fcb |
|
15-Dec-2016 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS64: Adjust Base and Offset
Minimize the number of statements needed to load/store data at an
arbitrary offset from a base register.
Test: test-art-host-gtest
Test: ART_TEST_OPTIMIZING=true test-art-target-run-test
Change-Id: I76cc4b715dbb5b41c76b3c537fbd62bae8409bc0
|
| 219bf253e5158c4f3438e70864b8bf7235c1e193 |
|
15-Mar-2017 |
Aart Bik <ajcbik@google.com> |
Revert "Introduce a number of MSA instructions for MIPS64"
This reverts commit dcabc8b740bf3066d59348ffdf21c164d2b27cb4.
Reason:
FAILING TESTS
valgrind-test-art-host-gtest-assembler_mips64_test32
ninja: build stopped: subcommand failed.
19:36:36 ninja failed with: exit status 1
make: *** [run_soong_ui] Error 1
Change-Id: If658375528d2a0f34bb6b22b6565fab1d863b3f5
|
| dcabc8b740bf3066d59348ffdf21c164d2b27cb4 |
|
10-Mar-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
Introduce a number of MSA instructions for MIPS64
Added a number of MSA (The MIPS SIMD Architecture) instructions.
Added assembler tests for each instruction.
Made necessary changes in disassembler for these instructions.
Test: mma test-art-host-gtest
Change-Id: I380f02c6ae5424a96ad999037153228acb07a108
|
| ba89c34e94a82f0a6904dcc62caa6aa7bb14c12c |
|
10-Mar-2017 |
Tijana Jakovljevic <tijana.jakovljevic@imgtec.com> |
MIPS64: Improve storing of constants in fields and array elements
Test: booted MIPS64 in QEMU
Test: mma test-art-target-run-test
Test: mma test-art-host-gtest-assembler_mips64_test
Change-Id: I8e0002166174eebea1309358eb9d96f34eee3225
|
| c061de1236e98fdd34d0214a9bbcc0e2149ff226 |
|
14-Feb-2017 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Implement heap poisoning in ART's Optimizing compiler.
This is in preparation for read barrier support.
Bug: 12687968
Test: test-art-host-gtest
Test: booted MIPS32R2 in QEMU
Test: test-art-target
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: test-art-target (both MIPS64R6 and MIPS32R6)
Note: built with ART_HEAP_POISONING=true.
Change-Id: I0e6e04ff8de2fc8ca6126388409fa218e6920734
|
| 95f271496da7421021ccb9845726a94cd5eaa914 |
|
20-Jan-2017 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS64: Extend assembler_mips64_test
Add tests for several existing instructions.
Test: mma test-art-host-gtest-assembler_mips64_test
Change-Id: I1505dc0cf019de2afedc9648e3fd41e7fd051861
|
| 0960ac5a5a255bb3e8418e185914243aeef54a7c |
|
21-Dec-2016 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Implement table-based packed switch
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: test-art-target-run-test-optimizing (MIPS64R6) in QEMU
Test: test-art-host-gtest
Change-Id: I333dca43fca57ae7e6021bb84585487c889417c3
|
| f63f569eeefe3907c48a175494a2a0ba351b641a |
|
14-Dec-2016 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Improve string and class loads.
This adds most kinds of string/class loads.
JIT string/class loads are TBD separately.
This also fixes Mips64Assembler::LoadLabelAddress()
(adding a constant to a 64-bit address must be done
using daddiu, not addiu).
Test: test-art-host-gtest
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: "make -j1 ART_TEST_DEFAULT_COMPILER=false ART_TEST_OPTIMIZING=true
ART_TEST_INTERPRETER=false ART_TEST_JIT=false
ART_TEST_PIC_TEST=true test-art-target-run-test64"
Change-Id: I1f94ece4cd202382c11167e1ed958e9d08d92822
|
| 36073947d2edb04e69ad0b20ec9de8c0712b8fd2 |
|
14-Dec-2016 |
Vladimir Marko <vmarko@google.com> |
Fix AssemblerMIPS64Test.LongBalc() running out of memory.
Pre-allocate the necessary buffer because the reallocation
strategy doesn't work well for a test of this size.
Test: m test-art-host-gtest-assembler_mips64_test
Change-Id: I16bc75f0ae83a62e5f3ed2cd8228dd40f0eb9524
|
| 19f6c696bbb7a17d8ac521b316c40f9cbef32151 |
|
01-Dec-2016 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Improve method invocation.
Improvements include:
- support for all kinds of method loads and static/direct calls
- 32-bit and 64-bit literals for the above and future work
- shorter instruction sequences for recursive static/direct calls
Also:
- include the MIPS64 dinsu instruction (missed earlier) and minor
clean-up in the disassembler
- properly prefix constant names with 'k' in relative patcher tests
Test: test-art-host-gtest
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: "make -j1 ART_TEST_DEFAULT_COMPILER=false ART_TEST_OPTIMIZING=true
ART_TEST_INTERPRETER=false ART_TEST_JIT=false
ART_TEST_PIC_TEST=true test-art-target-run-test64"
Change-Id: I19876fa5316b68531af7dfddfce90d2068433116
|
| e36605910cb13da1440fb9d7a8293842a9209c97 |
|
09-Nov-2016 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS64: java.lang.String.getChars
Test: run-test --64 --optimizing 020-string
Test: run-test --64 020-string
Test: run-test --64 --no-prebuild --optimizing 020-string
Test: run-test --64 --no-prebuild 020-string
Test: run-test --64 --optimizing 082-inline-execute
Test: run-test --64 082-inline-execute
Test: run-test --64 --no-prebuild --optimizing 082-inline-execute
Test: run-test --64 --no-prebuild 082-inline-execute
Test: mma -j2 ART_TEST_OPTIMIZING=true test-art-target-run-test
Test: mma test-art-target-gtest -j2
Test: booted MIPS64R6 emulator.
Note: All tests run against MIPS64 QEMU.
Change-Id: I48b9a87465f2516044a2e4f598cc5dce56b0d1c9
|
| 2e965aca73bacf84123b5c53bb0904b13b48e428 |
|
04-Nov-2016 |
Andreas Gampe <agampe@google.com> |
ART: Use references in assembler tests
Move parameters to const references.
Bug: 32619234
Test: m
Change-Id: Ib68bdc313b91fee1e9e4e1e794eeca630837b005
|
| c733dca42157cafe8751b558f1f8ab65efdeaa63 |
|
14-May-2016 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS64: Improve non-trivial 64-bit constant loading.
- Add special case where the upper 32 bits of the constant are equal to
the lower 32 bits of the constant. Use the "dinsu" instruction to
replicate the bottom 32 bits into the top 32 bits.
- Test output of LoadConst32()/LoadConst64() against various test
constants.
o Make the implementation of LoadConst64() into a template.
o Using the template code for LoadConst64() implement test
cases which simulate the computation of the value which the
generated code sequence is actually supposed to load.
o Add conditionally compiled code to verify that all of the
various data paths through the LoadConst64() function
actually get exercised.
Test: Booted MIPS64 in QEMU, and ran assembler tests.
Change-Id: Ie1ec050e65c666168a9ea582bae9fda97e4cf36a
|
| d967266cdfc8011c81ba6e9857a247c4a73bd0fc |
|
03-Sep-2015 |
Lazar Trsic <Lazar.Trsic@imgtec.com> |
MIPS64: Remove unaligned memory access from art generated code
Unaligned memory access was caused by sd, ld, ldc1 and sdc1
instructions. Check if offset is unaligned and replace it
with two 32 bit memory accesses, if so.
Added assembler tests for new instructions, as well as assembler
tests for LoadFromOffset, LoadFpuFromOffset, StoreToOffset and
StoreFpuToOffset.
Change-Id: I0228a4a2ce6c801eeb5b46952b8330e14468deb3
|
| baf60b7cceb3968ae36540e2f7f92cec3805f6ed |
|
23-Dec-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Improve conversion between ints and floats.
Change-Id: I767fe9623cc14e8480c31e305725eb5221cac282
|
| 299a93993fb8f3efbf0465cf674d80c3bcfdc66c |
|
09-Dec-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Fuse long and FP compare & condition in Optimizing.
Bug: 25559148
Change-Id: I2d14ac75460a76848c71c08cffff6d7a18f5f580
|
| a0e87b0a97fadd54540ec7e8331b61bebd82d378 |
|
25-Sep-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS64: Support short and long branches
Change-Id: I618c960bd211048166d9fde78d4106bd3ca42b3a
|
| 98a73e14554301ccd6d05f8a893b59b1d8b5eaeb |
|
19-Oct-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS64: Add tests for rotation, and shift instructions
Change-Id: I5611cb5c638c6be193739cbe859cb4ff4074a5fa
|
| 5141763acd9ca2ddb2ee6bcc742d6d2a2aebd7df |
|
02-Oct-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS64: Additional assember tests:
- MOV.fmt - NEG.fmt - CVT.D.fmt - CVT.S.fmt
- JALR - SLL - SRL - SRA
- DSLL - DSRA - DSRL - DSLL32
- DSRL32 - DSRA32
Change-Id: Ib15ac72128805a9bca707211359191e32d95d5d7
|
| dbce0d738e9d7956d2bd73e932a0fdd28f2229b4 |
|
17-Sep-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS64r6 Assembler Tests
Assembler tests for:
- SQRT.fmt - ABS.fmt - ROUND.L.fmt - ROUND.W.fmt
- CEIL.L.fmt - CEIL.W.fmt - FLOOR.L.fmt - FLOOR.W.fmt
- SEL.fmt - RINT.fmt - CLASS.fmt - MIN.fmt
- MAX.fmt - cvt.d.l - BITSWAP - DBITSWAP
- DSBH - DSHD - WSBH - ROTR
- SELEQZ - SELNEZ - CLZ - CLO
- DCLZ - DCLO - SC - SCD
- LL - LLD
These are the assembler instructions which were added to support
intrinsic functions on MIPS64. Tests for additional assembler
instructions will follow.
Support added to the testing infrastructure for:
- Assembler instructions which use three registers; previously
instructions were limited to one, or two, registers.
- Immediate values which have their sizes specified by the number of
bits required to store them rather than the number of bytes, in both
signed and unsigned versions.
Change-Id: I38c07dcbf2539825b25bed13aac05a26fa594b0b
|