/external/eigen/Eigen/src/Geometry/ |
H A D | Umeyama.h | 134 TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1); local 143 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose(); 151 Rt.col(m).head(m) = dst_mean; 152 Rt.col(m).head(m).noalias() -= c*Rt.topLeftCorner(m,m)*src_mean; 153 Rt.block(0,0,m,m) *= c; 157 Rt.col(m).head(m) = dst_mean; 158 Rt.col(m).head(m).noalias() -= Rt.topLeftCorner(m,m)*src_mean; 161 return Rt; [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCompound.cpp | 207 MCOperand Rs, Rt; local 217 Rt = L.getOperand(0); 222 CompoundInsn->addOperand(Rt); 228 Rt = L.getOperand(0); 234 CompoundInsn->addOperand(Rt); 243 Rt = L.getOperand(2); 249 CompoundInsn->addOperand(Rt); 256 Rt = L.getOperand(2); 262 CompoundInsn->addOperand(Rt); 269 Rt [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 326 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo 330 MCOperand &Rt = Inst.getOperand(3); local 331 assert (Rt.isReg() && "Expected register and none was found"); 332 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 337 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); 341 MCOperand &Rt = Inst.getOperand(2); local 342 assert (Rt.isReg() && "Expected register and none was found"); 343 unsigned Reg = RI->getEncodingValue(Rt.getReg()); 348 Rt 353 MCOperand &Rt = Inst.getOperand(2); local 554 MCOperand &Rt = Inst.getOperand(1); local [all...] |
H A D | HexagonInstrInfo.cpp | 1241 unsigned Rt = Op3.getReg(); local 1248 .addReg(Pu, (Rd == Rt) ? K1 : 0) 1250 if (Rd != Rt) 1253 .addReg(Rt, K3); 3757 // memw(Rs+#u4:2) = Rt 3758 // memb(Rs+#u4:0) = Rt 3761 // memw(r29+#u5:2) = Rt 3769 // memw(Rs+#u4:2) = Rt 3776 // memb(Rs+#u4:0) = Rt 3786 // memh(Rs+#u3:1) = Rt [all...] |
/external/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 537 uint32_t Rt = fieldFromInstruction(insn, 16, 5); local 541 if (Rs >= Rt) { 544 } else if (Rs != 0 && Rs < Rt) { 553 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); 573 uint32_t Rt = fieldFromInstruction(insn, 16, 5); local 577 if (Rs >= Rt) { 580 } else if (Rs != 0 && Rs < Rt) { 589 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); 610 uint32_t Rt = fieldFromInstruction(insn, 16, 5); local 614 if (Rt 652 uint32_t Rt = fieldFromInstruction(insn, 16, 5); local 690 uint32_t Rt = fieldFromInstruction(insn, 16, 5); local 736 uint32_t Rt = fieldFromInstruction(insn, 16, 5); local 1062 unsigned Rt = fieldFromInstruction(Insn, 16, 5); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 437 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); local 442 assert(isARMLowRegister(Rt)); 455 .addReg(Rt, IsStore ? 0 : RegState::Define);
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H A D | ARMBaseInstrInfo.cpp | 2820 unsigned Rt = MI.getOperand(0).getReg(); local 2822 return (Rt == Rm) ? 4 : 3; 2827 unsigned Rt = MI.getOperand(0).getReg(); local 2829 if (Rt == Rm) 2857 unsigned Rt = MI.getOperand(0).getReg(); local 2861 if (Rt == Rm) 2869 unsigned Rt = MI.getOperand(0).getReg(); local 2871 return (Rt == Rm) ? 3 : 2; 2892 unsigned Rt = MI.getOperand(0).getReg(); local 2893 if (Rt 2907 unsigned Rt = MI.getOperand(0).getReg(); local 2933 unsigned Rt = MI.getOperand(0).getReg(); local 2943 unsigned Rt = MI.getOperand(0).getReg(); local 2980 unsigned Rt = MI.getOperand(0).getReg(); local [all...] |
/external/capstone/arch/AArch64/ |
H A D | AArch64Disassembler.c | 943 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 951 // Rt is an immediate in prefetch. 952 MCOperand_CreateImm0(Inst, Rt); 962 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 969 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 973 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 977 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 981 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 985 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 989 DecodeFPR8RegisterClass(Inst, Rt, Add 1007 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1193 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1269 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1636 uint64_t Rt = fieldFromInstruction(insn, 0, 5); local [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 838 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 848 // Rt is an immediate in prefetch. 849 Inst.addOperand(MCOperand::createImm(Rt)); 859 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 866 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 870 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 874 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 878 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 882 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 886 DecodeFPR8RegisterClass(Inst, Rt, Add 899 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1084 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1167 unsigned Rt = fieldFromInstruction(insn, 0, 5); local 1536 uint64_t Rt = fieldFromInstruction(insn, 0, 5); local [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 603 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 607 if (Rs >= Rt) { 610 } else if (Rs != 0 && Rs < Rt) { 621 Rt))); 631 InsnType Rt = fieldFromInstruction(insn, 21, 5); local 635 if (Rs >= Rt) { 638 Rt))); 641 } else if (Rs != 0 && Rs < Rt) { 646 Rt))); 650 Rt))); 673 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 701 InsnType Rt = fieldFromInstruction(insn, 21, 5); local 744 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 789 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 831 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 880 InsnType Rt = fieldFromInstruction(insn, 16, 5); local 1808 unsigned Rt = fieldFromInstruction(Insn, 16, 5); local 2286 InsnType Rt = fieldFromInstruction(insn, 21, 5); local 2332 InsnType Rt = fieldFromInstruction(insn, 21, 5); local [all...] |
/external/pdfium/third_party/lcms/src/ |
H A D | cmspcs.c | 647 cmsFloat64Number Rt = -sin(2 * RADIANS(delta_ro)) * Rc; local 652 Rt*(delta_C/(Sc * Kc)) * (delta_H / (Sh * Kh)));
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/external/v8/src/arm/ |
H A D | disasm-arm.cc | 321 } else if (format[1] == 't') { // 'rt: Rt register 1395 // vmov: Sn = Rt 1396 // vmov: Rt = Sn 1422 // Qd = vdup.size(Qd, Rt) 1423 // vmov.size: Dd[i] = Rt 1424 // vmov.sign.size: Rt = Dn[i] 1571 int Rt = instr->RtValue(); local 1573 "vdup.%i q%d, r%d", size, Vd, Rt); 1758 // Dm = vmov(Rt, Rt2) 1759 // <Rt, Rt [all...] |
/external/spirv-llvm/lib/SPIRV/ |
H A D | SPIRVInternal.h | 341 const static char Rt[] = "rt"; member in namespace:SPIRV::kSPIRVPostfix
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1341 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 1349 // On stores, the writeback operand precedes Rt. 1366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1369 // On loads, the writeback operand comes after Rt. 1400 if (writeback && (Rn == 15 || Rn == Rt)) 1484 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 1496 // For {LD,ST}RD, Rt must be even, else undefined. 1504 if (Rt & 0x1) return MCDisassembler::Fail; 1516 // On stores, the writeback operand precedes Rt. 1532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Addres 2852 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 2984 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 3237 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 3261 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); local 3288 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 3313 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 3341 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 3366 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 3910 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 3936 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 3990 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local 4027 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); local [all...] |
/external/swiftshader/third_party/subzero/src/ |
H A D | IceAssemblerMIPS32.cpp | 210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); local 213 Opcode |= Rt << 16; 221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); local 225 Opcode |= Rt << 16; 236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); local 249 Opcode |= Rt << 16; 272 const IValueT Rt local 286 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); local 346 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); local 359 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); local 668 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui"); local 687 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "ldc1"); local 747 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "lwc1"); local 821 const IValueT Rt = 0; // $0 local 1071 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "sdc1"); local 1125 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "swc1"); local 1152 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "teq"); local 1231 IValueT Rt = encodeGPRegister(OpRt, "Rt", "branch"); local [all...] |
/external/vixl/src/aarch64/ |
H A D | assembler-aarch64.h | 2610 static Instr Rt(CPURegister rt) { function in class:vixl::aarch64::Assembler
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/external/capstone/arch/ARM/ |
H A D | ARMDisassembler.c | 1519 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 1528 // On stores, the writeback operand precedes Rt. 1545 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1548 // On loads, the writeback operand comes after Rt. 1578 if (writeback && (Rn == 15 || Rn == Rt)) 1668 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 1677 unsigned Rt2 = Rt + 1; 1681 // For {LD,ST}RD, Rt must be even, else undefined. 1689 if (Rt & 0x1) S = MCDisassembler_SoftFail; 1701 if (writeback && (Rn == 15 || Rn == Rt || R 3338 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 3411 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 3476 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 3542 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 3581 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 3734 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4112 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4135 unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); local 4161 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4187 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4215 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4241 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4799 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4826 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4874 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4911 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 4974 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); local 5067 unsigned Rt = fieldFromInstruction_4(Val, 12, 4); local 5098 unsigned Rt = fieldFromInstruction_4(Val, 12, 4); local [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1476 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 1484 // On stores, the writeback operand precedes Rt. 1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1504 // On loads, the writeback operand comes after Rt. 1535 if (writeback && (Rn == 15 || Rn == Rt)) 1624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 1633 unsigned Rt2 = Rt + 1; 1637 // For {LD,ST}RD, Rt must be even, else undefined. 1645 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1657 if (writeback && (Rn == 15 || Rn == Rt || R 3360 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 3443 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 3527 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 3607 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 3645 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 3801 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4231 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4253 unsigned Rt = fieldFromInstruction(Insn, 0, 4); local 4278 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4303 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4331 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4356 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4930 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 4956 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5003 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5040 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5098 unsigned Rt = fieldFromInstruction(Insn, 12, 4); local 5246 unsigned Rt = fieldFromInstruction(Val, 12, 4); local 5276 unsigned Rt = fieldFromInstruction(Val, 12, 4); local [all...] |
/external/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1584 MCOperand &Rt = Inst.getOperand(1); local 1587 TmpInst.addOperand(Rt); 1588 TmpInst.addOperand(Rt); 1598 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)" 2033 MCOperand &Rt = Inst.getOperand(2); local 2034 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); 2040 Rt.setReg(matchRegister(RegPair)); 2046 Rt.setReg(matchRegister(RegPair)); 2055 MCOperand &Rt = Inst.getOperand(3); local 2056 unsigned int RegNum = RI->getEncodingValue(Rt 2080 MCOperand &Rt = Inst.getOperand(2); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 2805 // Rt, Rt2 2825 // Rt, Rt2 2946 // Rt 2965 // Rt 2986 // Rt 3005 // Rt 3022 // Rt, Rt2 3042 // Rt, Rt2 4044 // Rt2 must be Rt + 1. 4045 unsigned Rt local 4054 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); local 4065 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); local [all...] |
/external/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 4029 // the intrinsic has 4 because Rt and Rt2 4041 Value *Rt = Builder.CreateTruncOrBitCast(RtAndRt2, Int32Ty); local 4045 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); 4070 Value *Rt = Builder.CreateExtractValue(RtAndRt2, 1); local 4072 Rt = Builder.CreateZExt(Rt, Int64Ty); 4076 RtAndRt2 = Builder.CreateShl(Rt, ShiftCast, "shl", true);
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 3442 // the Rt == Rt2. All of those are undefined behaviour. 3449 unsigned Rt = Inst.getOperand(1).getReg(); local 3452 if (RI->isSubRegisterEq(Rn, Rt)) 3466 unsigned Rt = Inst.getOperand(0).getReg(); local 3468 if (Rt == Rt2) 3469 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt"); 3479 unsigned Rt = Inst.getOperand(1).getReg(); local 3481 if (Rt == Rt2) 3482 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt"); 3495 unsigned Rt local 3528 unsigned Rt = Inst.getOperand(1).getReg(); local 3547 unsigned Rt = Inst.getOperand(1).getReg(); local [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 6041 unsigned Rt = MRI->getEncodingValue(Reg1); local 6044 // Rt2 must be Rt + 1 and Rt must be even. 6045 if (Rt + 1 != Rt2 || (Rt & 1)) { 6227 // Rt can't be R14. 6230 "Rt can't be R14"); 6232 const unsigned Rt = MRI->getEncodingValue(RtReg); local 6233 // Rt must be even-numbered. 6234 if ((Rt 6260 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); local 6277 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); local 6287 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local 6305 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); local 6328 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); local [all...] |