Searched refs:RAX (Results 1 - 25 of 48) sorted by relevance

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/external/strace/linux/x86_64/
H A Dset_error.c20 return upoke(tcp, 8 * RAX, rval);
41 return upoke(tcp, 8 * RAX, rval);
H A Duserent.h11 XLAT(8*RAX),
/external/kernel-headers/original/uapi/asm-x86/asm/
H A Dptrace-abi.h44 #define RAX 80 macro
/external/llvm/test/MC/X86/
H A Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
H A Dintel-syntax.s21 mov RAX, QWORD PTR [RSP]
27 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
67 mov RAX, QWORD PTR FS:[320]
69 mov RAX, QWORD PTR FS:320
71 mov QWORD PTR FS:320, RAX
73 mov QWORD PTR FS:20[rbx], RAX
382 shld [RAX], BX
383 shld [RAX], BX, CL
387 shrd [RAX], BX
388 shrd [RAX], B
[all...]
/external/libunwind/src/x86_64/
H A Dunwind_i.h39 #define RAX 0 macro
H A Dinit.h49 c->dwarf.loc[RAX] = REG_INIT_LOC(c, rax, RAX);
H A DGregs.c104 loc = c->dwarf.loc[(reg == UNW_X86_64_RAX) ? RAX : RDX];
H A DGos-freebsd.c111 c->dwarf.loc[RAX] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RAX, 0);
/external/capstone/suite/MC/X86/
H A Dintel-syntax-encoding.s.cs11 0x48,0x89,0x44,0x24,0xf0 = mov QWORD PTR [RSP - 16], RAX
/external/lzma/Asm/x86/
H A D7zAsm.asm66 r0 equ RAX
/external/valgrind/coregrind/m_sigframe/
H A Dsigframe-amd64-darwin.c106 SC2(__rax,RAX);
134 SC2(RAX,__rax);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX,
293 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
305 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
342 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
378 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
414 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
415 return X86::RAX;
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86RegisterInfo.cpp365 X86::RAX, X86::RDX, X86::RBX, X86::R12,
669 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
681 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
718 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
754 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
790 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
791 return X86::RAX;
H A DX86GenRegisterInfo.inc124 RAX = 105,
249 const unsigned AH_Overlaps[] = { X86::AH, X86::AX, X86::EAX, X86::RAX, 0 };
250 const unsigned AL_Overlaps[] = { X86::AL, X86::AX, X86::EAX, X86::RAX, 0 };
251 const unsigned AX_Overlaps[] = { X86::AX, X86::AH, X86::AL, X86::EAX, X86::RAX, 0 };
291 const unsigned EAX_Overlaps[] = { X86::EAX, X86::AH, X86::AL, X86::AX, X86::RAX, 0 };
353 const unsigned RAX_Overlaps[] = { X86::RAX, X86::AH, X86::AL, X86::AX, X86::EAX, 0 };
492 const unsigned AH_SuperRegsSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
493 const unsigned AL_SuperRegsSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
494 const unsigned AX_SuperRegsSet[] = { X86::EAX, X86::RAX, 0 };
508 const unsigned EAX_SuperRegsSet[] = { X86::RAX,
[all...]
H A DX86FrameLowering.cpp99 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
159 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
842 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1349 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1366 restoreR10MBB->addLiveIn(X86::RAX);
1409 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1444 .addReg(X86::RAX);
H A DX86SelectionDAGInfo.cpp103 ValReg = X86::RAX;
/external/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp57 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
126 ValReg = X86::RAX;
H A DX86MCInstLower.cpp262 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
289 if (Op0 == X86::RAX && Op1 == X86::EAX)
323 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
495 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
782 BaseReg = X86::RAX;
791 IndexReg = X86::RAX; break;
793 IndexReg = X86::RAX; break;
796 IndexReg = X86::RAX; break;
798 IndexReg = X86::RAX; break;
800 IndexReg = X86::RAX; SegmentRe
[all...]
H A DX86WinAllocaExpander.cpp214 unsigned RegA = (SlotSize == 8) ? X86::RAX : X86::EAX;
242 // The probe lowering expects the amount in RAX/EAX.
H A DX86FrameLowering.cpp201 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
266 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
290 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
499 // RAX contains the number of bytes of desired stack adjustment.
508 // SizeReg = RAX;
523 // RSP = RSP - RAX
547 // registers. For the prolog expansion we use RAX, RCX and RDX.
550 const unsigned SizeReg = InProlog ? (unsigned)X86::RAX
592 // Not in the prolog. Copy RAX to a virtual reg.
593 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h161 ENTRY(RAX) \
179 ENTRY(RAX) \
/external/google-breakpad/src/common/android/
H A Dbreakpad_getcontext_unittest.cc134 CHECK_REG(RAX);
/external/capstone/arch/X86/
H A DX86DisassemblerDecoder.h184 ENTRY(RAX) \
202 ENTRY(RAX) \
/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h171 ENTRY(RAX) \
189 ENTRY(RAX) \

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