/external/strace/linux/x86_64/ |
H A D | set_error.c | 20 return upoke(tcp, 8 * RAX, rval); 41 return upoke(tcp, 8 * RAX, rval);
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H A D | userent.h | 11 XLAT(8*RAX),
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/external/kernel-headers/original/uapi/asm-x86/asm/ |
H A D | ptrace-abi.h | 44 #define RAX 80 macro
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/external/llvm/test/MC/X86/ |
H A D | intel-syntax-encoding.s | 25 mov QWORD PTR [RSP - 16], RAX
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H A D | intel-syntax.s | 21 mov RAX, QWORD PTR [RSP] 27 mov EAX, DWORD PTR [RSP + 4*RAX - 24] 67 mov RAX, QWORD PTR FS:[320] 69 mov RAX, QWORD PTR FS:320 71 mov QWORD PTR FS:320, RAX 73 mov QWORD PTR FS:20[rbx], RAX 382 shld [RAX], BX 383 shld [RAX], BX, CL 387 shrd [RAX], BX 388 shrd [RAX], B [all...] |
/external/libunwind/src/x86_64/ |
H A D | unwind_i.h | 39 #define RAX 0 macro
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H A D | init.h | 49 c->dwarf.loc[RAX] = REG_INIT_LOC(c, rax, RAX);
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H A D | Gregs.c | 104 loc = c->dwarf.loc[(reg == UNW_X86_64_RAX) ? RAX : RDX];
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H A D | Gos-freebsd.c | 111 c->dwarf.loc[RAX] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RAX, 0);
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/external/capstone/suite/MC/X86/ |
H A D | intel-syntax-encoding.s.cs | 11 0x48,0x89,0x44,0x24,0xf0 = mov QWORD PTR [RSP - 16], RAX
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/external/lzma/Asm/x86/ |
H A D | 7zAsm.asm | 66 r0 equ RAX
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/external/valgrind/coregrind/m_sigframe/ |
H A D | sigframe-amd64-darwin.c | 106 SC2(__rax,RAX); 134 SC2(RAX,__rax);
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, 293 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 305 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 342 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 378 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 414 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 415 return X86::RAX;
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 365 X86::RAX, X86::RDX, X86::RBX, X86::R12, 669 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 681 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 718 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 754 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 790 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 791 return X86::RAX;
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H A D | X86GenRegisterInfo.inc | 124 RAX = 105,
249 const unsigned AH_Overlaps[] = { X86::AH, X86::AX, X86::EAX, X86::RAX, 0 };
250 const unsigned AL_Overlaps[] = { X86::AL, X86::AX, X86::EAX, X86::RAX, 0 };
251 const unsigned AX_Overlaps[] = { X86::AX, X86::AH, X86::AL, X86::EAX, X86::RAX, 0 };
291 const unsigned EAX_Overlaps[] = { X86::EAX, X86::AH, X86::AL, X86::AX, X86::RAX, 0 };
353 const unsigned RAX_Overlaps[] = { X86::RAX, X86::AH, X86::AL, X86::AX, X86::EAX, 0 };
492 const unsigned AH_SuperRegsSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
493 const unsigned AL_SuperRegsSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
494 const unsigned AX_SuperRegsSet[] = { X86::EAX, X86::RAX, 0 };
508 const unsigned EAX_SuperRegsSet[] = { X86::RAX, [all...] |
H A D | X86FrameLowering.cpp | 99 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, 159 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) 842 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) 1349 // The MOV R10, RAX needs to be in a different block, since the RET we emit in 1366 restoreR10MBB->addLiveIn(X86::RAX); 1409 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); 1444 .addReg(X86::RAX);
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H A D | X86SelectionDAGInfo.cpp | 103 ValReg = X86::RAX;
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/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 57 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, 126 ValReg = X86::RAX;
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H A D | X86MCInstLower.cpp | 262 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 289 if (Op0 == X86::RAX && Op1 == X86::EAX) 323 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 495 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; 782 BaseReg = X86::RAX; 791 IndexReg = X86::RAX; break; 793 IndexReg = X86::RAX; break; 796 IndexReg = X86::RAX; break; 798 IndexReg = X86::RAX; break; 800 IndexReg = X86::RAX; SegmentRe [all...] |
H A D | X86WinAllocaExpander.cpp | 214 unsigned RegA = (SlotSize == 8) ? X86::RAX : X86::EAX; 242 // The probe lowering expects the amount in RAX/EAX.
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H A D | X86FrameLowering.cpp | 201 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX || 266 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX); 290 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) 499 // RAX contains the number of bytes of desired stack adjustment. 508 // SizeReg = RAX; 523 // RSP = RSP - RAX 547 // registers. For the prolog expansion we use RAX, RCX and RDX. 550 const unsigned SizeReg = InProlog ? (unsigned)X86::RAX 592 // Not in the prolog. Copy RAX to a virtual reg. 593 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
H A D | X86DisassemblerDecoder.h | 161 ENTRY(RAX) \ 179 ENTRY(RAX) \
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/external/google-breakpad/src/common/android/ |
H A D | breakpad_getcontext_unittest.cc | 134 CHECK_REG(RAX);
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/external/capstone/arch/X86/ |
H A D | X86DisassemblerDecoder.h | 184 ENTRY(RAX) \ 202 ENTRY(RAX) \
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/external/llvm/lib/Target/X86/Disassembler/ |
H A D | X86DisassemblerDecoder.h | 171 ENTRY(RAX) \ 189 ENTRY(RAX) \
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