1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides X86 specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86MCTargetDesc.h" 15#include "InstPrinter/X86ATTInstPrinter.h" 16#include "InstPrinter/X86IntelInstPrinter.h" 17#include "X86MCAsmInfo.h" 18#include "llvm/ADT/Triple.h" 19#include "llvm/MC/MCInstrAnalysis.h" 20#include "llvm/MC/MCInstrInfo.h" 21#include "llvm/MC/MCRegisterInfo.h" 22#include "llvm/MC/MCStreamer.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MachineLocation.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/Host.h" 27#include "llvm/Support/TargetRegistry.h" 28 29#if _MSC_VER 30#include <intrin.h> 31#endif 32 33using namespace llvm; 34 35#define GET_REGINFO_MC_DESC 36#include "X86GenRegisterInfo.inc" 37 38#define GET_INSTRINFO_MC_DESC 39#include "X86GenInstrInfo.inc" 40 41#define GET_SUBTARGETINFO_MC_DESC 42#include "X86GenSubtargetInfo.inc" 43 44std::string X86_MC::ParseX86Triple(const Triple &TT) { 45 std::string FS; 46 if (TT.getArch() == Triple::x86_64) 47 FS = "+64bit-mode,-32bit-mode,-16bit-mode"; 48 else if (TT.getEnvironment() != Triple::CODE16) 49 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 50 else 51 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 52 53 return FS; 54} 55 56unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 57 if (TT.getArch() == Triple::x86_64) 58 return DWARFFlavour::X86_64; 59 60 if (TT.isOSDarwin()) 61 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 62 if (TT.isOSCygMing()) 63 // Unsupported by now, just quick fallback 64 return DWARFFlavour::X86_32_Generic; 65 return DWARFFlavour::X86_32_Generic; 66} 67 68void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { 69 // FIXME: TableGen these. 70 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 71 unsigned SEH = MRI->getEncodingValue(Reg); 72 MRI->mapLLVMRegToSEHReg(Reg, SEH); 73 } 74 75 // These CodeView registers are numbered sequentially starting at value 1. 76 static const MCPhysReg LowCVRegs[] = { 77 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, 78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, 79 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, 80 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, 81 }; 82 unsigned CVLowRegStart = 1; 83 for (unsigned I = 0; I < array_lengthof(LowCVRegs); ++I) 84 MRI->mapLLVMRegToCVReg(LowCVRegs[I], I + CVLowRegStart); 85 86 MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); 87 88 // The x87 registers start at 128 and are numbered sequentially. 89 unsigned FP0Start = 128; 90 for (unsigned I = 0; I < 8; ++I) 91 MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); 92 93 // The low 8 XMM registers start at 154 and are numbered sequentially. 94 unsigned CVXMM0Start = 154; 95 for (unsigned I = 0; I < 8; ++I) 96 MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); 97 98 // The high 8 XMM registers start at 252 and are numbered sequentially. 99 unsigned CVXMM8Start = 252; 100 for (unsigned I = 0; I < 8; ++I) 101 MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); 102 103 // FIXME: XMM16 and above from AVX512 not yet documented. 104 105 // AMD64 registers start at 324 and count up. 106 unsigned CVX64RegStart = 324; 107 static const MCPhysReg CVX64Regs[] = { 108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, 109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, 110 X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, 111 X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, 112 X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W, 113 X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W, 114 X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D, 115 X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, 116 X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, 117 X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 118 }; 119 for (unsigned I = 0; I < array_lengthof(CVX64Regs); ++I) 120 MRI->mapLLVMRegToCVReg(CVX64Regs[I], CVX64RegStart + I); 121} 122 123MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 124 StringRef CPU, StringRef FS) { 125 std::string ArchFS = X86_MC::ParseX86Triple(TT); 126 if (!FS.empty()) { 127 if (!ArchFS.empty()) 128 ArchFS = (Twine(ArchFS) + "," + FS).str(); 129 else 130 ArchFS = FS; 131 } 132 133 std::string CPUName = CPU; 134 if (CPUName.empty()) 135 CPUName = "generic"; 136 137 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS); 138} 139 140static MCInstrInfo *createX86MCInstrInfo() { 141 MCInstrInfo *X = new MCInstrInfo(); 142 InitX86MCInstrInfo(X); 143 return X; 144} 145 146static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 147 unsigned RA = (TT.getArch() == Triple::x86_64) 148 ? X86::RIP // Should have dwarf #16. 149 : X86::EIP; // Should have dwarf #8. 150 151 MCRegisterInfo *X = new MCRegisterInfo(); 152 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 153 X86_MC::getDwarfRegFlavour(TT, true), RA); 154 X86_MC::initLLVMToSEHAndCVRegMapping(X); 155 return X; 156} 157 158static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 159 const Triple &TheTriple) { 160 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 161 162 MCAsmInfo *MAI; 163 if (TheTriple.isOSBinFormatMachO()) { 164 if (is64Bit) 165 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 166 else 167 MAI = new X86MCAsmInfoDarwin(TheTriple); 168 } else if (TheTriple.isOSBinFormatELF()) { 169 // Force the use of an ELF container. 170 MAI = new X86ELFMCAsmInfo(TheTriple); 171 } else if (TheTriple.isWindowsMSVCEnvironment() || 172 TheTriple.isWindowsCoreCLREnvironment()) { 173 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 174 } else if (TheTriple.isOSCygMing() || 175 TheTriple.isWindowsItaniumEnvironment()) { 176 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 177 } else { 178 // The default is ELF. 179 MAI = new X86ELFMCAsmInfo(TheTriple); 180 } 181 182 // Initialize initial frame state. 183 // Calculate amount of bytes used for return address storing 184 int stackGrowth = is64Bit ? -8 : -4; 185 186 // Initial state of the frame pointer is esp+stackGrowth. 187 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 188 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( 189 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 190 MAI->addInitialFrameState(Inst); 191 192 // Add return address to move list 193 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 194 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 195 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 196 MAI->addInitialFrameState(Inst2); 197 198 return MAI; 199} 200 201static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, 202 CodeModel::Model &CM) { 203 bool is64Bit = TT.getArch() == Triple::x86_64; 204 205 // For static codegen, if we're not already set, use Small codegen. 206 if (CM == CodeModel::Default) 207 CM = CodeModel::Small; 208 else if (CM == CodeModel::JITDefault) 209 // 64-bit JIT places everything in the same buffer except external funcs. 210 CM = is64Bit ? CodeModel::Large : CodeModel::Small; 211} 212 213static MCInstPrinter *createX86MCInstPrinter(const Triple &T, 214 unsigned SyntaxVariant, 215 const MCAsmInfo &MAI, 216 const MCInstrInfo &MII, 217 const MCRegisterInfo &MRI) { 218 if (SyntaxVariant == 0) 219 return new X86ATTInstPrinter(MAI, MII, MRI); 220 if (SyntaxVariant == 1) 221 return new X86IntelInstPrinter(MAI, MII, MRI); 222 return nullptr; 223} 224 225static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 226 MCContext &Ctx) { 227 // Default to the stock relocation info. 228 return llvm::createMCRelocationInfo(TheTriple, Ctx); 229} 230 231static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 232 return new MCInstrAnalysis(Info); 233} 234 235// Force static initialization. 236extern "C" void LLVMInitializeX86TargetMC() { 237 for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { 238 // Register the MC asm info. 239 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 240 241 // Register the MC codegen info. 242 RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts); 243 244 // Register the MC instruction info. 245 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 246 247 // Register the MC register info. 248 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 249 250 // Register the MC subtarget info. 251 TargetRegistry::RegisterMCSubtargetInfo(*T, 252 X86_MC::createX86MCSubtargetInfo); 253 254 // Register the MC instruction analyzer. 255 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 256 257 // Register the code emitter. 258 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 259 260 // Register the object streamer. 261 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 262 263 // Register the MCInstPrinter. 264 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 265 266 // Register the MC relocation info. 267 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 268 } 269 270 // Register the asm backend. 271 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 272 createX86_32AsmBackend); 273 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 274 createX86_64AsmBackend); 275} 276 277unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, 278 bool High) { 279 switch (Size) { 280 default: return 0; 281 case 8: 282 if (High) { 283 switch (Reg) { 284 default: return getX86SubSuperRegisterOrZero(Reg, 64); 285 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 286 return X86::SI; 287 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 288 return X86::DI; 289 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 290 return X86::BP; 291 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 292 return X86::SP; 293 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 294 return X86::AH; 295 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 296 return X86::DH; 297 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 298 return X86::CH; 299 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 300 return X86::BH; 301 } 302 } else { 303 switch (Reg) { 304 default: return 0; 305 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 306 return X86::AL; 307 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 308 return X86::DL; 309 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 310 return X86::CL; 311 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 312 return X86::BL; 313 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 314 return X86::SIL; 315 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 316 return X86::DIL; 317 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 318 return X86::BPL; 319 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 320 return X86::SPL; 321 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 322 return X86::R8B; 323 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 324 return X86::R9B; 325 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 326 return X86::R10B; 327 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 328 return X86::R11B; 329 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 330 return X86::R12B; 331 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 332 return X86::R13B; 333 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 334 return X86::R14B; 335 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 336 return X86::R15B; 337 } 338 } 339 case 16: 340 switch (Reg) { 341 default: return 0; 342 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 343 return X86::AX; 344 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 345 return X86::DX; 346 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 347 return X86::CX; 348 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 349 return X86::BX; 350 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 351 return X86::SI; 352 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 353 return X86::DI; 354 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 355 return X86::BP; 356 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 357 return X86::SP; 358 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 359 return X86::R8W; 360 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 361 return X86::R9W; 362 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 363 return X86::R10W; 364 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 365 return X86::R11W; 366 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 367 return X86::R12W; 368 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 369 return X86::R13W; 370 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 371 return X86::R14W; 372 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 373 return X86::R15W; 374 } 375 case 32: 376 switch (Reg) { 377 default: return 0; 378 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 379 return X86::EAX; 380 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 381 return X86::EDX; 382 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 383 return X86::ECX; 384 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 385 return X86::EBX; 386 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 387 return X86::ESI; 388 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 389 return X86::EDI; 390 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 391 return X86::EBP; 392 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 393 return X86::ESP; 394 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 395 return X86::R8D; 396 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 397 return X86::R9D; 398 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 399 return X86::R10D; 400 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 401 return X86::R11D; 402 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 403 return X86::R12D; 404 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 405 return X86::R13D; 406 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 407 return X86::R14D; 408 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 409 return X86::R15D; 410 } 411 case 64: 412 switch (Reg) { 413 default: return 0; 414 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 415 return X86::RAX; 416 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 417 return X86::RDX; 418 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 419 return X86::RCX; 420 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 421 return X86::RBX; 422 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 423 return X86::RSI; 424 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 425 return X86::RDI; 426 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 427 return X86::RBP; 428 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 429 return X86::RSP; 430 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 431 return X86::R8; 432 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 433 return X86::R9; 434 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 435 return X86::R10; 436 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 437 return X86::R11; 438 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 439 return X86::R12; 440 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 441 return X86::R13; 442 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 443 return X86::R14; 444 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 445 return X86::R15; 446 } 447 } 448} 449 450unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { 451 unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 452 assert(Res != 0 && "Unexpected register or VT"); 453 return Res; 454} 455 456 457