1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *  * Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 *  * Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in
12 *    the documentation and/or other materials provided with the
13 *    distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <private/bionic_asm.h>
30
31// DWARF constants.
32#define DW_CFA_def_cfa_expression 0x0f
33#define DW_CFA_expression 0x10
34#define DW_EH_PE_pcrel 0x10
35#define DW_EH_PE_sdata4 0x0b
36#define DW_OP_breg4 0x74
37#define DW_OP_deref 0x06
38
39// Offsets into struct sigcontext.
40#define OFFSET_EDI 16
41#define OFFSET_ESI 20
42#define OFFSET_EBP 24
43#define OFFSET_ESP 28
44#define OFFSET_EBX 32
45#define OFFSET_EDX 36
46#define OFFSET_ECX 40
47#define OFFSET_EAX 44
48#define OFFSET_EIP 56
49
50// Non-standard DWARF constants for the x86 registers.
51#define DW_x86_REG_EAX 0
52#define DW_x86_REG_ECX 1
53#define DW_x86_REG_EDX 2
54#define DW_x86_REG_EBX 3
55#define DW_x86_REG_EBP 5
56#define DW_x86_REG_ESI 6
57#define DW_x86_REG_EDI 7
58#define DW_x86_REG_EIP 8
59
60#define cfi_signal_frame_start(f) \
61.section .eh_frame,"a",@progbits; \
62.L ## f ## _START_EH_FRAME: \
63  .long 2f - 1f; /* CIE length. */ \
641:.long 0;       /* CIE ID. */ \
65  .byte 1;       /* Version. */ \
66  .string "zRS"; /* Augmentation string. */ \
67  .uleb128 1;    /* Code alignment factor. */ \
68  .sleb128 -4;   /* Data alignment factor. */ \
69  .uleb128 DW_x86_REG_EIP;    /* Return address register. */ \
70  .uleb128 1;    /* 1 byte of augmentation data. */ \
71  .byte (DW_EH_PE_pcrel|DW_EH_PE_sdata4); /* FDE encoding. */ \
72  .align 8; \
732: \
74  .long .L ## f ## _END_FDE - .L ## f ## _START_FDE;   /* FDE length. */ \
75.L ## f ## _START_FDE: \
76  .long .L ## f ## _START_FDE - .L ## f ## _START_EH_FRAME; /* CIE location. */ \
77  .long (.L ## f ## _START - 1) - .;                   /* pcrel start address (see FDE encoding above). */ \
78  .long .L ## f ## _END - (.L ## f ## _START - 1);     /* Function this FDE applies to. */ \
79  .uleb128 0;                                          /* FDE augmentation length. */ \
80
81#define cfi_signal_frame_end(f) \
82.L ## f ## _END_FDE: \
83
84#define cfi_def_cfa(offset) \
85  .byte DW_CFA_def_cfa_expression; \
86  .uleb128 2f-1f; \
871:.byte DW_OP_breg4; \
88  .sleb128 offset; \
89  .byte DW_OP_deref; \
902: \
91
92#define cfi_offset(reg_number,offset) \
93  .byte DW_CFA_expression; \
94  .uleb128 reg_number; \
95  .uleb128 2f-1f; \
961:.byte DW_OP_breg4; \
97  .sleb128 offset; \
982: \
99
100ENTRY_PRIVATE(__restore)
101.L__restore_START:
102  popl %eax
103  movl $__NR_sigreturn, %eax
104  int $0x80
105.L__restore_END:
106END(__restore)
107cfi_signal_frame_start(__restore)
108  cfi_def_cfa(OFFSET_ESP + 4)
109  cfi_offset(DW_x86_REG_EDI, OFFSET_EDI + 4)
110  cfi_offset(DW_x86_REG_ESI, OFFSET_ESI + 4)
111  cfi_offset(DW_x86_REG_EBP, OFFSET_EBP + 4)
112  cfi_offset(DW_x86_REG_EBX, OFFSET_EBX + 4)
113  cfi_offset(DW_x86_REG_EDX, OFFSET_EDX + 4)
114  cfi_offset(DW_x86_REG_ECX, OFFSET_ECX + 4)
115  cfi_offset(DW_x86_REG_EAX, OFFSET_EAX + 4)
116  cfi_offset(DW_x86_REG_EIP, OFFSET_EIP + 4)
117cfi_signal_frame_end(__restore)
118
119ENTRY_PRIVATE(__restore_rt)
120.L__restore_rt_START:
121  movl $__NR_rt_sigreturn, %eax
122  int $0x80
123.L__restore_rt_END:
124END(__restore_rt)
125cfi_signal_frame_start(__restore_rt)
126  cfi_def_cfa(OFFSET_ESP + 160)
127  cfi_offset(DW_x86_REG_EDI, OFFSET_EDI + 160)
128  cfi_offset(DW_x86_REG_ESI, OFFSET_ESI + 160)
129  cfi_offset(DW_x86_REG_EBP, OFFSET_EBP + 160)
130  cfi_offset(DW_x86_REG_EBX, OFFSET_EBX + 160)
131  cfi_offset(DW_x86_REG_EDX, OFFSET_EDX + 160)
132  cfi_offset(DW_x86_REG_ECX, OFFSET_ECX + 160)
133  cfi_offset(DW_x86_REG_EAX, OFFSET_EAX + 160)
134  cfi_offset(DW_x86_REG_EIP, OFFSET_EIP + 160)
135cfi_signal_frame_end(__restore_rt)
136