etnaviv_drm.h revision 525ce914edf136d2bd02ac8c404d56c52e737f4d 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __ETNAVIV_DRM_H__
20#define __ETNAVIV_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24struct drm_etnaviv_timespec {
25  __s64 tv_sec;
26  __s64 tv_nsec;
27};
28#define ETNAVIV_PARAM_GPU_MODEL 0x01
29#define ETNAVIV_PARAM_GPU_REVISION 0x02
30#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
31#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
32#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
33#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
34#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
35#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
36#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
37#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
38#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
39#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
40#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
41#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
42#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
43#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
44#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
45#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
46#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
47#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
48#define ETNA_MAX_PIPES 4
49struct drm_etnaviv_param {
50  __u32 pipe;
51  __u32 param;
52  __u64 value;
53};
54#define ETNA_BO_CACHE_MASK 0x000f0000
55#define ETNA_BO_CACHED 0x00010000
56#define ETNA_BO_WC 0x00020000
57#define ETNA_BO_UNCACHED 0x00040000
58#define ETNA_BO_FORCE_MMU 0x00100000
59struct drm_etnaviv_gem_new {
60  __u64 size;
61  __u32 flags;
62  __u32 handle;
63};
64struct drm_etnaviv_gem_info {
65  __u32 handle;
66  __u32 pad;
67  __u64 offset;
68};
69#define ETNA_PREP_READ 0x01
70#define ETNA_PREP_WRITE 0x02
71#define ETNA_PREP_NOSYNC 0x04
72struct drm_etnaviv_gem_cpu_prep {
73  __u32 handle;
74  __u32 op;
75  struct drm_etnaviv_timespec timeout;
76};
77struct drm_etnaviv_gem_cpu_fini {
78  __u32 handle;
79  __u32 flags;
80};
81struct drm_etnaviv_gem_submit_reloc {
82  __u32 submit_offset;
83  __u32 reloc_idx;
84  __u64 reloc_offset;
85  __u32 flags;
86};
87#define ETNA_SUBMIT_BO_READ 0x0001
88#define ETNA_SUBMIT_BO_WRITE 0x0002
89struct drm_etnaviv_gem_submit_bo {
90  __u32 flags;
91  __u32 handle;
92  __u64 presumed;
93};
94#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
95#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
96#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
97#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT)
98#define ETNA_PIPE_3D 0x00
99#define ETNA_PIPE_2D 0x01
100#define ETNA_PIPE_VG 0x02
101struct drm_etnaviv_gem_submit {
102  __u32 fence;
103  __u32 pipe;
104  __u32 exec_state;
105  __u32 nr_bos;
106  __u32 nr_relocs;
107  __u32 stream_size;
108  __u64 bos;
109  __u64 relocs;
110  __u64 stream;
111  __u32 flags;
112  __s32 fence_fd;
113};
114#define ETNA_WAIT_NONBLOCK 0x01
115struct drm_etnaviv_wait_fence {
116  __u32 pipe;
117  __u32 fence;
118  __u32 flags;
119  __u32 pad;
120  struct drm_etnaviv_timespec timeout;
121};
122#define ETNA_USERPTR_READ 0x01
123#define ETNA_USERPTR_WRITE 0x02
124struct drm_etnaviv_gem_userptr {
125  __u64 user_ptr;
126  __u64 user_size;
127  __u32 flags;
128  __u32 handle;
129};
130struct drm_etnaviv_gem_wait {
131  __u32 pipe;
132  __u32 handle;
133  __u32 flags;
134  __u32 pad;
135  struct drm_etnaviv_timespec timeout;
136};
137#define DRM_ETNAVIV_GET_PARAM 0x00
138#define DRM_ETNAVIV_GEM_NEW 0x02
139#define DRM_ETNAVIV_GEM_INFO 0x03
140#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
141#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
142#define DRM_ETNAVIV_GEM_SUBMIT 0x06
143#define DRM_ETNAVIV_WAIT_FENCE 0x07
144#define DRM_ETNAVIV_GEM_USERPTR 0x08
145#define DRM_ETNAVIV_GEM_WAIT 0x09
146#define DRM_ETNAVIV_NUM_IOCTLS 0x0a
147#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
148#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
149#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
150#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
151#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
152#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
153#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
154#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
155#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
156#ifdef __cplusplus
157#endif
158#endif
159