drm_mode.h revision 96c1db7b9d601c31d103389cac074a6cce0d7633 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define DRM_DISPLAY_INFO_LEN 32
25#define DRM_CONNECTOR_NAME_LEN 32
26#define DRM_DISPLAY_MODE_LEN 32
27#define DRM_PROP_NAME_LEN 32
28#define DRM_MODE_TYPE_BUILTIN (1 << 0)
29#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
30#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
31#define DRM_MODE_TYPE_PREFERRED (1 << 3)
32#define DRM_MODE_TYPE_DEFAULT (1 << 4)
33#define DRM_MODE_TYPE_USERDEF (1 << 5)
34#define DRM_MODE_TYPE_DRIVER (1 << 6)
35#define DRM_MODE_FLAG_PHSYNC (1 << 0)
36#define DRM_MODE_FLAG_NHSYNC (1 << 1)
37#define DRM_MODE_FLAG_PVSYNC (1 << 2)
38#define DRM_MODE_FLAG_NVSYNC (1 << 3)
39#define DRM_MODE_FLAG_INTERLACE (1 << 4)
40#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
41#define DRM_MODE_FLAG_CSYNC (1 << 6)
42#define DRM_MODE_FLAG_PCSYNC (1 << 7)
43#define DRM_MODE_FLAG_NCSYNC (1 << 8)
44#define DRM_MODE_FLAG_HSKEW (1 << 9)
45#define DRM_MODE_FLAG_BCAST (1 << 10)
46#define DRM_MODE_FLAG_PIXMUX (1 << 11)
47#define DRM_MODE_FLAG_DBLCLK (1 << 12)
48#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
49#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
50#define DRM_MODE_FLAG_3D_NONE (0 << 14)
51#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
52#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
53#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
54#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
55#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
56#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
57#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
58#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
59#define DRM_MODE_PICTURE_ASPECT_NONE 0
60#define DRM_MODE_PICTURE_ASPECT_4_3 1
61#define DRM_MODE_PICTURE_ASPECT_16_9 2
62#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19)
63#define DRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE << 19)
64#define DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3 << 19)
65#define DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9 << 19)
66#define DRM_MODE_DPMS_ON 0
67#define DRM_MODE_DPMS_STANDBY 1
68#define DRM_MODE_DPMS_SUSPEND 2
69#define DRM_MODE_DPMS_OFF 3
70#define DRM_MODE_SCALE_NONE 0
71#define DRM_MODE_SCALE_FULLSCREEN 1
72#define DRM_MODE_SCALE_CENTER 2
73#define DRM_MODE_SCALE_ASPECT 3
74#define DRM_MODE_DITHERING_OFF 0
75#define DRM_MODE_DITHERING_ON 1
76#define DRM_MODE_DITHERING_AUTO 2
77#define DRM_MODE_DIRTY_OFF 0
78#define DRM_MODE_DIRTY_ON 1
79#define DRM_MODE_DIRTY_ANNOTATE 2
80struct drm_mode_modeinfo {
81  __u32 clock;
82  __u16 hdisplay;
83  __u16 hsync_start;
84  __u16 hsync_end;
85  __u16 htotal;
86  __u16 hskew;
87  __u16 vdisplay;
88  __u16 vsync_start;
89  __u16 vsync_end;
90  __u16 vtotal;
91  __u16 vscan;
92  __u32 vrefresh;
93  __u32 flags;
94  __u32 type;
95  char name[DRM_DISPLAY_MODE_LEN];
96};
97struct drm_mode_card_res {
98  __u64 fb_id_ptr;
99  __u64 crtc_id_ptr;
100  __u64 connector_id_ptr;
101  __u64 encoder_id_ptr;
102  __u32 count_fbs;
103  __u32 count_crtcs;
104  __u32 count_connectors;
105  __u32 count_encoders;
106  __u32 min_width;
107  __u32 max_width;
108  __u32 min_height;
109  __u32 max_height;
110};
111struct drm_mode_crtc {
112  __u64 set_connectors_ptr;
113  __u32 count_connectors;
114  __u32 crtc_id;
115  __u32 fb_id;
116  __u32 x;
117  __u32 y;
118  __u32 gamma_size;
119  __u32 mode_valid;
120  struct drm_mode_modeinfo mode;
121};
122#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
123#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
124struct drm_mode_set_plane {
125  __u32 plane_id;
126  __u32 crtc_id;
127  __u32 fb_id;
128  __u32 flags;
129  __s32 crtc_x;
130  __s32 crtc_y;
131  __u32 crtc_w;
132  __u32 crtc_h;
133  __u32 src_x;
134  __u32 src_y;
135  __u32 src_h;
136  __u32 src_w;
137};
138struct drm_mode_get_plane {
139  __u32 plane_id;
140  __u32 crtc_id;
141  __u32 fb_id;
142  __u32 possible_crtcs;
143  __u32 gamma_size;
144  __u32 count_format_types;
145  __u64 format_type_ptr;
146};
147struct drm_mode_get_plane_res {
148  __u64 plane_id_ptr;
149  __u32 count_planes;
150};
151#define DRM_MODE_ENCODER_NONE 0
152#define DRM_MODE_ENCODER_DAC 1
153#define DRM_MODE_ENCODER_TMDS 2
154#define DRM_MODE_ENCODER_LVDS 3
155#define DRM_MODE_ENCODER_TVDAC 4
156#define DRM_MODE_ENCODER_VIRTUAL 5
157#define DRM_MODE_ENCODER_DSI 6
158#define DRM_MODE_ENCODER_DPMST 7
159#define DRM_MODE_ENCODER_DPI 8
160struct drm_mode_get_encoder {
161  __u32 encoder_id;
162  __u32 encoder_type;
163  __u32 crtc_id;
164  __u32 possible_crtcs;
165  __u32 possible_clones;
166};
167enum drm_mode_subconnector {
168  DRM_MODE_SUBCONNECTOR_Automatic = 0,
169  DRM_MODE_SUBCONNECTOR_Unknown = 0,
170  DRM_MODE_SUBCONNECTOR_DVID = 3,
171  DRM_MODE_SUBCONNECTOR_DVIA = 4,
172  DRM_MODE_SUBCONNECTOR_Composite = 5,
173  DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
174  DRM_MODE_SUBCONNECTOR_Component = 8,
175  DRM_MODE_SUBCONNECTOR_SCART = 9,
176};
177#define DRM_MODE_CONNECTOR_Unknown 0
178#define DRM_MODE_CONNECTOR_VGA 1
179#define DRM_MODE_CONNECTOR_DVII 2
180#define DRM_MODE_CONNECTOR_DVID 3
181#define DRM_MODE_CONNECTOR_DVIA 4
182#define DRM_MODE_CONNECTOR_Composite 5
183#define DRM_MODE_CONNECTOR_SVIDEO 6
184#define DRM_MODE_CONNECTOR_LVDS 7
185#define DRM_MODE_CONNECTOR_Component 8
186#define DRM_MODE_CONNECTOR_9PinDIN 9
187#define DRM_MODE_CONNECTOR_DisplayPort 10
188#define DRM_MODE_CONNECTOR_HDMIA 11
189#define DRM_MODE_CONNECTOR_HDMIB 12
190#define DRM_MODE_CONNECTOR_TV 13
191#define DRM_MODE_CONNECTOR_eDP 14
192#define DRM_MODE_CONNECTOR_VIRTUAL 15
193#define DRM_MODE_CONNECTOR_DSI 16
194#define DRM_MODE_CONNECTOR_DPI 17
195struct drm_mode_get_connector {
196  __u64 encoders_ptr;
197  __u64 modes_ptr;
198  __u64 props_ptr;
199  __u64 prop_values_ptr;
200  __u32 count_modes;
201  __u32 count_props;
202  __u32 count_encoders;
203  __u32 encoder_id;
204  __u32 connector_id;
205  __u32 connector_type;
206  __u32 connector_type_id;
207  __u32 connection;
208  __u32 mm_width;
209  __u32 mm_height;
210  __u32 subpixel;
211  __u32 pad;
212};
213#define DRM_MODE_PROP_PENDING (1 << 0)
214#define DRM_MODE_PROP_RANGE (1 << 1)
215#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
216#define DRM_MODE_PROP_ENUM (1 << 3)
217#define DRM_MODE_PROP_BLOB (1 << 4)
218#define DRM_MODE_PROP_BITMASK (1 << 5)
219#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
220#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
221#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
222#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
223#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
224#define DRM_MODE_PROP_ATOMIC 0x80000000
225struct drm_mode_property_enum {
226  __u64 value;
227  char name[DRM_PROP_NAME_LEN];
228};
229struct drm_mode_get_property {
230  __u64 values_ptr;
231  __u64 enum_blob_ptr;
232  __u32 prop_id;
233  __u32 flags;
234  char name[DRM_PROP_NAME_LEN];
235  __u32 count_values;
236  __u32 count_enum_blobs;
237};
238struct drm_mode_connector_set_property {
239  __u64 value;
240  __u32 prop_id;
241  __u32 connector_id;
242};
243#define DRM_MODE_OBJECT_CRTC 0xcccccccc
244#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
245#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
246#define DRM_MODE_OBJECT_MODE 0xdededede
247#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
248#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
249#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
250#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
251#define DRM_MODE_OBJECT_ANY 0
252struct drm_mode_obj_get_properties {
253  __u64 props_ptr;
254  __u64 prop_values_ptr;
255  __u32 count_props;
256  __u32 obj_id;
257  __u32 obj_type;
258};
259struct drm_mode_obj_set_property {
260  __u64 value;
261  __u32 prop_id;
262  __u32 obj_id;
263  __u32 obj_type;
264};
265struct drm_mode_get_blob {
266  __u32 blob_id;
267  __u32 length;
268  __u64 data;
269};
270struct drm_mode_fb_cmd {
271  __u32 fb_id;
272  __u32 width;
273  __u32 height;
274  __u32 pitch;
275  __u32 bpp;
276  __u32 depth;
277  __u32 handle;
278};
279#define DRM_MODE_FB_INTERLACED (1 << 0)
280#define DRM_MODE_FB_MODIFIERS (1 << 1)
281struct drm_mode_fb_cmd2 {
282  __u32 fb_id;
283  __u32 width;
284  __u32 height;
285  __u32 pixel_format;
286  __u32 flags;
287  __u32 handles[4];
288  __u32 pitches[4];
289  __u32 offsets[4];
290  __u64 modifier[4];
291};
292#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
293#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
294#define DRM_MODE_FB_DIRTY_FLAGS 0x03
295#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
296struct drm_mode_fb_dirty_cmd {
297  __u32 fb_id;
298  __u32 flags;
299  __u32 color;
300  __u32 num_clips;
301  __u64 clips_ptr;
302};
303struct drm_mode_mode_cmd {
304  __u32 connector_id;
305  struct drm_mode_modeinfo mode;
306};
307#define DRM_MODE_CURSOR_BO 0x01
308#define DRM_MODE_CURSOR_MOVE 0x02
309#define DRM_MODE_CURSOR_FLAGS 0x03
310struct drm_mode_cursor {
311  __u32 flags;
312  __u32 crtc_id;
313  __s32 x;
314  __s32 y;
315  __u32 width;
316  __u32 height;
317  __u32 handle;
318};
319struct drm_mode_cursor2 {
320  __u32 flags;
321  __u32 crtc_id;
322  __s32 x;
323  __s32 y;
324  __u32 width;
325  __u32 height;
326  __u32 handle;
327  __s32 hot_x;
328  __s32 hot_y;
329};
330struct drm_mode_crtc_lut {
331  __u32 crtc_id;
332  __u32 gamma_size;
333  __u64 red;
334  __u64 green;
335  __u64 blue;
336};
337struct drm_color_ctm {
338  __s64 matrix[9];
339};
340struct drm_color_lut {
341  __u16 red;
342  __u16 green;
343  __u16 blue;
344  __u16 reserved;
345};
346#define DRM_MODE_PAGE_FLIP_EVENT 0x01
347#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
348#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
349#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
350#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
351#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)
352struct drm_mode_crtc_page_flip {
353  __u32 crtc_id;
354  __u32 fb_id;
355  __u32 flags;
356  __u32 reserved;
357  __u64 user_data;
358};
359struct drm_mode_crtc_page_flip_target {
360  __u32 crtc_id;
361  __u32 fb_id;
362  __u32 flags;
363  __u32 sequence;
364  __u64 user_data;
365};
366struct drm_mode_create_dumb {
367  __u32 height;
368  __u32 width;
369  __u32 bpp;
370  __u32 flags;
371  __u32 handle;
372  __u32 pitch;
373  __u64 size;
374};
375struct drm_mode_map_dumb {
376  __u32 handle;
377  __u32 pad;
378  __u64 offset;
379};
380struct drm_mode_destroy_dumb {
381  __u32 handle;
382};
383#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
384#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
385#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
386#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
387struct drm_mode_atomic {
388  __u32 flags;
389  __u32 count_objs;
390  __u64 objs_ptr;
391  __u64 count_props_ptr;
392  __u64 props_ptr;
393  __u64 prop_values_ptr;
394  __u64 reserved;
395  __u64 user_data;
396};
397struct drm_mode_create_blob {
398  __u64 data;
399  __u32 length;
400  __u32 blob_id;
401};
402struct drm_mode_destroy_blob {
403  __u32 blob_id;
404};
405#ifdef __cplusplus
406#endif
407#endif
408