drm_mode.h revision ba8d4f460b51161eb82cf1006cb34a3cc1389f47
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _DRM_MODE_H 20#define _DRM_MODE_H 21#include <linux/types.h> 22#define DRM_DISPLAY_INFO_LEN 32 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#define DRM_CONNECTOR_NAME_LEN 32 25#define DRM_DISPLAY_MODE_LEN 32 26#define DRM_PROP_NAME_LEN 32 27#define DRM_MODE_TYPE_BUILTIN (1<<0) 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 30#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 31#define DRM_MODE_TYPE_PREFERRED (1<<3) 32#define DRM_MODE_TYPE_DEFAULT (1<<4) 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define DRM_MODE_TYPE_USERDEF (1<<5) 35#define DRM_MODE_TYPE_DRIVER (1<<6) 36#define DRM_MODE_FLAG_PHSYNC (1<<0) 37#define DRM_MODE_FLAG_NHSYNC (1<<1) 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define DRM_MODE_FLAG_PVSYNC (1<<2) 40#define DRM_MODE_FLAG_NVSYNC (1<<3) 41#define DRM_MODE_FLAG_INTERLACE (1<<4) 42#define DRM_MODE_FLAG_DBLSCAN (1<<5) 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define DRM_MODE_FLAG_CSYNC (1<<6) 45#define DRM_MODE_FLAG_PCSYNC (1<<7) 46#define DRM_MODE_FLAG_NCSYNC (1<<8) 47#define DRM_MODE_FLAG_HSKEW (1<<9) 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define DRM_MODE_FLAG_BCAST (1<<10) 50#define DRM_MODE_FLAG_PIXMUX (1<<11) 51#define DRM_MODE_FLAG_DBLCLK (1<<12) 52#define DRM_MODE_FLAG_CLKDIV2 (1<<13) 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define DRM_MODE_FLAG_3D_MASK (0x1f<<14) 55#define DRM_MODE_FLAG_3D_NONE (0<<14) 56#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) 57#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) 60#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14) 61#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14) 62#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) 65#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) 66#define DRM_MODE_DPMS_ON 0 67#define DRM_MODE_DPMS_STANDBY 1 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69#define DRM_MODE_DPMS_SUSPEND 2 70#define DRM_MODE_DPMS_OFF 3 71#define DRM_MODE_SCALE_NONE 0 72#define DRM_MODE_SCALE_FULLSCREEN 1 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74#define DRM_MODE_SCALE_CENTER 2 75#define DRM_MODE_SCALE_ASPECT 3 76#define DRM_MODE_DITHERING_OFF 0 77#define DRM_MODE_DITHERING_ON 1 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79#define DRM_MODE_DITHERING_AUTO 2 80#define DRM_MODE_DIRTY_OFF 0 81#define DRM_MODE_DIRTY_ON 1 82#define DRM_MODE_DIRTY_ANNOTATE 2 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84struct drm_mode_modeinfo { 85 __u32 clock; 86 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; 87 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 __u32 vrefresh; 90 __u32 flags; 91 __u32 type; 92 char name[DRM_DISPLAY_MODE_LEN]; 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94}; 95struct drm_mode_card_res { 96 __u64 fb_id_ptr; 97 __u64 crtc_id_ptr; 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 __u64 connector_id_ptr; 100 __u64 encoder_id_ptr; 101 __u32 count_fbs; 102 __u32 count_crtcs; 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 __u32 count_connectors; 105 __u32 count_encoders; 106 __u32 min_width, max_width; 107 __u32 min_height, max_height; 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109}; 110struct drm_mode_crtc { 111 __u64 set_connectors_ptr; 112 __u32 count_connectors; 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 __u32 crtc_id; 115 __u32 fb_id; 116 __u32 x, y; 117 __u32 gamma_size; 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 __u32 mode_valid; 120 struct drm_mode_modeinfo mode; 121}; 122#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) 125struct drm_mode_set_plane { 126 __u32 plane_id; 127 __u32 crtc_id; 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 __u32 fb_id; 130 __u32 flags; 131 __s32 crtc_x, crtc_y; 132 __u32 crtc_w, crtc_h; 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 __u32 src_x, src_y; 135 __u32 src_h, src_w; 136}; 137struct drm_mode_get_plane { 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 __u32 plane_id; 140 __u32 crtc_id; 141 __u32 fb_id; 142 __u32 possible_crtcs; 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 __u32 gamma_size; 145 __u32 count_format_types; 146 __u64 format_type_ptr; 147}; 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149struct drm_mode_get_plane_res { 150 __u64 plane_id_ptr; 151 __u32 count_planes; 152}; 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154#define DRM_MODE_ENCODER_NONE 0 155#define DRM_MODE_ENCODER_DAC 1 156#define DRM_MODE_ENCODER_TMDS 2 157#define DRM_MODE_ENCODER_LVDS 3 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define DRM_MODE_ENCODER_TVDAC 4 160#define DRM_MODE_ENCODER_VIRTUAL 5 161#define DRM_MODE_ENCODER_DSI 6 162#define DRM_MODE_ENCODER_DPMST 7 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164struct drm_mode_get_encoder { 165 __u32 encoder_id; 166 __u32 encoder_type; 167 __u32 crtc_id; 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 __u32 possible_crtcs; 170 __u32 possible_clones; 171}; 172#define DRM_MODE_SUBCONNECTOR_Automatic 0 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define DRM_MODE_SUBCONNECTOR_Unknown 0 175#define DRM_MODE_SUBCONNECTOR_DVID 3 176#define DRM_MODE_SUBCONNECTOR_DVIA 4 177#define DRM_MODE_SUBCONNECTOR_Composite 5 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 180#define DRM_MODE_SUBCONNECTOR_Component 8 181#define DRM_MODE_SUBCONNECTOR_SCART 9 182#define DRM_MODE_CONNECTOR_Unknown 0 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184#define DRM_MODE_CONNECTOR_VGA 1 185#define DRM_MODE_CONNECTOR_DVII 2 186#define DRM_MODE_CONNECTOR_DVID 3 187#define DRM_MODE_CONNECTOR_DVIA 4 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189#define DRM_MODE_CONNECTOR_Composite 5 190#define DRM_MODE_CONNECTOR_SVIDEO 6 191#define DRM_MODE_CONNECTOR_LVDS 7 192#define DRM_MODE_CONNECTOR_Component 8 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194#define DRM_MODE_CONNECTOR_9PinDIN 9 195#define DRM_MODE_CONNECTOR_DisplayPort 10 196#define DRM_MODE_CONNECTOR_HDMIA 11 197#define DRM_MODE_CONNECTOR_HDMIB 12 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199#define DRM_MODE_CONNECTOR_TV 13 200#define DRM_MODE_CONNECTOR_eDP 14 201#define DRM_MODE_CONNECTOR_VIRTUAL 15 202#define DRM_MODE_CONNECTOR_DSI 16 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204struct drm_mode_get_connector { 205 __u64 encoders_ptr; 206 __u64 modes_ptr; 207 __u64 props_ptr; 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 __u64 prop_values_ptr; 210 __u32 count_modes; 211 __u32 count_props; 212 __u32 count_encoders; 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 __u32 encoder_id; 215 __u32 connector_id; 216 __u32 connector_type; 217 __u32 connector_type_id; 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 __u32 connection; 220 __u32 mm_width, mm_height; 221 __u32 subpixel; 222 __u32 pad; 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224}; 225#define DRM_MODE_PROP_PENDING (1<<0) 226#define DRM_MODE_PROP_RANGE (1<<1) 227#define DRM_MODE_PROP_IMMUTABLE (1<<2) 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229#define DRM_MODE_PROP_ENUM (1<<3) 230#define DRM_MODE_PROP_BLOB (1<<4) 231#define DRM_MODE_PROP_BITMASK (1<<5) 232#define DRM_MODE_PROP_LEGACY_TYPE ( DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK) 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0 235#define DRM_MODE_PROP_TYPE(n) ((n) << 6) 236#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1) 237#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2) 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239struct drm_mode_property_enum { 240 __u64 value; 241 char name[DRM_PROP_NAME_LEN]; 242}; 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244struct drm_mode_get_property { 245 __u64 values_ptr; 246 __u64 enum_blob_ptr; 247 __u32 prop_id; 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 __u32 flags; 250 char name[DRM_PROP_NAME_LEN]; 251 __u32 count_values; 252 __u32 count_enum_blobs; 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254}; 255struct drm_mode_connector_set_property { 256 __u64 value; 257 __u32 prop_id; 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 __u32 connector_id; 260}; 261struct drm_mode_obj_get_properties { 262 __u64 props_ptr; 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 __u64 prop_values_ptr; 265 __u32 count_props; 266 __u32 obj_id; 267 __u32 obj_type; 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269}; 270struct drm_mode_obj_set_property { 271 __u64 value; 272 __u32 prop_id; 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 __u32 obj_id; 275 __u32 obj_type; 276}; 277struct drm_mode_get_blob { 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 __u32 blob_id; 280 __u32 length; 281 __u64 data; 282}; 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284struct drm_mode_fb_cmd { 285 __u32 fb_id; 286 __u32 width, height; 287 __u32 pitch; 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 __u32 bpp; 290 __u32 depth; 291 __u32 handle; 292}; 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294#define DRM_MODE_FB_INTERLACED (1<<0) 295struct drm_mode_fb_cmd2 { 296 __u32 fb_id; 297 __u32 width, height; 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 __u32 pixel_format; 300 __u32 flags; 301 __u32 handles[4]; 302 __u32 pitches[4]; 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 __u32 offsets[4]; 305}; 306#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 307#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309#define DRM_MODE_FB_DIRTY_FLAGS 0x03 310#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256 311struct drm_mode_fb_dirty_cmd { 312 __u32 fb_id; 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 __u32 flags; 315 __u32 color; 316 __u32 num_clips; 317 __u64 clips_ptr; 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319}; 320struct drm_mode_mode_cmd { 321 __u32 connector_id; 322 struct drm_mode_modeinfo mode; 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324}; 325#define DRM_MODE_CURSOR_BO 0x01 326#define DRM_MODE_CURSOR_MOVE 0x02 327#define DRM_MODE_CURSOR_FLAGS 0x03 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329struct drm_mode_cursor { 330 __u32 flags; 331 __u32 crtc_id; 332 __s32 x; 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 __s32 y; 335 __u32 width; 336 __u32 height; 337 __u32 handle; 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339}; 340struct drm_mode_cursor2 { 341 __u32 flags; 342 __u32 crtc_id; 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 __s32 x; 345 __s32 y; 346 __u32 width; 347 __u32 height; 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 __u32 handle; 350 __s32 hot_x; 351 __s32 hot_y; 352}; 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354struct drm_mode_crtc_lut { 355 __u32 crtc_id; 356 __u32 gamma_size; 357 __u64 red; 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 __u64 green; 360 __u64 blue; 361}; 362#define DRM_MODE_PAGE_FLIP_EVENT 0x01 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364#define DRM_MODE_PAGE_FLIP_ASYNC 0x02 365#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC) 366struct drm_mode_crtc_page_flip { 367 __u32 crtc_id; 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 __u32 fb_id; 370 __u32 flags; 371 __u32 reserved; 372 __u64 user_data; 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374}; 375struct drm_mode_create_dumb { 376 uint32_t height; 377 uint32_t width; 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 uint32_t bpp; 380 uint32_t flags; 381 uint32_t handle; 382 uint32_t pitch; 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 uint64_t size; 385}; 386struct drm_mode_map_dumb { 387 __u32 handle; 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 __u32 pad; 390 __u64 offset; 391}; 392struct drm_mode_destroy_dumb { 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 uint32_t handle; 395}; 396#endif 397