1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _ASM_X86_KVM_H 20#define _ASM_X86_KVM_H 21#include <linux/types.h> 22#include <linux/ioctl.h> 23#define KVM_PIO_PAGE_OFFSET 1 24#define KVM_COALESCED_MMIO_PAGE_OFFSET 2 25#define DE_VECTOR 0 26#define DB_VECTOR 1 27#define BP_VECTOR 3 28#define OF_VECTOR 4 29#define BR_VECTOR 5 30#define UD_VECTOR 6 31#define NM_VECTOR 7 32#define DF_VECTOR 8 33#define TS_VECTOR 10 34#define NP_VECTOR 11 35#define SS_VECTOR 12 36#define GP_VECTOR 13 37#define PF_VECTOR 14 38#define MF_VECTOR 16 39#define AC_VECTOR 17 40#define MC_VECTOR 18 41#define XM_VECTOR 19 42#define VE_VECTOR 20 43#define __KVM_HAVE_PIT 44#define __KVM_HAVE_IOAPIC 45#define __KVM_HAVE_IRQ_LINE 46#define __KVM_HAVE_MSI 47#define __KVM_HAVE_USER_NMI 48#define __KVM_HAVE_GUEST_DEBUG 49#define __KVM_HAVE_MSIX 50#define __KVM_HAVE_MCE 51#define __KVM_HAVE_PIT_STATE2 52#define __KVM_HAVE_XEN_HVM 53#define __KVM_HAVE_VCPU_EVENTS 54#define __KVM_HAVE_DEBUGREGS 55#define __KVM_HAVE_XSAVE 56#define __KVM_HAVE_XCRS 57#define __KVM_HAVE_READONLY_MEM 58#define KVM_NR_INTERRUPTS 256 59struct kvm_memory_alias { 60 __u32 slot; 61 __u32 flags; 62 __u64 guest_phys_addr; 63 __u64 memory_size; 64 __u64 target_phys_addr; 65}; 66struct kvm_pic_state { 67 __u8 last_irr; 68 __u8 irr; 69 __u8 imr; 70 __u8 isr; 71 __u8 priority_add; 72 __u8 irq_base; 73 __u8 read_reg_select; 74 __u8 poll; 75 __u8 special_mask; 76 __u8 init_state; 77 __u8 auto_eoi; 78 __u8 rotate_on_auto_eoi; 79 __u8 special_fully_nested_mode; 80 __u8 init4; 81 __u8 elcr; 82 __u8 elcr_mask; 83}; 84#define KVM_IOAPIC_NUM_PINS 24 85struct kvm_ioapic_state { 86 __u64 base_address; 87 __u32 ioregsel; 88 __u32 id; 89 __u32 irr; 90 __u32 pad; 91 union { 92 __u64 bits; 93 struct { 94 __u8 vector; 95 __u8 delivery_mode : 3; 96 __u8 dest_mode : 1; 97 __u8 delivery_status : 1; 98 __u8 polarity : 1; 99 __u8 remote_irr : 1; 100 __u8 trig_mode : 1; 101 __u8 mask : 1; 102 __u8 reserve : 7; 103 __u8 reserved[4]; 104 __u8 dest_id; 105 } fields; 106 } redirtbl[KVM_IOAPIC_NUM_PINS]; 107}; 108#define KVM_IRQCHIP_PIC_MASTER 0 109#define KVM_IRQCHIP_PIC_SLAVE 1 110#define KVM_IRQCHIP_IOAPIC 2 111#define KVM_NR_IRQCHIPS 3 112#define KVM_RUN_X86_SMM (1 << 0) 113struct kvm_regs { 114 __u64 rax, rbx, rcx, rdx; 115 __u64 rsi, rdi, rsp, rbp; 116 __u64 r8, r9, r10, r11; 117 __u64 r12, r13, r14, r15; 118 __u64 rip, rflags; 119}; 120#define KVM_APIC_REG_SIZE 0x400 121struct kvm_lapic_state { 122 char regs[KVM_APIC_REG_SIZE]; 123}; 124struct kvm_segment { 125 __u64 base; 126 __u32 limit; 127 __u16 selector; 128 __u8 type; 129 __u8 present, dpl, db, s, l, g, avl; 130 __u8 unusable; 131 __u8 padding; 132}; 133struct kvm_dtable { 134 __u64 base; 135 __u16 limit; 136 __u16 padding[3]; 137}; 138struct kvm_sregs { 139 struct kvm_segment cs, ds, es, fs, gs, ss; 140 struct kvm_segment tr, ldt; 141 struct kvm_dtable gdt, idt; 142 __u64 cr0, cr2, cr3, cr4, cr8; 143 __u64 efer; 144 __u64 apic_base; 145 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; 146}; 147struct kvm_fpu { 148 __u8 fpr[8][16]; 149 __u16 fcw; 150 __u16 fsw; 151 __u8 ftwx; 152 __u8 pad1; 153 __u16 last_opcode; 154 __u64 last_ip; 155 __u64 last_dp; 156 __u8 xmm[16][16]; 157 __u32 mxcsr; 158 __u32 pad2; 159}; 160struct kvm_msr_entry { 161 __u32 index; 162 __u32 reserved; 163 __u64 data; 164}; 165struct kvm_msrs { 166 __u32 nmsrs; 167 __u32 pad; 168 struct kvm_msr_entry entries[0]; 169}; 170struct kvm_msr_list { 171 __u32 nmsrs; 172 __u32 indices[0]; 173}; 174struct kvm_cpuid_entry { 175 __u32 function; 176 __u32 eax; 177 __u32 ebx; 178 __u32 ecx; 179 __u32 edx; 180 __u32 padding; 181}; 182struct kvm_cpuid { 183 __u32 nent; 184 __u32 padding; 185 struct kvm_cpuid_entry entries[0]; 186}; 187struct kvm_cpuid_entry2 { 188 __u32 function; 189 __u32 index; 190 __u32 flags; 191 __u32 eax; 192 __u32 ebx; 193 __u32 ecx; 194 __u32 edx; 195 __u32 padding[3]; 196}; 197#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0) 198#define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1) 199#define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2) 200struct kvm_cpuid2 { 201 __u32 nent; 202 __u32 padding; 203 struct kvm_cpuid_entry2 entries[0]; 204}; 205struct kvm_pit_channel_state { 206 __u32 count; 207 __u16 latched_count; 208 __u8 count_latched; 209 __u8 status_latched; 210 __u8 status; 211 __u8 read_state; 212 __u8 write_state; 213 __u8 write_latch; 214 __u8 rw_mode; 215 __u8 mode; 216 __u8 bcd; 217 __u8 gate; 218 __s64 count_load_time; 219}; 220struct kvm_debug_exit_arch { 221 __u32 exception; 222 __u32 pad; 223 __u64 pc; 224 __u64 dr6; 225 __u64 dr7; 226}; 227#define KVM_GUESTDBG_USE_SW_BP 0x00010000 228#define KVM_GUESTDBG_USE_HW_BP 0x00020000 229#define KVM_GUESTDBG_INJECT_DB 0x00040000 230#define KVM_GUESTDBG_INJECT_BP 0x00080000 231struct kvm_guest_debug_arch { 232 __u64 debugreg[8]; 233}; 234struct kvm_pit_state { 235 struct kvm_pit_channel_state channels[3]; 236}; 237#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 238struct kvm_pit_state2 { 239 struct kvm_pit_channel_state channels[3]; 240 __u32 flags; 241 __u32 reserved[9]; 242}; 243struct kvm_reinject_control { 244 __u8 pit_reinject; 245 __u8 reserved[31]; 246}; 247#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 248#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 249#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 250#define KVM_VCPUEVENT_VALID_SMM 0x00000008 251#define KVM_X86_SHADOW_INT_MOV_SS 0x01 252#define KVM_X86_SHADOW_INT_STI 0x02 253struct kvm_vcpu_events { 254 struct { 255 __u8 injected; 256 __u8 nr; 257 __u8 has_error_code; 258 __u8 pad; 259 __u32 error_code; 260 } exception; 261 struct { 262 __u8 injected; 263 __u8 nr; 264 __u8 soft; 265 __u8 shadow; 266 } interrupt; 267 struct { 268 __u8 injected; 269 __u8 pending; 270 __u8 masked; 271 __u8 pad; 272 } nmi; 273 __u32 sipi_vector; 274 __u32 flags; 275 struct { 276 __u8 smm; 277 __u8 pending; 278 __u8 smm_inside_nmi; 279 __u8 latched_init; 280 } smi; 281 __u32 reserved[9]; 282}; 283struct kvm_debugregs { 284 __u64 db[4]; 285 __u64 dr6; 286 __u64 dr7; 287 __u64 flags; 288 __u64 reserved[9]; 289}; 290struct kvm_xsave { 291 __u32 region[1024]; 292}; 293#define KVM_MAX_XCRS 16 294struct kvm_xcr { 295 __u32 xcr; 296 __u32 reserved; 297 __u64 value; 298}; 299struct kvm_xcrs { 300 __u32 nr_xcrs; 301 __u32 flags; 302 struct kvm_xcr xcrs[KVM_MAX_XCRS]; 303 __u64 padding[16]; 304}; 305struct kvm_sync_regs { 306}; 307#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) 308#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) 309#endif 310