1/* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9/memreserve/ 0x80000000 0x00010000; 10 11/ { 12}; 13 14/ { 15 model = "FVP Base"; 16 compatible = "arm,vfp-base", "arm,vexpress"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 aliases { 24 serial0 = &v2m_serial0; 25 serial1 = &v2m_serial1; 26 serial2 = &v2m_serial2; 27 serial3 = &v2m_serial3; 28 }; 29 30 psci { 31 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 32 method = "smc"; 33 cpu_suspend = <0xc4000001>; 34 cpu_off = <0x84000002>; 35 cpu_on = <0xc4000003>; 36 sys_poweroff = <0x84000008>; 37 sys_reset = <0x84000009>; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 cpu-map { 45 cluster0 { 46 core0 { 47 cpu = <&CPU0>; 48 }; 49 core1 { 50 cpu = <&CPU1>; 51 }; 52 core2 { 53 cpu = <&CPU2>; 54 }; 55 core3 { 56 cpu = <&CPU3>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&CPU4>; 63 }; 64 core1 { 65 cpu = <&CPU5>; 66 }; 67 core2 { 68 cpu = <&CPU6>; 69 }; 70 core3 { 71 cpu = <&CPU7>; 72 }; 73 }; 74 }; 75 76 idle-states { 77 entry-method = "arm,psci"; 78 79 CPU_SLEEP_0: cpu-sleep-0 { 80 compatible = "arm,idle-state"; 81 local-timer-stop; 82 arm,psci-suspend-param = <0x0010000>; 83 entry-latency-us = <40>; 84 exit-latency-us = <100>; 85 min-residency-us = <150>; 86 }; 87 88 CLUSTER_SLEEP_0: cluster-sleep-0 { 89 compatible = "arm,idle-state"; 90 local-timer-stop; 91 arm,psci-suspend-param = <0x1010000>; 92 entry-latency-us = <500>; 93 exit-latency-us = <1000>; 94 min-residency-us = <2500>; 95 }; 96 }; 97 98 CPU0:cpu@0 { 99 device_type = "cpu"; 100 compatible = "arm,armv8"; 101 reg = <0x0 0x0>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 104 next-level-cache = <&L2_0>; 105 }; 106 107 CPU1:cpu@1 { 108 device_type = "cpu"; 109 compatible = "arm,armv8"; 110 reg = <0x0 0x1>; 111 enable-method = "psci"; 112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 113 next-level-cache = <&L2_0>; 114 }; 115 116 CPU2:cpu@2 { 117 device_type = "cpu"; 118 compatible = "arm,armv8"; 119 reg = <0x0 0x2>; 120 enable-method = "psci"; 121 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 122 next-level-cache = <&L2_0>; 123 }; 124 125 CPU3:cpu@3 { 126 device_type = "cpu"; 127 compatible = "arm,armv8"; 128 reg = <0x0 0x3>; 129 enable-method = "psci"; 130 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 131 next-level-cache = <&L2_0>; 132 }; 133 134 CPU4:cpu@100 { 135 device_type = "cpu"; 136 compatible = "arm,armv8"; 137 reg = <0x0 0x100>; 138 enable-method = "psci"; 139 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 140 next-level-cache = <&L2_0>; 141 }; 142 143 CPU5:cpu@101 { 144 device_type = "cpu"; 145 compatible = "arm,armv8"; 146 reg = <0x0 0x101>; 147 enable-method = "psci"; 148 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 149 next-level-cache = <&L2_0>; 150 }; 151 152 CPU6:cpu@102 { 153 device_type = "cpu"; 154 compatible = "arm,armv8"; 155 reg = <0x0 0x102>; 156 enable-method = "psci"; 157 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 158 next-level-cache = <&L2_0>; 159 }; 160 161 CPU7:cpu@103 { 162 device_type = "cpu"; 163 compatible = "arm,armv8"; 164 reg = <0x0 0x103>; 165 enable-method = "psci"; 166 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 167 next-level-cache = <&L2_0>; 168 }; 169 170 L2_0: l2-cache0 { 171 compatible = "cache"; 172 }; 173 }; 174 175 memory@80000000 { 176 device_type = "memory"; 177 reg = <0x00000000 0x80000000 0 0x7F000000>, 178 <0x00000008 0x80000000 0 0x80000000>; 179 }; 180 181 gic: interrupt-controller@2f000000 { 182 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 183 #interrupt-cells = <3>; 184 #address-cells = <0>; 185 interrupt-controller; 186 reg = <0x0 0x2f000000 0 0x10000>, 187 <0x0 0x2c000000 0 0x2000>, 188 <0x0 0x2c010000 0 0x2000>, 189 <0x0 0x2c02F000 0 0x2000>; 190 interrupts = <1 9 0xf04>; 191 }; 192 193 timer { 194 compatible = "arm,armv8-timer"; 195 interrupts = <1 13 0xff01>, 196 <1 14 0xff01>, 197 <1 11 0xff01>, 198 <1 10 0xff01>; 199 clock-frequency = <100000000>; 200 }; 201 202 timer@2a810000 { 203 compatible = "arm,armv7-timer-mem"; 204 reg = <0x0 0x2a810000 0x0 0x10000>; 205 clock-frequency = <100000000>; 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 frame@2a830000 { 210 frame-number = <1>; 211 interrupts = <0 26 4>; 212 reg = <0x0 0x2a830000 0x0 0x10000>; 213 }; 214 }; 215 216 pmu { 217 compatible = "arm,armv8-pmuv3"; 218 interrupts = <0 60 4>, 219 <0 61 4>, 220 <0 62 4>, 221 <0 63 4>; 222 }; 223 224 smb { 225 compatible = "simple-bus"; 226 227 #address-cells = <2>; 228 #size-cells = <1>; 229 ranges = <0 0 0 0x08000000 0x04000000>, 230 <1 0 0 0x14000000 0x04000000>, 231 <2 0 0 0x18000000 0x04000000>, 232 <3 0 0 0x1c000000 0x04000000>, 233 <4 0 0 0x0c000000 0x04000000>, 234 <5 0 0 0x10000000 0x04000000>; 235 236 /include/ "rtsm_ve-motherboard.dtsi" 237 }; 238 239 panels { 240 panel@0 { 241 compatible = "panel"; 242 mode = "XVGA"; 243 refresh = <60>; 244 xres = <1024>; 245 yres = <768>; 246 pixclock = <15748>; 247 left_margin = <152>; 248 right_margin = <48>; 249 upper_margin = <23>; 250 lower_margin = <3>; 251 hsync_len = <104>; 252 vsync_len = <4>; 253 sync = <0>; 254 vmode = "FB_VMODE_NONINTERLACED"; 255 tim2 = "TIM2_BCD", "TIM2_IPC"; 256 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; 257 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; 258 bpp = <16>; 259 }; 260 }; 261}; 262