1/*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <asm_macros.S>
7#include <platform_def.h>
8
9	.weak	plat_arm_calc_core_pos
10	.weak	plat_my_core_pos
11	.globl	plat_crash_console_init
12	.globl	plat_crash_console_putc
13	.globl	plat_crash_console_flush
14	.globl	platform_mem_init
15	.globl	arm_disable_spe
16
17
18	/* -----------------------------------------------------
19	 *  unsigned int plat_my_core_pos(void)
20	 *  This function uses the plat_arm_calc_core_pos()
21	 *  definition to get the index of the calling CPU.
22	 * -----------------------------------------------------
23	 */
24func plat_my_core_pos
25	mrs	x0, mpidr_el1
26	b	plat_arm_calc_core_pos
27endfunc plat_my_core_pos
28
29	/* -----------------------------------------------------
30	 *  unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
31	 *  Helper function to calculate the core position.
32	 *  With this function: CorePos = (ClusterId * 4) +
33	 *  				  CoreId
34	 * -----------------------------------------------------
35	 */
36func plat_arm_calc_core_pos
37	and	x1, x0, #MPIDR_CPU_MASK
38	and	x0, x0, #MPIDR_CLUSTER_MASK
39	add	x0, x1, x0, LSR #6
40	ret
41endfunc plat_arm_calc_core_pos
42
43	/* ---------------------------------------------
44	 * int plat_crash_console_init(void)
45	 * Function to initialize the crash console
46	 * without a C Runtime to print crash report.
47	 * Clobber list : x0 - x4
48	 * ---------------------------------------------
49	 */
50func plat_crash_console_init
51	mov_imm	x0, PLAT_ARM_CRASH_UART_BASE
52	mov_imm	x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ
53	mov_imm	x2, ARM_CONSOLE_BAUDRATE
54	b	console_core_init
55endfunc plat_crash_console_init
56
57	/* ---------------------------------------------
58	 * int plat_crash_console_putc(int c)
59	 * Function to print a character on the crash
60	 * console without a C Runtime.
61	 * Clobber list : x1, x2
62	 * ---------------------------------------------
63	 */
64func plat_crash_console_putc
65	mov_imm	x1, PLAT_ARM_CRASH_UART_BASE
66	b	console_core_putc
67endfunc plat_crash_console_putc
68
69	/* ---------------------------------------------
70	 * int plat_crash_console_flush()
71	 * Function to force a write of all buffered
72	 * data that hasn't been output.
73	 * Out : return -1 on error else return 0.
74	 * Clobber list : r0 - r1
75	 * ---------------------------------------------
76	 */
77func plat_crash_console_flush
78	mov_imm	x1, PLAT_ARM_CRASH_UART_BASE
79	b	console_core_flush
80endfunc plat_crash_console_flush
81
82	/* ---------------------------------------------------------------------
83	 * We don't need to carry out any memory initialization on ARM
84	 * platforms. The Secure RAM is accessible straight away.
85	 * ---------------------------------------------------------------------
86	 */
87func platform_mem_init
88	ret
89endfunc platform_mem_init
90
91	/* -----------------------------------------------------
92	 * void arm_disable_spe (void);
93	 * -----------------------------------------------------
94	 */
95#if ENABLE_SPE_FOR_LOWER_ELS
96func arm_disable_spe
97	/* Detect if SPE is implemented */
98	mrs	x0, id_aa64dfr0_el1
99	ubfx	x0, x0, #ID_AA64DFR0_PMS_SHIFT, #ID_AA64DFR0_PMS_LENGTH
100	cmp	x0, #0x1
101	b.ne	1f
102
103	/* Drain buffered data */
104	.arch	armv8.2-a+profile
105	psb	csync
106	dsb	nsh
107
108	/* Disable Profiling Buffer */
109	mrs	x0, pmblimitr_el1
110	bic	x0, x0, #1
111	msr	pmblimitr_el1, x0
112	isb
113	.arch	armv8-a
1141:
115	ret
116endfunc arm_disable_spe
117#endif
118
119/*
120 * Need to use coherent stack when ARM Cryptocell is used to autheticate images
121 * since Cryptocell uses DMA to transfer data and it is not coherent with the
122 * AP CPU.
123 */
124#if ARM_CRYPTOCELL_INTEG
125#if defined(IMAGE_BL1) || defined(IMAGE_BL2)
126	.globl	plat_get_my_stack
127	.globl	plat_set_my_stack
128	.local	platform_coherent_stacks
129
130	/* -------------------------------------------------------
131	 * uintptr_t plat_get_my_stack ()
132	 *
133	 * For cold-boot BL images, only the primary CPU needs a
134	 * stack. This function returns the stack pointer for a
135	 * stack allocated in coherent memory.
136	 * -------------------------------------------------------
137	 */
138func plat_get_my_stack
139	get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE
140	ret
141endfunc plat_get_my_stack
142
143	/* -------------------------------------------------------
144	 * void plat_set_my_stack ()
145	 *
146	 * For cold-boot BL images, only the primary CPU needs a
147	 * stack. This function sets the stack pointer to a stack
148	 * allocated in coherent memory.
149	 * -------------------------------------------------------
150	 */
151func plat_set_my_stack
152	get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE
153	mov sp, x0
154	ret
155endfunc plat_set_my_stack
156
157	/* ----------------------------------------------------
158	 * Single cpu stack in coherent memory.
159	 * ----------------------------------------------------
160	 */
161declare_stack platform_coherent_stacks, tzfw_coherent_mem, \
162		PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE
163
164#endif	/* defined(IMAGE_BL1) || defined(IMAGE_BL2) */
165#endif	/* ARM_CRYPTOCELL_INTEG */
166