1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch_helpers.h> 8#include <arm_gic.h> 9#include <assert.h> 10#include <bl_common.h> 11#include <cci.h> 12#include <console.h> 13#include <debug.h> 14#include <errno.h> 15#include <gicv2.h> 16#include <hi6220.h> 17#include <hisi_ipc.h> 18#include <hisi_pwrc.h> 19#include <mmio.h> 20#include <platform_def.h> 21 22#include "hikey_def.h" 23#include "hikey_private.h" 24 25/* 26 * The next 2 constants identify the extents of the code & RO data region. 27 * These addresses are used by the MMU setup code and therefore they must be 28 * page-aligned. It is the responsibility of the linker script to ensure that 29 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 30 */ 31#define BL31_RO_BASE (unsigned long)(&__RO_START__) 32#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 33 34/* 35 * The next 2 constants identify the extents of the coherent memory region. 36 * These addresses are used by the MMU setup code and therefore they must be 37 * page-aligned. It is the responsibility of the linker script to ensure that 38 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 39 * page-aligned addresses. 40 */ 41#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 42#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 43 44static entry_point_info_t bl32_ep_info; 45static entry_point_info_t bl33_ep_info; 46 47/****************************************************************************** 48 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 49 * interrupts. 50 *****************************************************************************/ 51const unsigned int g0_interrupt_array[] = { 52 IRQ_SEC_PHY_TIMER, 53 IRQ_SEC_SGI_0 54}; 55 56/* 57 * Ideally `arm_gic_data` structure definition should be a `const` but it is 58 * kept as modifiable for overwriting with different GICD and GICC base when 59 * running on FVP with VE memory map. 60 */ 61gicv2_driver_data_t hikey_gic_data = { 62 .gicd_base = PLAT_ARM_GICD_BASE, 63 .gicc_base = PLAT_ARM_GICC_BASE, 64 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 65 .g0_interrupt_array = g0_interrupt_array, 66}; 67 68static const int cci_map[] = { 69 CCI400_SL_IFACE3_CLUSTER_IX, 70 CCI400_SL_IFACE4_CLUSTER_IX 71}; 72 73entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 74{ 75 entry_point_info_t *next_image_info; 76 77 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 78 79 /* None of the images on this platform can have 0x0 as the entrypoint */ 80 if (next_image_info->pc) 81 return next_image_info; 82 return NULL; 83} 84 85#if LOAD_IMAGE_V2 86void bl31_early_platform_setup(void *from_bl2, 87 void *plat_params_from_bl2) 88#else 89void bl31_early_platform_setup(bl31_params_t *from_bl2, 90 void *plat_params_from_bl2) 91#endif 92{ 93 /* Initialize the console to provide early debug support */ 94 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 95 96 /* Initialize CCI driver */ 97 cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map)); 98 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 99 100#if LOAD_IMAGE_V2 101 /* 102 * Check params passed from BL2 should not be NULL, 103 */ 104 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 105 assert(params_from_bl2 != NULL); 106 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 107 assert(params_from_bl2->h.version >= VERSION_2); 108 109 bl_params_node_t *bl_params = params_from_bl2->head; 110 111 /* 112 * Copy BL33 and BL32 (if present), entry point information. 113 * They are stored in Secure RAM, in BL2's address space. 114 */ 115 while (bl_params) { 116 if (bl_params->image_id == BL32_IMAGE_ID) 117 bl32_ep_info = *bl_params->ep_info; 118 119 if (bl_params->image_id == BL33_IMAGE_ID) 120 bl33_ep_info = *bl_params->ep_info; 121 122 bl_params = bl_params->next_params_info; 123 } 124 125 if (bl33_ep_info.pc == 0) 126 panic(); 127 128#else /* LOAD_IMAGE_V2 */ 129 130 /* 131 * Check params passed from BL2 should not be NULL, 132 */ 133 assert(from_bl2 != NULL); 134 assert(from_bl2->h.type == PARAM_BL31); 135 assert(from_bl2->h.version >= VERSION_1); 136 137 /* 138 * Copy BL3-2 and BL3-3 entry point information. 139 * They are stored in Secure RAM, in BL2's address space. 140 */ 141 bl32_ep_info = *from_bl2->bl32_ep_info; 142 bl33_ep_info = *from_bl2->bl33_ep_info; 143#endif /* LOAD_IMAGE_V2 */ 144} 145 146void bl31_plat_arch_setup(void) 147{ 148 hikey_init_mmu_el3(BL31_BASE, 149 BL31_LIMIT - BL31_BASE, 150 BL31_RO_BASE, 151 BL31_RO_LIMIT, 152 BL31_COHERENT_RAM_BASE, 153 BL31_COHERENT_RAM_LIMIT); 154} 155 156/* Initialize EDMAC controller with non-secure mode. */ 157static void hikey_edma_init(void) 158{ 159 int i; 160 uint32_t non_secure; 161 162 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 163 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 164 165 for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) { 166 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 167 } 168} 169 170void bl31_platform_setup(void) 171{ 172 /* Initialize the GIC driver, cpu and distributor interfaces */ 173 gicv2_driver_init(&hikey_gic_data); 174 gicv2_distif_init(); 175 gicv2_pcpu_distif_init(); 176 gicv2_cpuif_enable(); 177 178 hikey_edma_init(); 179 180 hisi_ipc_init(); 181 hisi_pwrc_setup(); 182} 183 184void bl31_plat_runtime_setup(void) 185{ 186} 187