1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <arm_gic.h>
9#include <assert.h>
10#include <bl_common.h>
11#include <console.h>
12#include <context.h>
13#include <context_mgmt.h>
14#include <debug.h>
15#include <mmio.h>
16#include <plat_arm.h>
17#include <platform.h>
18#include <psci.h>
19#include "hi3798cv200.h"
20#include "plat_private.h"
21#include "platform_def.h"
22
23#define REG_PERI_CPU_RVBARADDR		0xF8A80034
24#define REG_PERI_CPU_AARCH_MODE		0xF8A80030
25
26#define REG_CPU_LP_CPU_SW_BEGIN		10
27#define CPU_REG_COREPO_SRST		12
28#define CPU_REG_CORE_SRST		8
29
30static void poplar_cpu_standby(plat_local_state_t cpu_state)
31{
32	dsb();
33	wfi();
34}
35
36static int poplar_pwr_domain_on(u_register_t mpidr)
37{
38	unsigned int cpu = plat_core_pos_by_mpidr(mpidr);
39	unsigned int regval, regval_bak;
40
41	/* Select 400MHz before start slave cores */
42	regval_bak = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP));
43	mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x206);
44	mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x606);
45
46	/* Clear the slave cpu arm_por_srst_req reset */
47	regval = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST));
48	regval &= ~(1 << (cpu + CPU_REG_COREPO_SRST));
49	mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval);
50
51	/* Clear the slave cpu reset */
52	regval = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST));
53	regval &= ~(1 << (cpu + CPU_REG_CORE_SRST));
54	mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval);
55
56	/* Restore cpu frequency */
57	regval = regval_bak & (~(1 << REG_CPU_LP_CPU_SW_BEGIN));
58	mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval);
59	mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval_bak);
60
61	return PSCI_E_SUCCESS;
62}
63
64static void poplar_pwr_domain_off(const psci_power_state_t *target_state)
65{
66	assert(0);
67}
68
69static void poplar_pwr_domain_suspend(const psci_power_state_t *target_state)
70{
71	assert(0);
72}
73
74static void poplar_pwr_domain_on_finish(const psci_power_state_t *target_state)
75{
76	assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
77					PLAT_MAX_OFF_STATE);
78
79	/* Enable the gic cpu interface */
80	plat_arm_gic_pcpu_init();
81
82	/* Program the gic per-cpu distributor or re-distributor interface */
83	plat_arm_gic_cpuif_enable();
84}
85
86static void poplar_pwr_domain_suspend_finish(
87		const psci_power_state_t *target_state)
88{
89	assert(0);
90}
91
92static void __dead2 poplar_system_off(void)
93{
94	ERROR("Poplar System Off: operation not handled.\n");
95	panic();
96}
97
98static void __dead2 poplar_system_reset(void)
99{
100	mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0xc00), 0x1ACCE551);
101	mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x0),   0x00000100);
102	mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x8),   0x00000003);
103
104	wfi();
105	ERROR("Poplar System Reset: operation not handled.\n");
106	panic();
107}
108
109static int32_t poplar_validate_power_state(unsigned int power_state,
110					   psci_power_state_t *req_state)
111{
112	VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
113
114	int pstate = psci_get_pstate_type(power_state);
115
116	assert(req_state);
117
118	/* Sanity check the requested state */
119	if (pstate == PSTATE_TYPE_STANDBY)
120		req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
121	else
122		req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
123
124	/* We expect the 'state id' to be zero */
125	if (psci_get_pstate_id(power_state))
126		return PSCI_E_INVALID_PARAMS;
127
128	return PSCI_E_SUCCESS;
129}
130
131static int poplar_validate_ns_entrypoint(uintptr_t entrypoint)
132{
133	/*
134	 * Check if the non secure entrypoint lies within the non
135	 * secure DRAM.
136	 */
137	if ((entrypoint >= DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE)))
138		return PSCI_E_SUCCESS;
139
140	return PSCI_E_INVALID_ADDRESS;
141}
142
143static void poplar_get_sys_suspend_power_state(psci_power_state_t *req_state)
144{
145	int i;
146
147	for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
148		req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
149}
150
151static const plat_psci_ops_t poplar_plat_psci_ops = {
152	.cpu_standby			= poplar_cpu_standby,
153	.pwr_domain_on			= poplar_pwr_domain_on,
154	.pwr_domain_off			= poplar_pwr_domain_off,
155	.pwr_domain_suspend		= poplar_pwr_domain_suspend,
156	.pwr_domain_on_finish		= poplar_pwr_domain_on_finish,
157	.pwr_domain_suspend_finish	= poplar_pwr_domain_suspend_finish,
158	.system_off			= poplar_system_off,
159	.system_reset			= poplar_system_reset,
160	.validate_power_state		= poplar_validate_power_state,
161	.validate_ns_entrypoint		= poplar_validate_ns_entrypoint,
162	.get_sys_suspend_power_state	= poplar_get_sys_suspend_power_state,
163};
164
165int plat_setup_psci_ops(uintptr_t sec_entrypoint,
166			const plat_psci_ops_t **psci_ops)
167{
168	*psci_ops = &poplar_plat_psci_ops;
169
170	mmio_write_32((uintptr_t)REG_PERI_CPU_AARCH_MODE, 0xF);
171	mmio_write_32((uintptr_t)REG_PERI_CPU_RVBARADDR, sec_entrypoint);
172	return 0;
173}
174