1/*
2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <gic_common.h>
11#include <interrupt_props.h>
12#include "mt8173_def.h"
13
14
15/*******************************************************************************
16 * Platform binary types for linking
17 ******************************************************************************/
18#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
19#define PLATFORM_LINKER_ARCH		aarch64
20
21/*******************************************************************************
22 * Generic platform constants
23 ******************************************************************************/
24
25/* Size of cacheable stacks */
26#if defined(IMAGE_BL1)
27#define PLATFORM_STACK_SIZE 0x440
28#elif defined(IMAGE_BL2)
29#define PLATFORM_STACK_SIZE 0x400
30#elif defined(IMAGE_BL31)
31#define PLATFORM_STACK_SIZE 0x800
32#elif defined(IMAGE_BL32)
33#define PLATFORM_STACK_SIZE 0x440
34#endif
35
36#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
37
38#define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL2
39#if !ENABLE_PLAT_COMPAT
40#define PLAT_MAX_PWR_LVL		2
41#define PLAT_MAX_RET_STATE		1
42#define PLAT_MAX_OFF_STATE		2
43#endif
44#define PLATFORM_SYSTEM_COUNT		1
45#define PLATFORM_CLUSTER_COUNT		2
46#define PLATFORM_CLUSTER0_CORE_COUNT	4
47#define PLATFORM_CLUSTER1_CORE_COUNT	2
48#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT +	\
49					 PLATFORM_CLUSTER0_CORE_COUNT)
50#define PLATFORM_MAX_CPUS_PER_CLUSTER	4
51#define PLATFORM_NUM_AFFS		(PLATFORM_SYSTEM_COUNT +	\
52					 PLATFORM_CLUSTER_COUNT +	\
53					 PLATFORM_CORE_COUNT)
54
55/*******************************************************************************
56 * Platform memory map related constants
57 ******************************************************************************/
58/*
59 * MT8173 SRAM memory layout
60 * 0x100000 +-------------------+
61 *          | shared mem (4KB)  |
62 * 0x101000 +-------------------+
63 *          |                   |
64 *          |   BL3-1 (124KB)   |
65 *          |                   |
66 * 0x120000 +-------------------+
67 *          |  reserved (64KB)  |
68 * 0x130000 +-------------------+
69 */
70/* TF txet, ro, rw, xlat table, coherent memory ... etc.
71 * Size: release: 128KB, debug: 128KB
72 */
73#define TZRAM_BASE		(0x100000)
74#if DEBUG
75#define TZRAM_SIZE		(0x20000)
76#else
77#define TZRAM_SIZE		(0x20000)
78#endif
79
80/* Reserved: 64KB */
81#define TZRAM2_BASE		(TZRAM_BASE + TZRAM_SIZE)
82#define TZRAM2_SIZE		(0x10000)
83
84/*******************************************************************************
85 * BL31 specific defines.
86 ******************************************************************************/
87/*
88 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
89 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
90 * little space for growth.
91 */
92#define BL31_BASE		(TZRAM_BASE + 0x1000)
93#define BL31_LIMIT		(TZRAM_BASE + TZRAM_SIZE)
94#define TZRAM2_LIMIT		(TZRAM2_BASE + TZRAM2_SIZE)
95
96/*******************************************************************************
97 * Platform specific page table and MMU setup constants
98 ******************************************************************************/
99#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
100#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
101#define MAX_XLAT_TABLES		4
102#define MAX_MMAP_REGIONS	16
103
104/*******************************************************************************
105 * Declarations and constants to access the mailboxes safely. Each mailbox is
106 * aligned on the biggest cache line size in the platform. This is known only
107 * to the platform as it might have a combination of integrated and external
108 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
109 * line at any cache level. They could belong to different cpus/clusters &
110 * get written while being protected by different locks causing corruption of
111 * a valid mailbox address.
112 ******************************************************************************/
113#define CACHE_WRITEBACK_SHIFT	6
114#define CACHE_WRITEBACK_GRANULE	(1 << CACHE_WRITEBACK_SHIFT)
115
116
117#define PLAT_ARM_GICD_BASE      BASE_GICD_BASE
118#define PLAT_ARM_GICC_BASE      BASE_GICC_BASE
119
120#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
121	INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
122			GIC_INTR_CFG_EDGE), \
123	INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
124			GIC_INTR_CFG_EDGE), \
125	INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
126			GIC_INTR_CFG_EDGE), \
127	INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
128			GIC_INTR_CFG_EDGE), \
129	INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
130			GIC_INTR_CFG_EDGE), \
131	INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
132			GIC_INTR_CFG_EDGE), \
133	INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
134			GIC_INTR_CFG_EDGE), \
135	INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
136			GIC_INTR_CFG_EDGE)
137
138#define PLAT_ARM_G0_IRQ_PROPS(grp)
139
140#endif /* __PLATFORM_DEF_H__ */
141