1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <bl_common.h> 8#include <gicv3.h> 9#include <platform.h> 10#include <platform_def.h> 11#include <utils.h> 12 13/****************************************************************************** 14 * The following functions are defined as weak to allow a platform to override 15 * the way the GICv3 driver is initialised and used. 16 *****************************************************************************/ 17#pragma weak plat_rockchip_gic_driver_init 18#pragma weak plat_rockchip_gic_init 19#pragma weak plat_rockchip_gic_cpuif_enable 20#pragma weak plat_rockchip_gic_cpuif_disable 21#pragma weak plat_rockchip_gic_pcpu_init 22 23/* The GICv3 driver only needs to be initialized in EL3 */ 24uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 25 26/* Array of Group1 secure interrupts to be configured by the gic driver */ 27const unsigned int g1s_interrupt_array[] = { 28 PLAT_RK_G1S_IRQS 29}; 30 31/* Array of Group0 interrupts to be configured by the gic driver */ 32const unsigned int g0_interrupt_array[] = { 33 PLAT_RK_G0_IRQS 34}; 35 36static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr) 37{ 38 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 39} 40 41const gicv3_driver_data_t rockchip_gic_data = { 42 .gicd_base = PLAT_RK_GICD_BASE, 43 .gicr_base = PLAT_RK_GICR_BASE, 44 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 45 .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), 46 .g0_interrupt_array = g0_interrupt_array, 47 .g1s_interrupt_array = g1s_interrupt_array, 48 .rdistif_num = PLATFORM_CORE_COUNT, 49 .rdistif_base_addrs = rdistif_base_addrs, 50 .mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos, 51}; 52 53void plat_rockchip_gic_driver_init(void) 54{ 55 /* 56 * The GICv3 driver is initialized in EL3 and does not need 57 * to be initialized again in SEL1. This is because the S-EL1 58 * can use GIC system registers to manage interrupts and does 59 * not need GIC interface base addresses to be configured. 60 */ 61#ifdef IMAGE_BL31 62 gicv3_driver_init(&rockchip_gic_data); 63#endif 64} 65 66/****************************************************************************** 67 * RockChip common helper to initialize the GIC. Only invoked 68 * by BL31 69 *****************************************************************************/ 70void plat_rockchip_gic_init(void) 71{ 72 gicv3_distif_init(); 73 gicv3_rdistif_init(plat_my_core_pos()); 74 gicv3_cpuif_enable(plat_my_core_pos()); 75} 76 77/****************************************************************************** 78 * RockChip common helper to enable the GIC CPU interface 79 *****************************************************************************/ 80void plat_rockchip_gic_cpuif_enable(void) 81{ 82 gicv3_cpuif_enable(plat_my_core_pos()); 83} 84 85/****************************************************************************** 86 * RockChip common helper to disable the GIC CPU interface 87 *****************************************************************************/ 88void plat_rockchip_gic_cpuif_disable(void) 89{ 90 gicv3_cpuif_disable(plat_my_core_pos()); 91} 92 93/****************************************************************************** 94 * RockChip common helper to initialize the per-cpu redistributor interface 95 * in GICv3 96 *****************************************************************************/ 97void plat_rockchip_gic_pcpu_init(void) 98{ 99 gicv3_rdistif_init(plat_my_core_pos()); 100} 101