1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef __PLATFORM_DEF_H__ 8#define __PLATFORM_DEF_H__ 9 10#include <arch.h> 11#include <common_def.h> 12#include <rk3368_def.h> 13 14#define DEBUG_XLAT_TABLE 0 15 16/******************************************************************************* 17 * Platform binary types for linking 18 ******************************************************************************/ 19#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 20#define PLATFORM_LINKER_ARCH aarch64 21 22/******************************************************************************* 23 * Generic platform constants 24 ******************************************************************************/ 25 26/* Size of cacheable stacks */ 27#if DEBUG_XLAT_TABLE 28#define PLATFORM_STACK_SIZE 0x800 29#elif defined(IMAGE_BL1) 30#define PLATFORM_STACK_SIZE 0x440 31#elif defined(IMAGE_BL2) 32#define PLATFORM_STACK_SIZE 0x400 33#elif defined(IMAGE_BL31) 34#define PLATFORM_STACK_SIZE 0x800 35#elif defined(IMAGE_BL32) 36#define PLATFORM_STACK_SIZE 0x440 37#endif 38 39#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 40 41#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 42#define PLATFORM_SYSTEM_COUNT 1 43#define PLATFORM_CLUSTER_COUNT 2 44#define PLATFORM_CLUSTER0_CORE_COUNT 4 45#define PLATFORM_CLUSTER1_CORE_COUNT 4 46#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 47 PLATFORM_CLUSTER0_CORE_COUNT) 48#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 49#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 50 PLATFORM_CLUSTER_COUNT + \ 51 PLATFORM_CORE_COUNT) 52 53#define PLAT_RK_CLST_TO_CPUID_SHIFT 8 54 55#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 56 57/* 58 * This macro defines the deepest retention state possible. A higher state 59 * id will represent an invalid or a power down state. 60 */ 61#define PLAT_MAX_RET_STATE 1 62 63/* 64 * This macro defines the deepest power down states possible. Any state ID 65 * higher than this is invalid. 66 */ 67#define PLAT_MAX_OFF_STATE 2 68 69/******************************************************************************* 70 * Platform memory map related constants 71 ******************************************************************************/ 72/* TF txet, ro, rw, Size: 512KB */ 73#define TZRAM_BASE (0x0) 74#define TZRAM_SIZE (0x80000) 75 76/******************************************************************************* 77 * BL31 specific defines. 78 ******************************************************************************/ 79/* 80 * Put BL3-1 at the top of the Trusted RAM 81 */ 82#define BL31_BASE (TZRAM_BASE + 0x10000) 83#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 84 85/******************************************************************************* 86 * Platform specific page table and MMU setup constants 87 ******************************************************************************/ 88#define ADDR_SPACE_SIZE (1ull << 32) 89#define MAX_XLAT_TABLES 8 90#define MAX_MMAP_REGIONS 16 91 92/******************************************************************************* 93 * Declarations and constants to access the mailboxes safely. Each mailbox is 94 * aligned on the biggest cache line size in the platform. This is known only 95 * to the platform as it might have a combination of integrated and external 96 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 97 * line at any cache level. They could belong to different cpus/clusters & 98 * get written while being protected by different locks causing corruption of 99 * a valid mailbox address. 100 ******************************************************************************/ 101#define CACHE_WRITEBACK_SHIFT 6 102#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 103 104/* 105 * Define GICD and GICC and GICR base 106 */ 107#define PLAT_RK_GICD_BASE RK3368_GICD_BASE 108#define PLAT_RK_GICC_BASE RK3368_GICC_BASE 109 110/* 111 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 112 * terminology. On a GICv2 system or mode, the lists will be merged and treated 113 * as Group 0 interrupts. 114 */ 115#define PLAT_RK_G1S_IRQS RK_G1S_IRQS 116 117#define PLAT_RK_UART_BASE RK3368_UART2_BASE 118#define PLAT_RK_UART_CLOCK RK3368_UART_CLOCK 119#define PLAT_RK_UART_BAUDRATE RK3368_BAUDRATE 120 121#define PLAT_RK_CCI_BASE CCI400_BASE 122 123#define PLAT_RK_PRIMARY_CPU 0x0 124 125#define PSRAM_DO_DDR_RESUME 0 126#define PSRAM_CHECK_WAKEUP_CPU 0 127 128#endif /* __PLATFORM_DEF_H__ */ 129