1/** @file
2  Header files and data structures needed by PCI Bus module.
3
4Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
5This program and the accompanying materials
6are licensed and made available under the terms and conditions of the BSD License
7which accompanies this distribution.  The full text of the license may be found at
8http://opensource.org/licenses/bsd-license.php
9
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15
16#ifndef _EFI_PCI_BUS_H_
17#define _EFI_PCI_BUS_H_
18
19#include <PiDxe.h>
20
21#include <Protocol/LoadedImage.h>
22#include <Protocol/PciHostBridgeResourceAllocation.h>
23#include <Protocol/PciIo.h>
24#include <Protocol/LoadFile2.h>
25#include <Protocol/PciRootBridgeIo.h>
26#include <Protocol/PciHotPlugRequest.h>
27#include <Protocol/DevicePath.h>
28#include <Protocol/PciPlatform.h>
29#include <Protocol/PciHotPlugInit.h>
30#include <Protocol/Decompress.h>
31#include <Protocol/BusSpecificDriverOverride.h>
32#include <Protocol/IncompatiblePciDeviceSupport.h>
33#include <Protocol/PciOverride.h>
34#include <Protocol/PciEnumerationComplete.h>
35
36#include <Library/DebugLib.h>
37#include <Library/UefiDriverEntryPoint.h>
38#include <Library/BaseLib.h>
39#include <Library/UefiLib.h>
40#include <Library/BaseMemoryLib.h>
41#include <Library/ReportStatusCodeLib.h>
42#include <Library/MemoryAllocationLib.h>
43#include <Library/UefiBootServicesTableLib.h>
44#include <Library/DevicePathLib.h>
45#include <Library/PcdLib.h>
46#include <Library/PeCoffLib.h>
47
48#include <IndustryStandard/Pci.h>
49#include <IndustryStandard/PeImage.h>
50#include <IndustryStandard/Acpi.h>
51
52typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
53typedef struct _PCI_BAR                    PCI_BAR;
54
55#define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
56#define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
57
58#define     EFI_PCI_IOV_POLICY_ARI           0x0001
59#define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
60#define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
61
62typedef enum {
63  PciBarTypeUnknown = 0,
64  PciBarTypeIo16,
65  PciBarTypeIo32,
66  PciBarTypeMem32,
67  PciBarTypePMem32,
68  PciBarTypeMem64,
69  PciBarTypePMem64,
70  PciBarTypeIo,
71  PciBarTypeMem,
72  PciBarTypeMaxType
73} PCI_BAR_TYPE;
74
75#include "ComponentName.h"
76#include "PciIo.h"
77#include "PciCommand.h"
78#include "PciDeviceSupport.h"
79#include "PciEnumerator.h"
80#include "PciEnumeratorSupport.h"
81#include "PciDriverOverride.h"
82#include "PciRomTable.h"
83#include "PciOptionRomSupport.h"
84#include "PciPowerManagement.h"
85#include "PciHotPlugSupport.h"
86#include "PciLib.h"
87
88#define VGABASE1  0x3B0
89#define VGALIMIT1 0x3BB
90
91#define VGABASE2  0x3C0
92#define VGALIMIT2 0x3DF
93
94#define ISABASE   0x100
95#define ISALIMIT  0x3FF
96
97//
98// PCI BAR parameters
99//
100struct _PCI_BAR {
101  UINT64        BaseAddress;
102  UINT64        Length;
103  UINT64        Alignment;
104  PCI_BAR_TYPE  BarType;
105  BOOLEAN       BarTypeFixed;
106  UINT16        Offset;
107};
108
109//
110// defined in PCI Card Specification, 8.0
111//
112#define PCI_CARD_MEMORY_BASE_0                0x1C
113#define PCI_CARD_MEMORY_LIMIT_0               0x20
114#define PCI_CARD_MEMORY_BASE_1                0x24
115#define PCI_CARD_MEMORY_LIMIT_1               0x28
116#define PCI_CARD_IO_BASE_0_LOWER              0x2C
117#define PCI_CARD_IO_BASE_0_UPPER              0x2E
118#define PCI_CARD_IO_LIMIT_0_LOWER             0x30
119#define PCI_CARD_IO_LIMIT_0_UPPER             0x32
120#define PCI_CARD_IO_BASE_1_LOWER              0x34
121#define PCI_CARD_IO_BASE_1_UPPER              0x36
122#define PCI_CARD_IO_LIMIT_1_LOWER             0x38
123#define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
124#define PCI_CARD_BRIDGE_CONTROL               0x3E
125
126#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
127#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
128
129#define RB_IO_RANGE                           1
130#define RB_MEM32_RANGE                        2
131#define RB_PMEM32_RANGE                       3
132#define RB_MEM64_RANGE                        4
133#define RB_PMEM64_RANGE                       5
134
135#define PPB_BAR_0                             0
136#define PPB_BAR_1                             1
137#define PPB_IO_RANGE                          2
138#define PPB_MEM32_RANGE                       3
139#define PPB_PMEM32_RANGE                      4
140#define PPB_PMEM64_RANGE                      5
141#define PPB_MEM64_RANGE                       0xFF
142
143#define P2C_BAR_0                             0
144#define P2C_MEM_1                             1
145#define P2C_MEM_2                             2
146#define P2C_IO_1                              3
147#define P2C_IO_2                              4
148
149#define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
150#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
151#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
152#define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
153#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
154#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
155#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
156
157#define PCI_MAX_HOST_BRIDGE_NUM               0x0010
158
159//
160// Define option for attribute
161//
162#define EFI_SET_SUPPORTS    0
163#define EFI_SET_ATTRIBUTES  1
164
165#define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
166
167struct _PCI_IO_DEVICE {
168  UINT32                                    Signature;
169  EFI_HANDLE                                Handle;
170  EFI_PCI_IO_PROTOCOL                       PciIo;
171  LIST_ENTRY                                Link;
172
173  EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
174  EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
175  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
176  EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
177
178  //
179  // PCI configuration space header type
180  //
181  PCI_TYPE00                                Pci;
182
183  //
184  // Bus number, Device number, Function number
185  //
186  UINT8                                     BusNumber;
187  UINT8                                     DeviceNumber;
188  UINT8                                     FunctionNumber;
189
190  //
191  // BAR for this PCI Device
192  //
193  PCI_BAR                                   PciBar[PCI_MAX_BAR];
194
195  //
196  // The bridge device this pci device is subject to
197  //
198  PCI_IO_DEVICE                             *Parent;
199
200  //
201  // A linked list for children Pci Device if it is bridge device
202  //
203  LIST_ENTRY                                ChildList;
204
205  //
206  // TRUE if the PCI bus driver creates the handle for this PCI device
207  //
208  BOOLEAN                                   Registered;
209
210  //
211  // TRUE if the PCI bus driver successfully allocates the resource required by
212  // this PCI device
213  //
214  BOOLEAN                                   Allocated;
215
216  //
217  // The attribute this PCI device currently set
218  //
219  UINT64                                    Attributes;
220
221  //
222  // The attributes this PCI device actually supports
223  //
224  UINT64                                    Supports;
225
226  //
227  // The resource decode the bridge supports
228  //
229  UINT32                                    Decodes;
230
231  //
232  // TRUE if the ROM image is from the PCI Option ROM BAR
233  //
234  BOOLEAN                                   EmbeddedRom;
235
236  //
237  // The OptionRom Size
238  //
239  UINT64                                    RomSize;
240
241  //
242  // The OptionRom Size
243  //
244  UINT64                                    RomBase;
245
246  //
247  // TRUE if all OpROM (in device or in platform specific position) have been processed
248  //
249  BOOLEAN                                   AllOpRomProcessed;
250
251  //
252  // TRUE if there is any EFI driver in the OptionRom
253  //
254  BOOLEAN                                   BusOverride;
255
256  //
257  // A list tracking reserved resource on a bridge device
258  //
259  LIST_ENTRY                                ReservedResourceList;
260
261  //
262  // A list tracking image handle of platform specific overriding driver
263  //
264  LIST_ENTRY                                OptionRomDriverList;
265
266  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
267  EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
268
269  //
270  // Bus number ranges for a PCI Root Bridge device
271  //
272  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;
273
274  BOOLEAN                                   IsPciExp;
275  //
276  // For SR-IOV
277  //
278  UINT8                                     PciExpressCapabilityOffset;
279  UINT32                                    AriCapabilityOffset;
280  UINT32                                    SrIovCapabilityOffset;
281  UINT32                                    MrIovCapabilityOffset;
282  PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
283  UINT32                                    SystemPageSize;
284  UINT16                                    InitialVFs;
285  UINT16                                    ReservedBusNum;
286  //
287  // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
288  // but some chipsets support non-standard I/O window alignments less than 4K.
289  // This field is used to support this case.
290  //
291  UINT16                                    BridgeIoAlignment;
292};
293
294#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
295  CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
296
297#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
298  CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
299
300#define PCI_IO_DEVICE_FROM_LINK(a) \
301  CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
302
303#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
304  CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
305
306
307
308//
309// Global Variables
310//
311extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
312extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
313extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
314extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
315extern BOOLEAN                                      gFullEnumeration;
316extern UINTN                                        gPciHostBridgeNumber;
317extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
318extern UINT64                                       gAllOne;
319extern UINT64                                       gAllZero;
320extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
321extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
322extern BOOLEAN                                      mReserveIsaAliases;
323extern BOOLEAN                                      mReserveVgaAliases;
324
325/**
326  Macro that checks whether device is a GFX device.
327
328  @param  _p      Specified device.
329
330  @retval TRUE    Device is a GFX device.
331  @retval FALSE   Device is not a GFX device.
332
333**/
334#define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
335
336/**
337  Test to see if this driver supports ControllerHandle. Any ControllerHandle
338  than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
339
340  @param  This                Protocol instance pointer.
341  @param  Controller          Handle of device to test.
342  @param  RemainingDevicePath Optional parameter use to pick a specific child
343                              device to start.
344
345  @retval EFI_SUCCESS         This driver supports this device.
346  @retval EFI_ALREADY_STARTED This driver is already running on this device.
347  @retval other               This driver does not support this device.
348
349**/
350EFI_STATUS
351EFIAPI
352PciBusDriverBindingSupported (
353  IN EFI_DRIVER_BINDING_PROTOCOL    *This,
354  IN EFI_HANDLE                     Controller,
355  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
356  );
357
358/**
359  Start this driver on ControllerHandle and enumerate Pci bus and start
360  all device under PCI bus.
361
362  @param  This                 Protocol instance pointer.
363  @param  Controller           Handle of device to bind driver to.
364  @param  RemainingDevicePath  Optional parameter use to pick a specific child
365                               device to start.
366
367  @retval EFI_SUCCESS          This driver is added to ControllerHandle.
368  @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
369  @retval other                This driver does not support this device.
370
371**/
372EFI_STATUS
373EFIAPI
374PciBusDriverBindingStart (
375  IN EFI_DRIVER_BINDING_PROTOCOL    *This,
376  IN EFI_HANDLE                     Controller,
377  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
378  );
379
380/**
381  Stop this driver on ControllerHandle. Support stopping any child handles
382  created by this driver.
383
384  @param  This              Protocol instance pointer.
385  @param  Controller        Handle of device to stop driver on.
386  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
387                            children is zero stop the entire bus driver.
388  @param  ChildHandleBuffer List of Child Handles to Stop.
389
390  @retval EFI_SUCCESS       This driver is removed ControllerHandle.
391  @retval other             This driver was not removed from this device.
392
393**/
394EFI_STATUS
395EFIAPI
396PciBusDriverBindingStop (
397  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
398  IN  EFI_HANDLE                    Controller,
399  IN  UINTN                         NumberOfChildren,
400  IN  EFI_HANDLE                    *ChildHandleBuffer
401  );
402
403#endif
404