1/** @file 2 Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual. 3 4 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13**/ 14 15#ifndef __PAL_API_H__ 16#define __PAL_API_H__ 17 18#define PAL_SUCCESS 0x0 19 20/// 21/// CacheType of PAL_CACHE_FLUSH. 22/// 23#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1 24#define PAL_CACHE_FLUSH_DATA_ALL 2 25#define PAL_CACHE_FLUSH_ALL 3 26#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4 27 28 29/// 30/// Bitmask of Opearation of PAL_CACHE_FLUSH. 31/// 32#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0 33#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0 34#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1 35#define PAL_CACHE_FLUSH_NO_INTERRUPT 0 36 37/** 38 PAL Procedure - PAL_CACHE_FLUSH. 39 40 Flush the instruction or data caches. It is required by Itanium processors. 41 The PAL procedure supports the Static Registers calling 42 convention. It could be called at virtual mode and physical 43 mode. 44 45 @param Index Index of PAL_CACHE_FLUSH within the 46 list of PAL procedures. 47 @param CacheType Unsigned 64-bit integer indicating 48 which cache to flush. 49 @param Operation Formatted bit vector indicating the 50 operation of this call. 51 @param ProgressIndicator Unsigned 64-bit integer specifying 52 the starting position of the flush 53 operation. 54 55 @retval 2 Call completed without error, but a PMI 56 was taken during the execution of this 57 procedure. 58 @retval 1 Call has not completed flushing due to 59 a pending interrupt. 60 @retval 0 Call completed without error 61 @retval -2 Invalid argument 62 @retval -3 Call completed with error 63 64 @return R9 Unsigned 64-bit integer specifying the vector 65 number of the pending interrupt. 66 @return R10 Unsigned 64-bit integer specifying the 67 starting position of the flush operation. 68 @return R11 Unsigned 64-bit integer specifying the vector 69 number of the pending interrupt. 70 71**/ 72#define PAL_CACHE_FLUSH 1 73 74 75/// 76/// Attributes of PAL_CACHE_CONFIG_INFO1 77/// 78#define PAL_CACHE_ATTR_WT 0 79#define PAL_CACHE_ATTR_WB 1 80 81/// 82/// PAL_CACHE_CONFIG_INFO1.StoreHint 83/// 84#define PAL_CACHE_STORE_TEMPORAL 0 85#define PAL_CACHE_STORE_NONE_TEMPORAL 3 86 87/// 88/// PAL_CACHE_CONFIG_INFO1.StoreHint 89/// 90#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0 91#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3 92 93/// 94/// PAL_CACHE_CONFIG_INFO1.StoreHint 95/// 96#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0 97#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1 98#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3 99 100/// 101/// Detail the characteristics of a given processor controlled 102/// cache in the cache hierarchy. 103/// 104typedef struct { 105 UINT64 IsUnified : 1; 106 UINT64 Attributes : 2; 107 UINT64 Associativity:8; 108 UINT64 LineSize:8; 109 UINT64 Stride:8; 110 UINT64 StoreLatency:8; 111 UINT64 StoreHint:8; 112 UINT64 LoadHint:8; 113} PAL_CACHE_INFO_RETURN1; 114 115/// 116/// Detail the characteristics of a given processor controlled 117/// cache in the cache hierarchy. 118/// 119typedef struct { 120 UINT64 CacheSize:32; 121 UINT64 AliasBoundary:8; 122 UINT64 TagLsBits:8; 123 UINT64 TagMsBits:8; 124} PAL_CACHE_INFO_RETURN2; 125 126/** 127 PAL Procedure - PAL_CACHE_INFO. 128 129 Return detailed instruction or data cache information. It is 130 required by Itanium processors. The PAL procedure supports the Static 131 Registers calling convention. It could be called at virtual 132 mode and physical mode. 133 134 @param Index Index of PAL_CACHE_INFO within the list of 135 PAL procedures. 136 @param CacheLevel Unsigned 64-bit integer specifying the 137 level in the cache hierarchy for which 138 information is requested. This value must 139 be between 0 and one less than the value 140 returned in the cache_levels return value 141 from PAL_CACHE_SUMMARY. 142 @param CacheType Unsigned 64-bit integer with a value of 1 143 for instruction cache and 2 for data or 144 unified cache. All other values are 145 reserved. 146 @param Reserved Should be 0. 147 148 @retval 0 Call completed without error 149 @retval -2 Invalid argument 150 @retval -3 Call completed with error 151 152 @return R9 Detail the characteristics of a given 153 processor controlled cache in the cache 154 hierarchy. See PAL_CACHE_INFO_RETURN1. 155 @return R10 Detail the characteristics of a given 156 processor controlled cache in the cache 157 hierarchy. See PAL_CACHE_INFO_RETURN2. 158 @return R11 Reserved with 0. 159 160**/ 161#define PAL_CACHE_INFO 2 162 163 164 165/// 166/// Level of PAL_CACHE_INIT. 167/// 168#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL 169 170/// 171/// CacheType 172/// 173#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1 174#define PAL_CACHE_INIT_TYPE_DATA 0x2 175#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3 176 177/// 178/// Restrict of PAL_CACHE_INIT. 179/// 180#define PAL_CACHE_INIT_NO_RESTRICT 0 181#define PAL_CACHE_INIT_RESTRICTED 1 182 183/** 184 PAL Procedure - PAL_CACHE_INIT. 185 186 Initialize the instruction or data caches. It is required by 187 Itanium processors. The PAL procedure supports the Static Registers calling 188 convention. It could be called at physical mode. 189 190 @param Index Index of PAL_CACHE_INIT within the list of PAL 191 procedures. 192 @param Level Unsigned 64-bit integer containing the level of 193 cache to initialize. If the cache level can be 194 initialized independently, only that level will 195 be initialized. Otherwise 196 implementation-dependent side-effects will 197 occur. 198 @param CacheType Unsigned 64-bit integer with a value of 1 to 199 initialize the instruction cache, 2 to 200 initialize the data cache, or 3 to 201 initialize both. All other values are 202 reserved. 203 @param Restrict Unsigned 64-bit integer with a value of 0 or 204 1. All other values are reserved. If 205 restrict is 1 and initializing the specified 206 level and cache_type of the cache would 207 cause side-effects, PAL_CACHE_INIT will 208 return -4 instead of initializing the cache. 209 210 @retval 0 Call completed without error 211 @retval -2 Invalid argument 212 @retval -3 Call completed with error. 213 @retval -4 Call could not initialize the specified 214 level and cache_type of the cache without 215 side-effects and restrict was 1. 216 217**/ 218#define PAL_CACHE_INIT 3 219 220 221/// 222/// PAL_CACHE_PROTECTION.Method. 223/// 224#define PAL_CACHE_PROTECTION_NONE_PROTECT 0 225#define PAL_CACHE_PROTECTION_ODD_PROTECT 1 226#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2 227#define PAL_CACHE_PROTECTION_ECC_PROTECT 3 228 229 230 231/// 232/// PAL_CACHE_PROTECTION.TagOrData. 233/// 234#define PAL_CACHE_PROTECTION_PROTECT_DATA 0 235#define PAL_CACHE_PROTECTION_PROTECT_TAG 1 236#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2 237#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3 238 239/// 240/// 32-bit protection information structures. 241/// 242typedef struct { 243 UINT32 DataBits:8; 244 UINT32 TagProtLsb:6; 245 UINT32 TagProtMsb:6; 246 UINT32 ProtBits:6; 247 UINT32 Method:4; 248 UINT32 TagOrData:2; 249} PAL_CACHE_PROTECTION; 250 251/** 252 PAL Procedure - PAL_CACHE_PROT_INFO. 253 254 Return instruction or data cache protection information. It is 255 required by Itanium processors. The PAL procedure supports the Static 256 Registers calling convention. It could be called at physical 257 mode and Virtual mode. 258 259 @param Index Index of PAL_CACHE_PROT_INFO within the list of 260 PAL procedures. 261 @param CacheLevel Unsigned 64-bit integer specifying the level 262 in the cache hierarchy for which information 263 is requested. This value must be between 0 264 and one less than the value returned in the 265 cache_levels return value from 266 PAL_CACHE_SUMMARY. 267 @param CacheType Unsigned 64-bit integer with a value of 1 268 for instruction cache and 2 for data or 269 unified cache. All other values are 270 reserved. 271 272 @retval 0 Call completed without error 273 @retval -2 Invalid argument 274 @retval -3 Call completed with error. 275 276 @return R9 Detail the characteristics of a given 277 processor controlled cache in the cache 278 hierarchy. See PAL_CACHE_PROTECTION[0..1]. 279 @return R10 Detail the characteristics of a given 280 processor controlled cache in the cache 281 hierarchy. See PAL_CACHE_PROTECTION[2..3]. 282 @return R11 Detail the characteristics of a given 283 processor controlled cache in the cache 284 hierarchy. See PAL_CACHE_PROTECTION[4..5]. 285 286**/ 287#define PAL_CACHE_PROT_INFO 38 288 289typedef struct { 290 UINT64 ThreadId : 16; ///< The thread identifier of the logical 291 ///< processor for which information is being 292 ///< returned. This value will be unique on a per core basis. 293 UINT64 Reserved1: 16; 294 UINT64 CoreId: 16; ///< The core identifier of the logical processor 295 ///< for which information is being returned. 296 ///< This value will be unique on a per physical 297 ///< processor package basis. 298 UINT64 Reserved2: 16; 299} PAL_PCOC_N_CACHE_INFO1; 300 301 302typedef struct { 303 UINT64 LogicalAddress : 16; ///< Logical address: geographical address 304 ///< of the logical processor for which 305 ///< information is being returned. This is 306 ///< the same value that is returned by the 307 ///< PAL_FIXED_ADDR procedure when it is 308 ///< called on the logical processor. 309 UINT64 Reserved1: 16; 310 UINT64 Reserved2: 32; 311} PAL_PCOC_N_CACHE_INFO2; 312 313/** 314 PAL Procedure - PAL_CACHE_SHARED_INFO. 315 316 Returns information on which logical processors share caches. 317 It is optional. The PAL procedure supports the Static 318 Registers calling convention. It could be called at physical 319 mode and Virtual mode. 320 321 @param Index Index of PAL_CACHE_SHARED_INFO within the list 322 of PAL procedures. 323 @param CacheLevel Unsigned 64-bit integer specifying the 324 level in the cache hierarchy for which 325 information is requested. This value must 326 be between 0 and one less than the value 327 returned in the cache_levels return value 328 from PAL_CACHE_SUMMARY. 329 @param CacheType Unsigned 64-bit integer with a value of 1 330 for instruction cache and 2 for data or 331 unified cache. All other values are 332 reserved. 333 @param ProcNumber Unsigned 64-bit integer that specifies for 334 which logical processor information is 335 being requested. This input argument must 336 be zero for the first call to this 337 procedure and can be a maximum value of 338 one less than the number of logical 339 processors sharing this cache, which is 340 returned by the num_shared return value. 341 342 @retval 0 Call completed without error 343 @retval -1 Unimplemented procedure 344 @retval -2 Invalid argument 345 @retval -3 Call completed with error. 346 347 @return R9 Unsigned integer that returns the number of 348 logical processors that share the processor 349 cache level and type, for which information was 350 requested. 351 @return R10 The format of PAL_PCOC_N_CACHE_INFO1. 352 @return R11 The format of PAL_PCOC_N_CACHE_INFO2. 353 354**/ 355#define PAL_CACHE_SHARED_INFO 43 356 357 358/** 359 PAL Procedure - PAL_CACHE_SUMMARY. 360 361 Return a summary of the cache hierarchy. It is required by 362 Itanium processors. The PAL procedure supports the Static Registers calling 363 convention. It could be called at physical mode and Virtual 364 mode. 365 366 @param Index Index of PAL_CACHE_SUMMARY within the list of 367 PAL procedures. 368 369 @retval 0 Call completed without error 370 @retval -2 Invalid argument 371 @retval -3 Call completed with error. 372 373 @return R9 CacheLevels Unsigned 64-bit integer denoting the 374 number of levels of cache 375 implemented by the processor. 376 Strictly, this is the number of 377 levels for which the cache 378 controller is integrated into the 379 processor (the cache SRAMs may be 380 external to the processor). 381 @return R10 UniqueCaches Unsigned 64-bit integer denoting the 382 number of unique caches implemented 383 by the processor. This has a maximum 384 of 2*cache_levels, but may be less 385 if any of the levels in the cache 386 hierarchy are unified caches or do 387 not have both instruction and data 388 caches. 389 390**/ 391#define PAL_CACHE_SUMMARY 4 392 393 394// 395// Virtual Memory Attributes implemented by processor. 396// 397#define PAL_MEMORY_ATTR_WB 0 398#define PAL_MEMORY_ATTR_WC 6 399#define PAL_MEMORY_ATTR_UC 4 400#define PAL_MEMORY_ATTR_UCE 5 401#define PAL_MEMORY_ATTR_NATPAGE 7 402 403/** 404 PAL Procedure - PAL_MEM_ATTRIB. 405 406 Return a list of supported memory attributes.. It is required 407 by Itanium processors. The PAL procedure supports the Static Registers calling 408 convention. It could be called at physical mode and Virtual 409 mode. 410 411 @param Index Index of PAL_MEM_ATTRIB within the list of PAL 412 procedures. 413 414 @retval 0 Call completed without error 415 @retval -2 Invalid argument 416 @retval -3 Call completed with error. 417 418 @return R9 Attributes 8-bit vector of memory attributes 419 implemented by processor. See Virtual 420 Memory Attributes above. 421 422**/ 423 424#define PAL_MEM_ATTRIB 5 425 426/** 427 PAL Procedure - PAL_PREFETCH_VISIBILITY. 428 429 Used in architected sequence to transition pages from a 430 cacheable, speculative attribute to an uncacheable attribute. 431 It is required by Itanium processors. The PAL procedure supports the Static 432 Registers calling convention. It could be called at physical 433 mode and Virtual mode. 434 435 @param Index Index of PAL_PREFETCH_VISIBILITY within the list 436 of PAL procedures. 437 @param TransitionType Unsigned integer specifying the type 438 of memory attribute transition that is 439 being performed. 440 441 @retval 1 Call completed without error; this 442 call is not necessary on remote 443 processors. 444 @retval 0 Call completed without error 445 @retval -2 Invalid argument 446 @retval -3 Call completed with error. 447 448**/ 449#define PAL_PREFETCH_VISIBILITY 41 450 451/** 452 PAL Procedure - PAL_PTCE_INFO. 453 454 Return information needed for ptc.e instruction to purge 455 entire TC. It is required by Itanium processors. The PAL procedure supports 456 the Static Registers calling convention. It could be called at 457 physical mode and Virtual mode. 458 459 @param Index Index of PAL_PTCE_INFO within the list 460 of PAL procedures. 461 462 @retval 0 Call completed without error 463 @retval -2 Invalid argument 464 @retval -3 Call completed with error. 465 466 @return R9 Unsigned 64-bit integer denoting the beginning 467 address to be used by the first PTCE instruction 468 in the purge loop. 469 @return R10 Two unsigned 32-bit integers denoting the loop 470 counts of the outer (loop 1) and inner (loop 2) 471 purge loops. count1 (loop 1) is contained in bits 472 63:32 of the parameter, and count2 (loop 2) is 473 contained in bits 31:0 of the parameter. 474 @return R11 Two unsigned 32-bit integers denoting the loop 475 strides of the outer (loop 1) and inner (loop 2) 476 purge loops. stride1 (loop 1) is contained in bits 477 63:32 of the parameter, and stride2 (loop 2) is 478 contained in bits 31:0 of the parameter. 479 480**/ 481#define PAL_PTCE_INFO 6 482 483typedef struct { 484 UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting the number 485 ///< of hash sets for the specified level 486 ///< (1=fully associative) 487 UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting the 488 ///< associativity of the specified level 489 ///< (1=direct). 490 UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting the 491 ///< number of entries in the specified TC. 492 UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the 493 ///< specified level is optimized for 494 ///< the region's preferred page size 495 ///< (1=optimized) tc_pages indicates 496 ///< which page sizes are usable by 497 ///< this translation cache. 498 UINT64 TcIsUnified:1; ///< Flag denoting whether the specified TC is 499 ///< unified (1=unified). 500 UINT64 EntriesReduction:1; ///< Flag denoting whether installed 501 ///< translation registers will reduce 502 ///< the number of entries within the 503 ///< specified TC. 504} PAL_TC_INFO; 505 506/** 507 PAL Procedure - PAL_VM_INFO. 508 509 Return detailed information about virtual memory features 510 supported in the processor. It is required by Itanium processors. The PAL 511 procedure supports the Static Registers calling convention. It 512 could be called at physical mode and Virtual mode. 513 514 @param Index Index of PAL_VM_INFO within the list 515 of PAL procedures. 516 @param TcLevel Unsigned 64-bit integer specifying the level 517 in the TLB hierarchy for which information is 518 required. This value must be between 0 and one 519 less than the value returned in the 520 vm_info_1.num_tc_levels return value from 521 PAL_VM_SUMMARY. 522 @param TcType Unsigned 64-bit integer with a value of 1 for 523 instruction translation cache and 2 for data 524 or unified translation cache. All other values 525 are reserved. 526 527 @retval 0 Call completed without error 528 @retval -2 Invalid argument 529 @retval -3 Call completed with error. 530 531 @return R9 8-byte formatted value returning information 532 about the specified TC. See PAL_TC_INFO above. 533 @return R10 64-bit vector containing a bit for each page 534 size supported in the specified TC, where bit 535 position n indicates a page size of 2**n. 536 537**/ 538#define PAL_VM_INFO 7 539 540 541/** 542 PAL Procedure - PAL_VM_PAGE_SIZE. 543 544 Return virtual memory TC and hardware walker page sizes 545 supported in the processor. It is required by Itanium processors. The PAL 546 procedure supports the Static Registers calling convention. It 547 could be called at physical mode and Virtual mode. 548 549 @param Index Index of PAL_VM_PAGE_SIZE within the list 550 of PAL procedures. 551 552 @retval 0 Call completed without error 553 @retval -2 Invalid argument 554 @retval -3 Call completed with error. 555 556 @return R9 64-bit vector containing a bit for each 557 architected page size that is supported for 558 TLB insertions and region registers. 559 @return R10 64-bit vector containing a bit for each 560 architected page size supported for TLB purge 561 operations. 562 563**/ 564#define PAL_VM_PAGE_SIZE 34 565 566typedef struct { 567 UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether a hardware 568 ///< TLB walker is implemented (1 = walker 569 ///< present). 570 UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer 571 ///< denoting the number of bits of 572 ///< physical address implemented. 573 UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoting the number 574 ///< of bits mplemented in the PKR.key field. 575 UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoting the 576 ///< maximum PKR index (number of PKRs-1). 577 UINT64 HashTagId:8; ///< Unsigned 8-bit integer which uniquely 578 ///< identifies the processor hash and tag 579 ///< algorithm. 580 UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoting the 581 ///< maximum data translation register index 582 ///< (number of dtr entries - 1). 583 UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoting the 584 ///< maximum instruction translation register 585 ///< index (number of itr entries - 1). 586 UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoting the 587 ///< number of unique TCs implemented. 588 ///< This is a maximum of 589 ///< 2*num_tc_levels. 590 UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoting the 591 ///< number of TC levels. 592} PAL_VM_INFO1; 593 594typedef struct { 595 UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting 596 ///< is the total number of virtual 597 ///< address bits - 1. 598 UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting the number 599 ///< of bits implemented in the RR.rid field. 600 UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting the 601 ///< maximum number of concurrent outstanding 602 ///< TLB purges allowed by the processor. A 603 ///< value of 0 indicates one outstanding 604 ///< purge allowed. A value of 216-1 605 ///< indicates no limit on outstanding 606 ///< purges. All other values indicate the 607 ///< actual number of concurrent outstanding 608 ///< purges allowed. 609 UINT64 Reserved:32; 610} PAL_VM_INFO2; 611 612/** 613 PAL Procedure - PAL_VM_SUMMARY. 614 615 Return summary information about virtual memory features 616 supported in the processor. It is required by Itanium processors. The PAL 617 procedure supports the Static Registers calling convention. It 618 could be called at physical mode and Virtual mode. 619 620 @param Index Index of PAL_VM_SUMMARY within the list 621 of PAL procedures. 622 623 @retval 0 Call completed without error 624 @retval -2 Invalid argument 625 @retval -3 Call completed with error. 626 627 @return R9 8-byte formatted value returning global virtual 628 memory information. See PAL_VM_INFO1 above. 629 @return R10 8-byte formatted value returning global virtual 630 memory information. See PAL_VM_INFO2 above. 631 632**/ 633#define PAL_VM_SUMMARY 8 634 635 636// 637// Bit mask of TR_valid flag. 638// 639#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0 640#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1 641#define PAL_TR_DIRTY_IS_VALID BIT2 642#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3 643 644 645/** 646 PAL Procedure - PAL_VM_TR_READ. 647 648 Read contents of a translation register. It is required by 649 Itanium processors. The PAL procedure supports the Stacked Register calling 650 convention. It could be called at physical mode. 651 652 @param Index Index of PAL_VM_TR_READ within the list 653 of PAL procedures. 654 @param RegNumber Unsigned 64-bit number denoting which TR to 655 read. 656 @param TrType Unsigned 64-bit number denoting whether to 657 read an ITR (0) or DTR (1). All other values 658 are reserved. 659 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in 660 which translation data is returned. 661 662 @retval 0 Call completed without error 663 @retval -2 Invalid argument 664 @retval -3 Call completed with error. 665 666 @return R9 Formatted bit vector denoting which fields are 667 valid. See TR_valid above. 668 669**/ 670#define PAL_VM_TR_READ 261 671 672 673 674 675// 676// Bit Mask of Processor Bus Fesatures . 677// 678 679/** 680 681 When 0, bus data errors are detected and single bit errors are 682 corrected. When 1, no error detection or correction is done. 683 684**/ 685#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63 686 687 688/** 689 690 When 0, bus address errors are signalled on the bus. When 1, 691 no bus errors are signalled on the bus. If Disable Bus Address 692 Error Checking is 1, this bit is ignored. 693 694**/ 695#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62 696 697 698 699 700/** 701 702 When 0, bus errors are detected, single bit errors are 703 corrected., and a CMCI or MCA is generated internally to the 704 processor. When 1, no bus address errors are detected or 705 corrected. 706 707**/ 708#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61 709 710 711/** 712 713 When 0, bus protocol errors (BINIT#) are signaled by the 714 processor on the bus. When 1, bus protocol errors (BINIT#) are 715 not signaled on the bus. If Disable Bus Initialization Event 716 Checking is 1, this bit is ignored. 717 718**/ 719#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60 720 721 722/** 723 724 When 0, bus protocol errors (BINIT#) are detected and sampled 725 and an MCA is generated internally to the processor. When 1, 726 the processor will ignore bus protocol error conditions 727 (BINIT#). 728 729**/ 730#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59 731 732 733 734/** 735 736 When 0, BERR# is signalled if a bus error is detected. When 1, 737 bus errors are not signalled on the bus. 738 739**/ 740#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58 741 742 743 744 745/** 746 747 When 0, BERR# is signalled when internal processor requestor 748 initiated bus errors are detected. When 1, internal requester 749 bus errors are not signalled on the bus. 750 751**/ 752#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57 753 754 755/** 756 757 When 0, the processor takes an MCA if BERR# is asserted. When 758 1, the processor ignores the BERR# signal. 759 760**/ 761#define PAL_BUS_DISABLE_ERROR_CHECK BIT56 762 763 764/** 765 766 When 0, the processor asserts BINIT# if it detects a parity 767 error on the signals which identify the transactions to which 768 this is a response. When 1, the processor ignores parity on 769 these signals. 770 771**/ 772#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55 773 774 775/** 776 777 When 0, the in-order transaction queue is limited only by the 778 number of hardware entries. When 1, the processor's in-order 779 transactions queue is limited to one entry. 780 781**/ 782#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54 783 784/** 785 786 Enable a bus cache line replacement transaction when a cache 787 line in the exclusive state is replaced from the highest level 788 processor cache and is not present in the lower level processor 789 caches. When 0, no bus cache line replacement transaction will 790 be seen on the bus. When 1, bus cache line replacement 791 transactions will be seen on the bus when the above condition is 792 detected. 793 794**/ 795#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53 796 797 798/** 799 800 Enable a bus cache line replacement transaction when a cache 801 line in the shared or exclusive state is replaced from the 802 highest level processor cache and is not present in the lower 803 level processor caches. 804 When 0, no bus cache line replacement transaction will be seen 805 on the bus. When 1, bus cache line replacement transactions 806 will be seen on the bus when the above condition is detected. 807 808**/ 809#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52 810 811 812 813/** 814 815 When 0, the data bus is configured at the 2x data transfer 816 rate.When 1, the data bus is configured at the 1x data 817 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the 818 processor executes locked transactions atomically. When 1, the 819 processor masks the bus lock signal and executes locked 820 transactions as a non-atomic series of transactions. 821 822**/ 823#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30 824 825/** 826 827 When 0, the processor will deassert bus request when finished 828 with each transaction. When 1, the processor will continue to 829 assert bus request after it has finished, if it was the last 830 agent to own the bus and if there are no other pending 831 requests. 832 833**/ 834#define PAL_BUS_REQUEST_BUS_PARKING BIT29 835 836 837/** 838 PAL Procedure - PAL_BUS_GET_FEATURES. 839 840 Return configurable processor bus interface features and their 841 current settings. It is required by Itanium processors. The PAL procedure 842 supports the Stacked Register calling convention. It could be 843 called at physical mode. 844 845 @param Index Index of PAL_BUS_GET_FEATURES within the list 846 of PAL procedures. 847 848 @retval 0 Call completed without error 849 @retval -2 Invalid argument 850 @retval -3 Call completed with error. 851 852 @return R9 64-bit vector of features implemented. 853 (1=implemented, 0=not implemented) 854 @return R10 64-bit vector of current feature settings. 855 @return R11 64-bit vector of features controllable by 856 software. (1=controllable, 0= not controllable) 857 858**/ 859#define PAL_BUS_GET_FEATURES 9 860 861/** 862 PAL Procedure - PAL_BUS_SET_FEATURES. 863 864 Enable or disable configurable features in processor bus 865 interface. It is required by Itanium processors. The PAL procedure 866 supports the Static Registers calling convention. It could be 867 called at physical mode. 868 869 @param Index Index of PAL_BUS_SET_FEATURES within the list 870 of PAL procedures. 871 @param FeatureSelect 64-bit vector denoting desired state of 872 each feature (1=select, 0=non-select). 873 874 @retval 0 Call completed without error 875 @retval -2 Invalid argument 876 @retval -3 Call completed with error. 877 878**/ 879#define PAL_BUS_SET_FEATURES 10 880 881 882/** 883 PAL Procedure - PAL_DEBUG_INFO. 884 885 Return the number of instruction and data breakpoint 886 registers. It is required by Itanium processors. The 887 PAL procedure supports the Static Registers calling 888 convention. It could be called at physical mode and virtual 889 mode. 890 891 @param Index Index of PAL_DEBUG_INFO within the list of PAL 892 procedures. 893 894 @retval 0 Call completed without error 895 @retval -2 Invalid argument 896 @retval -3 Call completed with error. 897 898 @return R9 Unsigned 64-bit integer denoting the number of 899 pairs of instruction debug registers implemented 900 by the processor. 901 @return R10 Unsigned 64-bit integer denoting the number of 902 pairs of data debug registers implemented by the 903 processor. 904 905**/ 906#define PAL_DEBUG_INFO 11 907 908/** 909 PAL Procedure - PAL_FIXED_ADDR. 910 911 Return the fixed component of a processor's directed address. 912 It is required by Itanium processors. The PAL 913 procedure supports the Static Registers calling convention. It 914 could be called at physical mode and virtual mode. 915 916 @param Index Index of PAL_FIXED_ADDR within the list of PAL 917 procedures. 918 919 @retval 0 Call completed without error 920 @retval -2 Invalid argument 921 @retval -3 Call completed with error. 922 923 @return R9 Fixed geographical address of this processor. 924 925**/ 926#define PAL_FIXED_ADDR 12 927 928/** 929 PAL Procedure - PAL_FREQ_BASE. 930 931 Return the frequency of the output clock for use by the 932 platform, if generated by the processor. It is optinal. The 933 PAL procedure supports the Static Registers calling 934 convention. It could be called at physical mode and virtual 935 mode. 936 937 @param Index Index of PAL_FREQ_BASE within the list of PAL 938 procedures. 939 940 @retval 0 Call completed without error 941 @retval -1 Unimplemented procedure 942 @retval -2 Invalid argument 943 @retval -3 Call completed with error. 944 945 @return R9 Base frequency of the platform if generated by the 946 processor chip. 947 948**/ 949#define PAL_FREQ_BASE 13 950 951 952/** 953 PAL Procedure - PAL_FREQ_RATIOS. 954 955 Return ratio of processor, bus, and interval time counter to 956 processor input clock or output clock for platform use, if 957 generated by the processor. It is required by Itanium processors. The PAL 958 procedure supports the Static Registers calling convention. It 959 could be called at physical mode and virtual mode. 960 961 @param Index Index of PAL_FREQ_RATIOS within the list of PAL 962 procedures. 963 964 @retval 0 Call completed without error 965 @retval -2 Invalid argument 966 @retval -3 Call completed with error. 967 968 @return R9 Ratio of the processor frequency to the input 969 clock of the processor, if the platform clock is 970 generated externally or to the output clock to the 971 platform, if the platform clock is generated by 972 the processor. 973 @return R10 Ratio of the bus frequency to the input clock of 974 the processor, if the platform clock is generated 975 externally or to the output clock to the platform, 976 if the platform clock is generated by the 977 processor. 978 @return R11 Ratio of the interval timer counter rate to input 979 clock of the processor, if the platform clock is 980 generated externally or to the output clock to the 981 platform, if the platform clock is generated by 982 the processor. 983 984**/ 985#define PAL_FREQ_RATIOS 14 986 987typedef struct { 988 UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical 989 ///< processors on this physical 990 ///< processor package that are 991 ///< enabled. 992 UINT64 ThreadsPerCore:8; ///< Number of threads per core. 993 UINT64 Reserved1:8; 994 UINT64 CoresPerProcessor:8; ///< Total number of cores on this 995 ///< physical processor package. 996 UINT64 Reserved2:8; 997 UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package 998 ///< identifier which was 999 ///< assigned at reset by the 1000 ///< platform or bus 1001 ///< controller. This value may 1002 ///< or may not be unique 1003 ///< across the entire platform 1004 ///< since it depends on the 1005 ///< platform vendor's policy. 1006 UINT64 Reserved3:8; 1007} PAL_LOGICAL_PROCESSPR_OVERVIEW; 1008 1009typedef struct { 1010 UINT64 ThreadId:16; ///< The thread identifier of the logical 1011 ///< processor for which information is being 1012 ///< returned. This value will be unique on a per 1013 ///< core basis. 1014 UINT64 Reserved1:16; 1015 UINT64 CoreId:16; ///< The core identifier of the logical processor 1016 ///< for which information is being returned. 1017 ///< This value will be unique on a per physical 1018 ///< processor package basis. 1019 UINT64 Reserved2:16; 1020} PAL_LOGICAL_PROCESSORN_INFO1; 1021 1022typedef struct { 1023 UINT64 LogicalAddress:16; ///< Geographical address of the logical 1024 ///< processor for which information is being 1025 ///< returned. This is the same value that is 1026 ///< returned by the PAL_FIXED_ADDR procedure 1027 ///< when it is called on the logical processor. 1028 UINT64 Reserved:48; 1029} PAL_LOGICAL_PROCESSORN_INFO2; 1030 1031/** 1032 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL. 1033 1034 Return information on which logical processors map to a 1035 physical processor die. It is optinal. The PAL procedure 1036 supports the Static Registers calling convention. It could be 1037 called at physical mode and virtual mode. 1038 1039 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL 1040 procedures. 1041 @param ProcessorNumber Signed 64-bit integer that specifies 1042 for which logical processor 1043 information is being requested. When 1044 this input argument is -1, information 1045 is returned about the logical 1046 processor on which the procedure call 1047 is made. This input argument must be 1048 in the range of 1 up to one less than 1049 the number of logical processors 1050 returned by num_log in the 1051 log_overview return value. 1052 1053 @retval 0 Call completed without error 1054 @retval -1 Unimplemented procedure 1055 @retval -2 Invalid argument 1056 @retval -3 Call completed with error. 1057 1058 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW. 1059 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1. 1060 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2. 1061 1062**/ 1063#define PAL_LOGICAL_TO_PHYSICAL 42 1064 1065typedef struct { 1066 UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number defining the 1067 ///< number of generic PMC/PMD pairs. 1068 UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in the range 1069 ///< 0:60 defining the number of 1070 ///< implemented counter bits. 1071 UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number defining the 1072 ///< event type for counting processor cycles. 1073 UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit 1074 ///< number defining the 1075 ///< event type for retired 1076 ///< instruction bundles. 1077 UINT64 Reserved:32; 1078} PAL_PERFORMANCE_INFO; 1079 1080/** 1081 PAL Procedure - PAL_PERF_MON_INFO. 1082 1083 Return the number and type of performance monitors. It is 1084 required by Itanium processors. The PAL procedure supports the Static 1085 Registers calling convention. It could be called at physical 1086 mode and virtual mode. 1087 1088 @param Index Index of PAL_PERF_MON_INFO within the list of 1089 PAL procedures. 1090 @param PerformanceBuffer An address to an 8-byte aligned 1091 128-byte memory buffer. 1092 1093 @retval 0 Call completed without error 1094 @retval -2 Invalid argument 1095 @retval -3 Call completed with error. 1096 1097 @return R9 Information about the performance monitors 1098 implemented. See PAL_PERFORMANCE_INFO; 1099 1100**/ 1101#define PAL_PERF_MON_INFO 15 1102 1103#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0 1104#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1 1105 1106/** 1107 PAL Procedure - PAL_PLATFORM_ADDR. 1108 1109 Specify processor interrupt block address and I/O port space 1110 address. It is required by Itanium processors. The PAL procedure supports the 1111 Static Registers calling convention. It could be called at 1112 physical mode and virtual mode. 1113 1114 @param Index Index of PAL_PLATFORM_ADDR within the list of 1115 PAL procedures. 1116 @param Type Unsigned 64-bit integer specifying the type of 1117 block. 0 indicates that the processor interrupt 1118 block pointer should be initialized. 1 indicates 1119 that the processor I/O block pointer should be 1120 initialized. 1121 @param Address Unsigned 64-bit integer specifying the address 1122 to which the processor I/O block or interrupt 1123 block shall be set. The address must specify 1124 an implemented physical address on the 1125 processor model, bit 63 is ignored. 1126 1127 @retval 0 Call completed without error 1128 @retval -1 Unimplemented procedure. 1129 @retval -2 Invalid argument 1130 @retval -3 Call completed with error. 1131 1132**/ 1133#define PAL_PLATFORM_ADDR 16 1134 1135typedef struct { 1136 UINT64 Reserved1:36; 1137 UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplemented 1138 ///< instruction address reported as 1139 ///< fault. Denotes how the processor 1140 ///< reports the detection of 1141 ///< unimplemented instruction 1142 ///< addresses. When 1, the processor 1143 ///< reports an Unimplemented 1144 ///< Instruction Address fault on the 1145 ///< unimplemented address; when 0, it 1146 ///< reports an Unimplemented 1147 ///< Instruction Address trap on the 1148 ///< previous instruction in program 1149 ///< order. This feature may only be 1150 ///< interrogated by 1151 ///< PAL_PROC_GET_FEATURES. It may not 1152 ///< be enabled or disabled by 1153 ///< PAL_PROC_SET_FEATURES. The 1154 ///< corresponding argument is ignored. 1155 1156 UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins 1157 ///< present. Denotes the absence of INIT, 1158 ///< PMI, LINT0 and LINT1 pins on the 1159 ///< processor. When 1, the pins are absent. 1160 ///< When 0, the pins are present. This 1161 ///< feature may only be interrogated by 1162 ///< PAL_PROC_GET_FEATURES. It may not be 1163 ///< enabled or disabled by 1164 ///< PAL_PROC_SET_FEATURES. The corresponding 1165 ///< argument is ignored. 1166 1167 UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple 1168 ///< implementation of 1169 ///< unimplemented instruction 1170 ///< addresses. Denotes how an 1171 ///< unimplemented instruction 1172 ///< address is recorded in IIP 1173 ///< on an Unimplemented 1174 ///< Instruction Address trap or 1175 ///< fault. When 1, the full 1176 ///< unimplemented address is 1177 ///< recorded in IIP; when 0, the 1178 ///< address is sign extended 1179 ///< (virtual addresses) or zero 1180 ///< extended (physical 1181 ///< addresses). This feature may 1182 ///< only be interrogated by 1183 ///< PAL_PROC_GET_FEATURES. It 1184 ///< may not be enabled or 1185 ///< disabled by 1186 ///< PAL_PROC_SET_FEATURES. The 1187 ///< corresponding argument is 1188 ///< ignored. 1189 1190 UINT64 NoVariablePState:1; ///< Bit39, No Variable P-state 1191 ///< performance: A value of 1, indicates 1192 ///< that a processor implements 1193 ///< techniques to optimize performance 1194 ///< for the given P-state power budget 1195 ///< by dynamically varying the 1196 ///< frequency, such that maximum 1197 ///< performance is achieved for the 1198 ///< power budget. A value of 0, 1199 ///< indicates that P-states have no 1200 ///< frequency variation or very small 1201 ///< frequency variations for their given 1202 ///< power budget. This feature may only 1203 ///< be interrogated by 1204 ///< PAL_PROC_GET_FEATURES. it may not be 1205 ///< enabled or disabled by 1206 ///< PAL_PROC_SET_FEATURES. The 1207 ///< corresponding argument is ignored. 1208 1209 UINT64 NoVM:1; ///< Bit40, No Virtual Machine features implemented. 1210 ///< Denotes whether PSR.vm is implemented. This 1211 ///< feature may only be interrogated by 1212 ///< PAL_PROC_GET_FEATURES. It may not be enabled or 1213 ///< disabled by PAL_PROC_SET_FEATURES. The 1214 ///< corresponding argument is ignored. 1215 1216 UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, and XFS 1217 ///< implemented. Denotes whether XIP, XPSR, 1218 ///< and XFS are implemented for machine 1219 ///< check recovery. This feature may only be 1220 ///< interrogated by PAL_PROC_GET_FEATURES. 1221 ///< It may not be enabled or disabled by 1222 ///< PAL_PROC_SET_FEATURES. The corresponding 1223 ///< argument is ignored. 1224 1225 UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through XR3 implemented. 1226 ///< Denotes whether XR1 XR3 are 1227 ///< implemented for machine check 1228 ///< recovery. This feature may only be 1229 ///< interrogated by PAL_PROC_GET_FEATURES. 1230 ///< It may not be enabled or disabled by 1231 ///< PAL_PROC_SET_FEATURES. The 1232 ///< corresponding argument is ignored. 1233 1234 UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic 1235 ///< Predicate Prediction. When 1236 ///< 0, the processor may predict 1237 ///< predicate results and 1238 ///< execute speculatively, but 1239 ///< may not commit results until 1240 ///< the actual predicates are 1241 ///< known. When 1, the processor 1242 ///< shall not execute predicated 1243 ///< instructions until the 1244 ///< actual predicates are known. 1245 1246 UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Spontaneous 1247 ///< Deferral. When 1, the 1248 ///< processor may optionally 1249 ///< defer speculative loads 1250 ///< that do not encounter any 1251 ///< exception conditions, but 1252 ///< that trigger other 1253 ///< implementation-dependent 1254 ///< conditions (e.g., cache 1255 ///< miss). When 0, spontaneous 1256 ///< deferral is disabled. 1257 1258 UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic 1259 ///< Data Cache Prefetch. 1260 ///< When 0, the processor 1261 ///< may prefetch into the 1262 ///< caches any data which 1263 ///< has not been accessed 1264 ///< by instruction 1265 ///< execution, but which 1266 ///< is likely to be 1267 ///< accessed. When 1, no 1268 ///< data may be fetched 1269 ///< until it is needed for 1270 ///< instruction execution 1271 ///< or is fetched by an 1272 ///< lfetch instruction. 1273 1274 UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable 1275 ///< DynamicInstruction Cache 1276 ///< Prefetch. When 0, the 1277 ///< processor may prefetch 1278 ///< into the caches any 1279 ///< instruction which has 1280 ///< not been executed, but 1281 ///< whose execution is 1282 ///< likely. When 1, 1283 ///< instructions may not be 1284 ///< fetched until needed or 1285 ///< hinted for execution. 1286 ///< (Prefetch for a hinted 1287 ///< branch is allowed even 1288 ///< when dynamic instruction 1289 ///< cache prefetch is 1290 ///< disabled.) 1291 1292 UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynamic branch 1293 ///< prediction. When 0, the 1294 ///< processor may predict branch 1295 ///< targets and speculatively 1296 ///< execute, but may not commit 1297 ///< results. When 1, the processor 1298 ///< must wait until branch targets 1299 ///< are known to execute. 1300 UINT64 Reserved2:4; 1301 UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL 1302 ///< P-state procedures (PAL_PSTATE_INFO, 1303 ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will 1304 ///< return with a status of -1 1305 ///< (Unimplemented procedure). 1306 1307 UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling 1308 ///< on data-poisoning event 1309 ///< detection. When 0, a CMCI 1310 ///< will be signaled on error 1311 ///< detection. When 1, an MCA 1312 ///< will be signaled on error 1313 ///< detection. If this feature 1314 ///< is not supported, then the 1315 ///< corresponding argument is 1316 ///< ignored when calling 1317 ///< PAL_PROC_SET_FEATURES. Note 1318 ///< that the functionality of 1319 ///< this bit is independent of 1320 ///< the setting in bit 60 1321 ///< (Enable CMCI promotion), and 1322 ///< that the bit 60 setting does 1323 ///< not affect CMCI signaling 1324 ///< for data-poisoning related 1325 ///< events. Volume 2: Processor 1326 ///< Abstraction Layer 2:431 1327 ///< PAL_PROC_GET_FEATURES 1328 1329 UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw 1330 ///< instruction. When 0, the vmsw instruction 1331 ///< causes a Virtualization fault when 1332 ///< executed at the most privileged level. 1333 ///< When 1, this bit will enable normal 1334 ///< operation of the vmsw instruction. 1335 1336 UINT64 EnableEnvNotification:1; ///< Bit55, Enable external 1337 ///< notification when the processor 1338 ///< detects hardware errors caused 1339 ///< by environmental factors that 1340 ///< could cause loss of 1341 ///< deterministic behavior of the 1342 ///< processor. When 1, this bit will 1343 ///< enable external notification, 1344 ///< when 0 external notification is 1345 ///< not provided. The type of 1346 ///< external notification of these 1347 ///< errors is processor-dependent. A 1348 ///< loss of processor deterministic 1349 ///< behavior is considered to have 1350 ///< occurred if these 1351 ///< environmentally induced errors 1352 ///< cause the processor to deviate 1353 ///< from its normal execution and 1354 ///< eventually causes different 1355 ///< behavior which can be observed 1356 ///< at the processor bus pins. 1357 ///< Processor errors that do not 1358 ///< have this effects (i.e., 1359 ///< software induced machine checks) 1360 ///< may or may not be promoted 1361 ///< depending on the processor 1362 ///< implementation. 1363 1364 UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on 1365 ///< internal processor time-out. 1366 ///< When 0, the processor may 1367 ///< generate a BINIT on an 1368 ///< internal processor time-out. 1369 ///< When 1, the processor will not 1370 ///< generate a BINIT on an 1371 ///< internal processor time-out. 1372 ///< The event is silently ignored. 1373 1374 UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management 1375 ///< (DPM). When 0, the hardware may reduce 1376 ///< power consumption by removing the clock 1377 ///< input from idle functional units. When 1, 1378 ///< all functional units will receive clock 1379 ///< input, even when idle. 1380 1381 UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0, 1382 ///< the processor uses normal coherency 1383 ///< requests and responses. When 1, the 1384 ///< processor answers all requests as if 1385 ///< the line were not present. 1386 1387 UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the 1388 ///< processor performs cast outs on 1389 ///< cacheable pages and issues and responds 1390 ///< to coherency requests normally. When 1, 1391 ///< the processor performs a memory access 1392 ///< for each reference regardless of cache 1393 ///< contents and issues no coherence 1394 ///< requests and responds as if the line 1395 ///< were not present. Cache contents cannot 1396 ///< be relied upon when the cache is 1397 ///< disabled. WARNING: Semaphore 1398 ///< instructions may not be atomic or may 1399 ///< cause Unsupported Data Reference faults 1400 ///< if caches are disabled. 1401 1402 UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When 1403 ///< 1, Corrected Machine Check 1404 ///< Interrupts (CMCI) are promoted to 1405 ///< MCAs. They are also further 1406 ///< promoted to BERR if bit 39, Enable 1407 ///< MCA promotion, is also set and 1408 ///< they are promoted to BINIT if bit 1409 ///< 38, Enable MCA to BINIT promotion, 1410 ///< is also set. This bit has no 1411 ///< effect if MCA signalling is 1412 ///< disabled (see 1413 ///< PAL_BUS_GET/SET_FEATURES) 1414 1415 UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT 1416 ///< promotion. When 1, machine 1417 ///< check aborts (MCAs) are 1418 ///< promoted to the Bus 1419 ///< Initialization signal, and 1420 ///< the BINIT pin is assert on 1421 ///< each occurrence of an MCA. 1422 ///< Setting this bit has no 1423 ///< effect if BINIT signalling 1424 ///< is disabled. (See 1425 ///< PAL_BUS_GET/SET_FEATURES) 1426 1427 UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When 1428 ///< 1, machine check aborts (MCAs) are 1429 ///< promoted to the Bus Error signal, 1430 ///< and the BERR pin is assert on each 1431 ///< occurrence of an MCA. Setting this 1432 ///< bit has no effect if BERR 1433 ///< signalling is disabled. (See 1434 ///< PAL_BUS_GET/SET_FEATURES) 1435 1436 UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When 1437 ///< 1, the Bus Error (BERR) signal is 1438 ///< promoted to the Bus Initialization 1439 ///< (BINIT) signal, and the BINIT pin 1440 ///< is asserted on the occurrence of 1441 ///< each Bus Error. Setting this bit 1442 ///< has no effect if BINIT signalling 1443 ///< is disabled. (See 1444 ///< PAL_BUS_GET/SET_FEATURES) 1445} PAL_PROCESSOR_FEATURES; 1446 1447/** 1448 PAL Procedure - PAL_PROC_GET_FEATURES. 1449 1450 Return configurable processor features and their current 1451 setting. It is required by Itanium processors. The PAL procedure supports the 1452 Static Registers calling convention. It could be called at 1453 physical mode and virtual mode. 1454 1455 @param Index Index of PAL_PROC_GET_FEATURES within the list of 1456 PAL procedures. 1457 @param Reserved Reserved parameter. 1458 @param FeatureSet Feature set information is being requested 1459 for. 1460 1461 @retval 1 Call completed without error; The 1462 feature_set passed is not supported but a 1463 feature_set of a larger value is supported. 1464 @retval 0 Call completed without error 1465 @retval -2 Invalid argument 1466 @retval -3 Call completed with error. 1467 @retval -8 feature_set passed is beyond the maximum 1468 feature_set supported 1469 1470 @return R9 64-bit vector of features implemented. See 1471 PAL_PROCESSOR_FEATURES. 1472 @return R10 64-bit vector of current feature settings. See 1473 PAL_PROCESSOR_FEATURES. 1474 @return R11 64-bit vector of features controllable by 1475 software. 1476 1477**/ 1478#define PAL_PROC_GET_FEATURES 17 1479 1480 1481/** 1482 PAL Procedure - PAL_PROC_SET_FEATURES. 1483 1484 Enable or disable configurable processor features. It is 1485 required by Itanium processors. The PAL procedure supports the Static 1486 Registers calling convention. It could be called at physical 1487 mode. 1488 1489 @param Index Index of PAL_PROC_SET_FEATURES within the list of 1490 PAL procedures. 1491 @param FeatureSelect 64-bit vector denoting desired state of 1492 each feature (1=select, 0=non-select). 1493 @param FeatureSet Feature set to apply changes to. See 1494 PAL_PROC_GET_FEATURES for more information 1495 on feature sets. 1496 1497 @retval 1 Call completed without error; The 1498 feature_set passed is not supported but a 1499 feature_set of a larger value is supported 1500 @retval 0 Call completed without error 1501 @retval -2 Invalid argument 1502 @retval -3 Call completed with error. 1503 @retval -8 feature_set passed is beyond the maximum 1504 feature_set supported 1505 1506**/ 1507#define PAL_PROC_SET_FEATURES 18 1508 1509 1510// 1511// Value of PAL_REGISTER_INFO.InfoRequest. 1512// 1513#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0 1514#define PAL_APPLICATION_REGISTER_READABLE 1 1515#define PAL_CONTROL_REGISTER_IMPLEMENTED 2 1516#define PAL_CONTROL_REGISTER_READABLE 3 1517 1518 1519/** 1520 PAL Procedure - PAL_REGISTER_INFO. 1521 1522 Return AR and CR register information. It is required by Itanium processors. 1523 The PAL procedure supports the Static Registers calling 1524 convention. It could be called at physical mode and virtual 1525 mode. 1526 1527 @param Index Index of PAL_REGISTER_INFO within the list of 1528 PAL procedures. 1529 @param InfoRequest Unsigned 64-bit integer denoting what 1530 register information is requested. See 1531 PAL_REGISTER_INFO.InfoRequest above. 1532 1533 @retval 0 Call completed without error 1534 @retval -2 Invalid argument 1535 @retval -3 Call completed with error. 1536 1537 @return R9 64-bit vector denoting information for registers 1538 0-63. Bit 0 is register 0, bit 63 is register 63. 1539 @return R10 64-bit vector denoting information for registers 1540 64-127. Bit 0 is register 64, bit 63 is register 1541 127. 1542 1543**/ 1544#define PAL_REGISTER_INFO 39 1545 1546/** 1547 PAL Procedure - PAL_RSE_INFO. 1548 1549 Return RSE information. It is required by Itanium processors. The PAL 1550 procedure supports the Static Registers calling convention. It 1551 could be called at physical mode and virtual mode. 1552 1553 @param Index Index of PAL_RSE_INFO within the list of 1554 PAL procedures. 1555 @param InfoRequest Unsigned 64-bit integer denoting what 1556 register information is requested. See 1557 PAL_REGISTER_INFO.InfoRequest above. 1558 1559 @retval 0 Call completed without error 1560 @retval -2 Invalid argument 1561 @retval -3 Call completed with error. 1562 1563 @return R9 Number of physical stacked general registers. 1564 @return R10 RSE hints supported by processor. 1565 1566**/ 1567#define PAL_RSE_INFO 19 1568 1569typedef struct { 1570 UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD) 1571 ///< number that provides identification 1572 ///< information about the PAL_B firmware. 1573 UINT64 Reserved1:8; 1574 UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicating the 1575 ///< vendor of the PAL code. 1576 UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD) 1577 ///< number that provides identification 1578 ///< information about the PAL_A firmware. In 1579 ///< the split PAL_A model, this return value 1580 ///< is the version number of the 1581 ///< processor-specific PAL_A. The generic 1582 ///< PAL_A version is not returned by this 1583 ///< procedure in the split PAL_A model. 1584 UINT64 Reserved2:16; 1585} PAL_VERSION_INFO; 1586 1587/** 1588 PAL Procedure - PAL_VERSION. 1589 1590 Return version of PAL code. It is required by Itanium processors. The PAL 1591 procedure supports the Static Registers calling convention. It 1592 could be called at physical mode and virtual mode. 1593 1594 @param Index Index of PAL_VERSION within the list of 1595 PAL procedures. 1596 @param InfoRequest Unsigned 64-bit integer denoting what 1597 register information is requested. See 1598 PAL_REGISTER_INFO.InfoRequest above. 1599 1600 @retval 0 Call completed without error 1601 @retval -2 Invalid argument 1602 @retval -3 Call completed with error. 1603 1604 @return R9 8-byte formatted value returning the minimum PAL 1605 version needed for proper operation of the 1606 processor. See PAL_VERSION_INFO above. 1607 @return R10 8-byte formatted value returning the current PAL 1608 version running on the processor. See 1609 PAL_VERSION_INFO above. 1610 1611**/ 1612#define PAL_VERSION 20 1613 1614 1615 1616// 1617// Vectors of PAL_MC_CLEAR_LOG.pending 1618// 1619#define PAL_MC_PENDING BIT0 1620#define PAL_INIT_PENDING BIT1 1621 1622/** 1623 PAL Procedure - PAL_MC_CLEAR_LOG. 1624 1625 Clear all error information from processor error logging 1626 registers. It is required by Itanium processors. The PAL procedure supports 1627 the Static Registers calling convention. It could be called at 1628 physical mode and virtual mode. 1629 1630 @param Index Index of PAL_MC_CLEAR_LOG within the list of 1631 PAL procedures. 1632 1633 @retval 0 Call completed without error 1634 @retval -2 Invalid argument 1635 @retval -3 Call completed with error. 1636 1637 @return R9 64-bit vector denoting whether an event is 1638 pending. See PAL_MC_CLEAR_LOG.pending above. 1639 1640**/ 1641#define PAL_MC_CLEAR_LOG 21 1642 1643/** 1644 PAL Procedure - PAL_MC_DRAIN. 1645 1646 Ensure that all operations that could cause an MCA have 1647 completed. It is required by Itanium processors. The PAL procedure supports 1648 the Static Registers calling convention. It could be called at 1649 physical mode and virtual mode. 1650 1651 @param Index Index of PAL_MC_DRAIN within the list of PAL 1652 procedures. 1653 1654 @retval 0 Call completed without error 1655 @retval -2 Invalid argument 1656 @retval -3 Call completed with error. 1657 1658**/ 1659#define PAL_MC_DRAIN 22 1660 1661 1662/** 1663 PAL Procedure - PAL_MC_DYNAMIC_STATE. 1664 1665 Return Processor Dynamic State for logging by SAL. It is 1666 optional. The PAL procedure supports the Static Registers 1667 calling convention. It could be called at physical mode. 1668 1669 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL 1670 procedures. 1671 @param Offset Offset of the next 8 bytes of Dynamic Processor 1672 State to return. (multiple of 8). 1673 1674 @retval 0 Call completed without error 1675 @retval -1 Unimplemented procedure. 1676 @retval -2 Invalid argument 1677 @retval -3 Call completed with error. 1678 1679 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic 1680 Processor State returned. 1681 @return R10 Next 8 bytes of Dynamic Processor State. 1682 1683**/ 1684#define PAL_MC_DYNAMIC_STATE 24 1685 1686 1687 1688// 1689// Values of PAL_MC_ERROR_INFO.InfoIndex. 1690// 1691#define PAL_PROCESSOR_ERROR_MAP 0 1692#define PAL_PROCESSOR_STATE_PARAM 1 1693#define PAL_STRUCTURE_SPECIFIC_ERROR 2 1694 1695typedef struct { 1696 UINT64 CoreId:4; ///< Bit3:0, Processor core ID (default is 0 for 1697 ///< processors with a single core) 1698 1699 UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (default is 0 for 1700 ///< processors that execute a single thread) 1701 1702 UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is 1703 ///< available for 1st, 2nd, 3rd, and 4th 1704 ///< level instruction caches. 1705 1706 UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is 1707 ///< available for 1st, 2nd, 3rd, and 4th 1708 ///< level data/unified caches. 1709 1710 UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is available 1711 ///< for 1st, 2nd, 3rd, and 4th level 1712 ///< instruction TLB. 1713 1714 UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is available 1715 ///< for 1st, 2nd, 3rd, and 4th level 1716 ///< data/unified TLB 1717 1718 UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is 1719 ///< available for the 1st, 2nd, 3rd, 1720 ///< and 4th level processor bus 1721 ///< hierarchy. 1722 UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is 1723 ///< available on register file 1724 ///< structures. 1725 UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is 1726 ///< available on micro-architectural 1727 ///< structures. 1728 UINT64 Reserved:16; 1729} PAL_MC_ERROR_INFO_LEVEL_INDEX; 1730 1731// 1732// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex 1733// 1734#define PAL_ERR_INFO_BY_LEVEL_INDEX 0 1735#define PAL_ERR_INFO_TARGET_ADDRESS 1 1736#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2 1737#define PAL_ERR_INFO_REPONSER_INDENTIFIER 3 1738#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4 1739 1740typedef struct { 1741 UINT64 Operation:4; ///< Bit3:0, Type of cache operation that caused 1742 ///< the machine check: 0 - unknown or internal 1743 ///< error 1 - load 2 - store 3 - instruction 1744 ///< fetch or instruction prefetch 4 - data 1745 ///< prefetch (both hardware and software) 5 - 1746 ///< snoop (coherency check) 6 - cast out 1747 ///< (explicit or implicit write-back of a cache 1748 ///< line) 7 - move in (cache line fill) 1749 1750 UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where the 1751 ///< error occurred. A value of 0 1752 ///< indicates the first level of cache. 1753 UINT64 Reserved1:2; 1754 UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the data part of the cache line. 1755 UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the tag part of the cache line. 1756 UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the data cache 1757 1758 UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the 1759 ///< instruction cache. 1760 1761 UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache 1762 ///< line is held shared. 2 - cache line is held 1763 ///< exclusive. 3 - cache line is modified. All other 1764 ///< values are reserved. 1765 1766 UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check 1767 ///< parameter is valid. 1768 1769 UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of 1770 ///< the cache indicated by this value. 1771 1772 UINT64 WayIndexIsValid:1; ///< Bit21, The way and index field in the 1773 ///< cache_check parameter is valid. 1774 1775 UINT64 Reserved2:1; 1776 UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error was 1777 ///< detected, and data was poisoned for 1778 ///< the corresponding cache line during 1779 ///< castout. 1780 UINT64 Reserved3:8; 1781 UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache 1782 ///< line where the error occurred. 1783 UINT64 Reserved4:2; 1784 1785 UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value 1786 ///< is set to zero, the instruction that 1787 ///< generated the machine check was an 1788 ///< Intel Itanium instruction. If this bit 1789 ///< is set to one, the instruction that 1790 ///< generated the machine check was IA-32 1791 ///< instruction. 1792 1793 UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the 1794 ///< cache_check parameter is valid. 1795 1796 UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The 1797 ///< privilege level of the instruction 1798 ///< bundle responsible for generating the 1799 ///< machine check. 1800 1801 UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the 1802 ///< cache_check parameter is 1803 ///< valid. 1804 1805 UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit 1806 ///< is set to one to indicate that the machine 1807 ///< check has been corrected. 1808 1809 UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid: 1810 ///< This bit is set to one to 1811 ///< indicate that a valid target 1812 ///< address has been logged. 1813 1814 UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: This 1815 ///< bit is set to one to indicate that 1816 ///< a valid requester identifier has 1817 ///< been logged. 1818 1819 UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This 1820 ///< bit is set to one to indicate that 1821 ///< a valid responder identifier has 1822 ///< been logged. 1823 1824 UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction pointer. 1825 ///< This bit is set to one to indicate 1826 ///< that a valid precise instruction 1827 ///< pointer has been logged. 1828 1829} PAL_CACHE_CHECK_INFO; 1830 1831 1832typedef struct { 1833 UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the translation 1834 ///< register where the failure occurred. 1835 UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the 1836 ///< TLB_check parameter is valid. 1837 UINT64 Reserved1 :1; 1838 UINT64 TlbLevel:2; ///< Bit11:10, The level of the TLB where the 1839 ///< error occurred. A value of 0 indicates the 1840 ///< first level of TLB 1841 UINT64 Reserved2 :4; 1842 1843 UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the data 1844 ///< translation registers. 1845 1846 UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the instruction 1847 ///< translation registers 1848 1849 UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data 1850 ///< translation cache. 1851 1852 UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the instruction 1853 ///< translation cache. 1854 1855 UINT64 FailedOperation:4; ///< Bit23:20, Type of cache operation that 1856 ///< caused the machine check: 0 - unknown 1857 ///< 1 - TLB access due to load instruction 1858 ///< 2 - TLB access due to store 1859 ///< instruction 3 - TLB access due to 1860 ///< instruction fetch or instruction 1861 ///< prefetch 4 - TLB access due to data 1862 ///< prefetch (both hardware and software) 1863 ///< 5 - TLB shoot down access 6 - TLB 1864 ///< probe instruction (probe, tpa) 7 - 1865 ///< move in (VHPT fill) 8 - purge (insert 1866 ///< operation that purges entries or a TLB 1867 ///< purge instruction) All other values 1868 ///< are reserved. 1869 1870 UINT64 Reserved3:30; 1871 UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value 1872 ///< is set to zero, the instruction that 1873 ///< generated the machine check was an 1874 ///< Intel Itanium instruction. If this bit 1875 ///< is set to one, the instruction that 1876 ///< generated the machine check was IA-32 1877 ///< instruction. 1878 1879 UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the 1880 ///< TLB_check parameter is valid. 1881 1882 UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The 1883 ///< privilege level of the instruction 1884 ///< bundle responsible for generating the 1885 ///< machine check. 1886 1887 UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the 1888 ///< TLB_check parameter is valid. 1889 1890 UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit 1891 ///< is set to one to indicate that the machine 1892 ///< check has been corrected. 1893 1894 UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid: 1895 ///< This bit is set to one to 1896 ///< indicate that a valid target 1897 ///< address has been logged. 1898 1899 UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: This 1900 ///< bit is set to one to indicate that 1901 ///< a valid requester identifier has 1902 ///< been logged. 1903 1904 UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This 1905 ///< bit is set to one to indicate that 1906 ///< a valid responder identifier has 1907 ///< been logged. 1908 1909 UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction pointer. 1910 ///< This bit is set to one to indicate 1911 ///< that a valid precise instruction 1912 ///< pointer has been logged. 1913} PAL_TLB_CHECK_INFO; 1914 1915/** 1916 PAL Procedure - PAL_MC_ERROR_INFO. 1917 1918 Return Processor Machine Check Information and Processor 1919 Static State for logging by SAL. It is required by Itanium processors. The 1920 PAL procedure supports the Static Registers calling 1921 convention. It could be called at physical and virtual mode. 1922 1923 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL 1924 procedures. 1925 @param InfoIndex Unsigned 64-bit integer identifying the 1926 error information that is being requested. 1927 See PAL_MC_ERROR_INFO.InfoIndex. 1928 @param LevelIndex 8-byte formatted value identifying the 1929 structure to return error information 1930 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX. 1931 @param ErrorTypeIndex Unsigned 64-bit integer denoting the 1932 type of error information that is 1933 being requested for the structure 1934 identified in LevelIndex. 1935 1936 @retval 0 Call completed without error 1937 @retval -2 Invalid argument 1938 @retval -3 Call completed with error. 1939 @retval -6 Argument was valid, but no error 1940 information was available 1941 1942 @return R9 Error information returned. The format of this 1943 value is dependant on the input values passed. 1944 @return R10 If this value is zero, all the error information 1945 specified by err_type_index has been returned. If 1946 this value is one, more structure-specific error 1947 information is available and the caller needs to 1948 make this procedure call again with level_index 1949 unchanged and err_type_index, incremented. 1950 1951**/ 1952#define PAL_MC_ERROR_INFO 25 1953 1954/** 1955 PAL Procedure - PAL_MC_EXPECTED. 1956 1957 Set/Reset Expected Machine Check Indicator. It is required by 1958 Itanium processors. The PAL procedure supports the Static Registers calling 1959 convention. It could be called at physical mode. 1960 1961 @param Index Index of PAL_MC_EXPECTED within the list of PAL 1962 procedures. 1963 @param Expected Unsigned integer with a value of 0 or 1 to 1964 set or reset the hardware resource 1965 PALE_CHECK examines for expected machine 1966 checks. 1967 1968 @retval 0 Call completed without error 1969 @retval -2 Invalid argument 1970 @retval -3 Call completed with error. 1971 1972 @return R9 Unsigned integer denoting whether a machine check 1973 was previously expected. 1974 1975**/ 1976#define PAL_MC_EXPECTED 23 1977 1978/** 1979 PAL Procedure - PAL_MC_REGISTER_MEM. 1980 1981 Register min-state save area with PAL for machine checks and 1982 inits. It is required by Itanium processors. The PAL procedure supports the 1983 Static Registers calling convention. It could be called at 1984 physical mode. 1985 1986 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL 1987 procedures. 1988 @param Address Physical address of the buffer to be 1989 registered with PAL. 1990 1991 @retval 0 Call completed without error 1992 @retval -2 Invalid argument 1993 @retval -3 Call completed with error. 1994 1995**/ 1996#define PAL_MC_REGISTER_MEM 27 1997 1998/** 1999 PAL Procedure - PAL_MC_RESUME. 2000 2001 Restore minimal architected state and return to interrupted 2002 process. It is required by Itanium processors. The PAL procedure supports the 2003 Static Registers calling convention. It could be called at 2004 physical mode. 2005 2006 @param Index Index of PAL_MC_RESUME within the list of PAL 2007 procedures. 2008 @param SetCmci Unsigned 64 bit integer denoting whether to 2009 set the CMC interrupt. A value of 0 indicates 2010 not to set the interrupt, a value of 1 2011 indicated to set the interrupt, and all other 2012 values are reserved. 2013 @param SavePtr Physical address of min-state save area used 2014 to used to restore processor state. 2015 @param NewContext Unsigned 64-bit integer denoting whether 2016 the caller is returning to a new context. 2017 A value of 0 indicates the caller is 2018 returning to the interrupted context, a 2019 value of 1 indicates that the caller is 2020 returning to a new context. 2021 2022 @retval -2 Invalid argument 2023 @retval -3 Call completed with error. 2024 2025**/ 2026#define PAL_MC_RESUME 26 2027 2028/** 2029 PAL Procedure - PAL_HALT. 2030 2031 Enter the low-power HALT state or an implementation-dependent 2032 low-power state. It is optinal. The PAL procedure supports the 2033 Static Registers calling convention. It could be called at 2034 physical mode. 2035 2036 @param Index Index of PAL_HALT within the list of PAL 2037 procedures. 2038 @param HaltState Unsigned 64-bit integer denoting low power 2039 state requested. 2040 @param IoDetailPtr 8-byte aligned physical address pointer to 2041 information on the type of I/O 2042 (load/store) requested. 2043 2044 @retval 0 Call completed without error 2045 @retval -1 Unimplemented procedure 2046 @retval -2 Invalid argument 2047 @retval -3 Call completed with error. 2048 2049 @return R9 Value returned if a load instruction is requested 2050 in the io_detail_ptr 2051 2052**/ 2053#define PAL_HALT 28 2054 2055 2056/** 2057 PAL Procedure - PAL_HALT_INFO. 2058 2059 Return the low power capabilities of the processor. It is 2060 required by Itanium processors. The PAL procedure supports the 2061 Stacked Registers calling convention. It could be called at 2062 physical and virtual mode. 2063 2064 @param Index Index of PAL_HALT_INFO within the list of PAL 2065 procedures. 2066 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned 2067 on an 8-byte boundary. 2068 2069 @retval 0 Call completed without error 2070 @retval -2 Invalid argument 2071 @retval -3 Call completed with error. 2072 2073**/ 2074#define PAL_HALT_INFO 257 2075 2076 2077/** 2078 PAL Procedure - PAL_HALT_LIGHT. 2079 2080 Enter the low power LIGHT HALT state. It is required by 2081 Itanium processors. The PAL procedure supports the Static Registers calling 2082 convention. It could be called at physical and virtual mode. 2083 2084 @param Index Index of PAL_HALT_LIGHT within the list of PAL 2085 procedures. 2086 2087 @retval 0 Call completed without error 2088 @retval -2 Invalid argument 2089 @retval -3 Call completed with error. 2090 2091**/ 2092#define PAL_HALT_LIGHT 29 2093 2094/** 2095 PAL Procedure - PAL_CACHE_LINE_INIT. 2096 2097 Initialize tags and data of a cache line for processor 2098 testing. It is required by Itanium processors. The PAL procedure supports the 2099 Static Registers calling convention. It could be called at 2100 physical and virtual mode. 2101 2102 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL 2103 procedures. 2104 @param Address Unsigned 64-bit integer value denoting the 2105 physical address from which the physical page 2106 number is to be generated. The address must be 2107 an implemented physical address, bit 63 must 2108 be zero. 2109 @param DataValue 64-bit data value which is used to 2110 initialize the cache line. 2111 2112 @retval 0 Call completed without error 2113 @retval -2 Invalid argument 2114 @retval -3 Call completed with error. 2115 2116**/ 2117#define PAL_CACHE_LINE_INIT 31 2118 2119/** 2120 PAL Procedure - PAL_CACHE_READ. 2121 2122 Read tag and data of a cache line for diagnostic testing. It 2123 is optional. The PAL procedure supports the 2124 Satcked Registers calling convention. It could be called at 2125 physical mode. 2126 2127 @param Index Index of PAL_CACHE_READ within the list of PAL 2128 procedures. 2129 @param LineId 8-byte formatted value describing where in the 2130 cache to read the data. 2131 @param Address 64-bit 8-byte aligned physical address from 2132 which to read the data. The address must be an 2133 implemented physical address on the processor 2134 model with bit 63 set to zero. 2135 2136 @retval 1 The word at address was found in the 2137 cache, but the line was invalid. 2138 @retval 0 Call completed without error 2139 @retval -2 Invalid argument 2140 @retval -3 Call completed with error. 2141 @retval -5 The word at address was not found in the 2142 cache. 2143 @retval -7 The operation requested is not supported 2144 for this cache_type and level. 2145 2146 @return R9 Right-justified value returned from the cache 2147 line. 2148 @return R10 The number of bits returned in data. 2149 @return R11 The status of the cache line. 2150 2151**/ 2152#define PAL_CACHE_READ 259 2153 2154 2155/** 2156 PAL Procedure - PAL_CACHE_WRITE. 2157 2158 Write tag and data of a cache for diagnostic testing. It is 2159 optional. The PAL procedure supports the Satcked Registers 2160 calling convention. It could be called at physical mode. 2161 2162 @param Index Index of PAL_CACHE_WRITE within the list of PAL 2163 procedures. 2164 @param LineId 8-byte formatted value describing where in the 2165 cache to write the data. 2166 @param Address 64-bit 8-byte aligned physical address at 2167 which the data should be written. The address 2168 must be an implemented physical address on the 2169 processor model with bit 63 set to 0. 2170 @param Data Unsigned 64-bit integer value to write into 2171 the specified part of the cache. 2172 2173 @retval 0 Call completed without error 2174 @retval -2 Invalid argument 2175 @retval -3 Call completed with error. 2176 @retval -7 The operation requested is not supported 2177 for this cache_type and level. 2178 2179**/ 2180#define PAL_CACHE_WRITE 260 2181 2182/** 2183 PAL Procedure - PAL_TEST_INFO. 2184 2185 Returns alignment and size requirements needed for the memory 2186 buffer passed to the PAL_TEST_PROC procedure as well as 2187 information on self-test control words for the processor self 2188 tests. It is required by Itanium processors. The PAL procedure supports the 2189 Static Registers calling convention. It could be called at 2190 physical mode. 2191 2192 @param Index Index of PAL_TEST_INFO within the list of PAL 2193 procedures. 2194 @param TestPhase Unsigned integer that specifies which phase 2195 of the processor self-test information is 2196 being requested on. A value of 0 indicates 2197 the phase two of the processor self-test and 2198 a value of 1 indicates phase one of the 2199 processor self-test. All other values are 2200 reserved. 2201 2202 @retval 0 Call completed without error 2203 @retval -2 Invalid argument 2204 @retval -3 Call completed with error. 2205 2206 @return R9 Unsigned 64-bit integer denoting the number of 2207 bytes of main memory needed to perform the second 2208 phase of processor self-test. 2209 @return R10 Unsigned 64-bit integer denoting the alignment 2210 required for the memory buffer. 2211 @return R11 48-bit wide bit-field indicating if control of 2212 the processor self-tests is supported and which 2213 bits of the test_control field are defined for 2214 use. 2215 2216**/ 2217#define PAL_TEST_INFO 37 2218 2219typedef struct { 2220 UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory 2221 ///< buffer that is passed to this procedure. 2222 ///< BufferSize must be greater than or equal in 2223 ///< size to the bytes_needed return value from 2224 ///< PAL_TEST_INFO, otherwise this procedure will 2225 ///< return with an invalid argument return 2226 ///< value. 2227 2228 UINT64 TestPhase:8; ///< Defines which phase of the processor 2229 ///< self-tests are requested to be run. A value 2230 ///< of zero indicates to run phase two of the 2231 ///< processor self-tests. Phase two of the 2232 ///< processor self-tests are ones that require 2233 ///< external memory to execute correctly. A 2234 ///< value of one indicates to run phase one of 2235 ///< the processor self-tests. Phase one of the 2236 ///< processor self-tests are tests run during 2237 ///< PALE_RESET and do not depend on external 2238 ///< memory to run correctly. When the caller 2239 ///< requests to have phase one of the processor 2240 ///< self-test run via this procedure call, a 2241 ///< memory buffer may be needed to save and 2242 ///< restore state as required by the PAL calling 2243 ///< conventions. The procedure PAL_TEST_INFO 2244 ///< informs the caller about the requirements of 2245 ///< the memory buffer. 2246} PAL_TEST_INFO_INFO; 2247 2248typedef struct { 2249 UINT64 TestControl:47; ///< This is an ordered implementation-specific 2250 ///< control word that allows the user control 2251 ///< over the length and runtime of the 2252 ///< processor self-tests. This control word is 2253 ///< ordered from the longest running tests up 2254 ///< to the shortest running tests with bit 0 2255 ///< controlling the longest running test. PAL 2256 ///< may not implement all 47-bits of the 2257 ///< test_control word. PAL communicates if a 2258 ///< bit provides control by placing a zero in 2259 ///< that bit. If a bit provides no control, 2260 ///< PAL will place a one in it. PAL will have 2261 ///< two sets of test_control bits for the two 2262 ///< phases of the processor self-test. PAL 2263 ///< provides information about implemented 2264 ///< test_control bits at the hand-off from PAL 2265 ///< to SAL for the firmware recovery check. 2266 ///< These test_control bits provide control 2267 ///< for phase one of processor self-test. It 2268 ///< also provides this information via the PAL 2269 ///< procedure call PAL_TEST_INFO for both the 2270 ///< phase one and phase two processor tests 2271 ///< depending on which information the caller 2272 ///< is requesting. PAL interprets these bits 2273 ///< as input parameters on two occasions. The 2274 ///< first time is when SAL passes control back 2275 ///< to PAL after the firmware recovery check. 2276 ///< The second time is when a call to 2277 ///< PAL_TEST_PROC is made. When PAL interprets 2278 ///< these bits it will only interpret 2279 ///< implemented test_control bits and will 2280 ///< ignore the values located in the 2281 ///< unimplemented test_control bits. PAL 2282 ///< interprets the implemented bits such that 2283 ///< if a bit contains a zero, this indicates 2284 ///< to run the test. If a bit contains a one, 2285 ///< this indicates to PAL to skip the test. If 2286 ///< the cs bit indicates that control is not 2287 ///< available, the test_control bits will be 2288 ///< ignored or generate an illegal argument in 2289 ///< procedure calls if the caller sets these 2290 ///< bits. 2291 2292 UINT64 ControlSupport:1; ///< This bit defines if an implementation 2293 ///< supports control of the PAL self-tests 2294 ///< via the self-test control word. If 2295 ///< this bit is 0, the implementation does 2296 ///< not support control of the processor 2297 ///< self-tests via the self-test control 2298 ///< word. If this bit is 1, the 2299 ///< implementation does support control of 2300 ///< the processor self-tests via the 2301 ///< self-test control word. If control is 2302 ///< not supported, GR37 will be ignored at 2303 ///< the hand-off between SAL and PAL after 2304 ///< the firmware recovery check and the 2305 ///< PAL procedures related to the 2306 ///< processor self-tests may return 2307 ///< illegal arguments if a user tries to 2308 ///< use the self-test control features. 2309 UINT64 Reserved:16; 2310} PAL_SELF_TEST_CONTROL; 2311 2312typedef struct { 2313 UINT64 Attributes:8; ///< Specifies the memory attributes that are 2314 ///< allowed to be used with the memory buffer 2315 ///< passed to this procedure. The attributes 2316 ///< parameter is a vector where each bit 2317 ///< represents one of the virtual memory 2318 ///< attributes defined by the architecture.See 2319 ///< MEMORY_AATRIBUTES. The caller is required 2320 ///< to support the cacheable attribute for the 2321 ///< memory buffer, otherwise an invalid 2322 ///< argument will be returned. 2323 UINT64 Reserved:8; 2324 UINT64 TestControl:48; ///< Is the self-test control word 2325 ///< corresponding to the test_phase passed. 2326 ///< This test_control directs the coverage and 2327 ///< runtime of the processor self-tests 2328 ///< specified by the test_phase input 2329 ///< argument. Information on if this 2330 ///< feature is implemented and the number of 2331 ///< bits supported can be obtained by the 2332 ///< PAL_TEST_INFO procedure call. If this 2333 ///< feature is implemented by the processor, 2334 ///< the caller can selectively skip parts of 2335 ///< the processor self-test by setting 2336 ///< test_control bits to a one. If a bit has a 2337 ///< zero, this test will be run. The values in 2338 ///< the unimplemented bits are ignored. If 2339 ///< PAL_TEST_INFO indicated that the self-test 2340 ///< control word is not implemented, this 2341 ///< procedure will return with an invalid 2342 ///< argument status if the caller sets any of 2343 ///< the test_control bits. See 2344 ///< PAL_SELF_TEST_CONTROL. 2345} PAL_TEST_CONTROL; 2346 2347/** 2348 PAL Procedure - PAL_TEST_PROC. 2349 2350 Perform late processor self test. It is required by Itanium processors. The 2351 PAL procedure supports the Static Registers calling 2352 convention. It could be called at physical mode. 2353 2354 @param Index Index of PAL_TEST_PROC within the list of PAL 2355 procedures. 2356 @param TestAddress 64-bit physical address of main memory 2357 area to be used by processor self-test. 2358 The memory region passed must be 2359 cacheable, bit 63 must be zero. 2360 @param TestInfo Input argument specifying the size of the 2361 memory buffer passed and the phase of the 2362 processor self-test that should be run. See 2363 PAL_TEST_INFO. 2364 @param TestParam Input argument specifying the self-test 2365 control word and the allowable memory 2366 attributes that can be used with the memory 2367 buffer. See PAL_TEST_CONTROL. 2368 2369 @retval 1 Call completed without error, but hardware 2370 failures occurred during self-test. 2371 @retval 0 Call completed without error 2372 @retval -2 Invalid argument 2373 @retval -3 Call completed with error. 2374 2375 @return R9 Formatted 8-byte value denoting the state of the 2376 processor after self-test 2377 2378**/ 2379#define PAL_TEST_PROC 258 2380 2381typedef struct { 2382 UINT32 NumberOfInterruptControllers; ///< Number of interrupt 2383 ///< controllers currently 2384 ///< enabled on the system. 2385 2386 UINT32 NumberOfProcessors; ///< Number of processors currently 2387 ///< enabled on the system. 2388} PAL_PLATFORM_INFO; 2389 2390/** 2391 PAL Procedure - PAL_COPY_INFO. 2392 2393 Return information needed to relocate PAL procedures and PAL 2394 PMI code to memory. It is required by Itanium processors. The PAL procedure 2395 supports the Static Registers calling convention. It could be 2396 called at physical mode. 2397 2398 @param Index Index of PAL_COPY_INFO within the list of PAL 2399 procedures. 2400 @param CopyType Unsigned integer denoting type of procedures 2401 for which copy information is requested. 2402 @param PlatformInfo 8-byte formatted value describing the 2403 number of processors and the number of 2404 interrupt controllers currently enabled 2405 on the system. See PAL_PLATFORM_INFO. 2406 @param McaProcStateInfo Unsigned integer denoting the number 2407 of bytes that SAL needs for the 2408 min-state save area for each 2409 processor. 2410 2411 @retval 0 Call completed without error 2412 @retval -2 Invalid argument 2413 @retval -3 Call completed with error. 2414 2415 @return R9 Unsigned integer denoting the number of bytes of 2416 PAL information that must be copied to main 2417 memory. 2418 @return R10 Unsigned integer denoting the starting alignment 2419 of the data to be copied. 2420 2421**/ 2422#define PAL_COPY_INFO 30 2423 2424/** 2425 PAL Procedure - PAL_COPY_PAL. 2426 2427 Relocate PAL procedures and PAL PMI code to memory. It is 2428 required by Itanium processors. The PAL procedure supports the Stacked 2429 Registers calling convention. It could be called at physical 2430 mode. 2431 2432 @param Index Index of PAL_COPY_PAL within the list of PAL 2433 procedures. 2434 @param TargetAddress Physical address of a memory buffer to 2435 copy relocatable PAL procedures and PAL 2436 PMI code. 2437 @param AllocSize Unsigned integer denoting the size of the 2438 buffer passed by SAL for the copy operation. 2439 @param CopyOption Unsigned integer indicating whether 2440 relocatable PAL code and PAL PMI code 2441 should be copied from firmware address 2442 space to main memory. 2443 2444 @retval 0 Call completed without error 2445 @retval -2 Invalid argument 2446 @retval -3 Call completed with error. 2447 2448 @return R9 Unsigned integer denoting the offset of PAL_PROC 2449 in the relocatable segment copied. 2450 2451**/ 2452#define PAL_COPY_PAL 256 2453 2454/** 2455 PAL Procedure - PAL_ENTER_IA_32_ENV. 2456 2457 Enter IA-32 System environment. It is optional. The PAL 2458 procedure supports the Static Registers calling convention. 2459 It could be called at physical mode. 2460 2461 Note: Since this is a special call, it does not follow the PAL 2462 static register calling convention. GR28 contains the index of 2463 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other 2464 input arguments including GR29-GR31 are setup by SAL to values 2465 as required by the IA-32 operating system defined in Table 2466 11-67. The registers that are designated as preserved, scratch, 2467 input arguments and procedure return values by the static 2468 procedure calling convention are not followed by this call. For 2469 instance, GR5 and GR6 need not be preserved since these are 2470 regarded as scratch by the IA-32 operating system. Note: In an 2471 MP system, this call must be COMPLETED on the first CPU to enter 2472 the IA-32 System Environment (may or may not be the BSP) prior 2473 to being called on the remaining processors in the MP system. 2474 2475 @param Index GR28 contains the index of the 2476 PAL_ENTER_IA_32_ENV call within the list of PAL 2477 procedures. 2478 2479 2480 @retval The status is returned in GR4. 2481 -1 - Un-implemented procedure 0 JMPE detected 2482 at privilege level 2483 2484 0 - 1 SAL allocated buffer for IA-32 System 2485 Environment operation is too small 2486 2487 2 - IA-32 Firmware Checksum Error 2488 2489 3 - SAL allocated buffer for IA-32 System 2490 Environment operation is not properly aligned 2491 2492 4 - Error in SAL MP Info Table 2493 2494 5 - Error in SAL Memory Descriptor Table 2495 2496 6 - Error in SAL System Table 2497 2498 7 - Inconsistent IA-32 state 2499 2500 8 - IA-32 Firmware Internal Error 2501 2502 9 - IA-32 Soft Reset (Note: remaining register 2503 state is undefined for this termination 2504 reason) 2505 2506 10 - Machine Check Error 2507 2508 11 - Error in SAL I/O Intercept Table 2509 2510 12 - Processor exit due to other processor in 2511 MP system terminating the IA32 system 2512 environment. (Note: remaining register state 2513 is undefined for this termination reason.) 2514 2515 13 - Itanium architecture-based state 2516 corruption by either SAL PMI handler or I/O 2517 Intercept callback function. 2518 2519 2520**/ 2521#define PAL_ENTER_IA_32_ENV 33 2522 2523/** 2524 PAL Procedure - PAL_PMI_ENTRYPOINT. 2525 2526 Register PMI memory entrypoints with processor. It is required 2527 by Itanium processors. The PAL procedure supports the Stacked Registers 2528 calling convention. It could be called at physical mode. 2529 2530 @param Index Index of PAL_PMI_ENTRYPOINT within the list of 2531 PAL procedures. 2532 @param SalPmiEntry 256-byte aligned physical address of SAL 2533 PMI entrypoint in memory. 2534 2535 @retval 0 Call completed without error 2536 @retval -2 Invalid argument 2537 @retval -3 Call completed with error. 2538 2539**/ 2540#define PAL_PMI_ENTRYPOINT 32 2541 2542 2543/** 2544 2545 The ASCII brand identification string will be copied to the 2546 address specified in the address input argument. The processor 2547 brand identification string is defined to be a maximum of 128 2548 characters long; 127 bytes will contain characters and the 128th 2549 byte is defined to be NULL (0). A processor may return less than 2550 the 127 ASCII characters as long as the string is null 2551 terminated. The string length will be placed in the brand_info 2552 return argument. 2553 2554**/ 2555#define PAL_BRAND_INFO_ID_REQUEST 0 2556 2557/** 2558 PAL Procedure - PAL_BRAND_INFO. 2559 2560 Provides processor branding information. It is optional by 2561 Itanium processors. The PAL procedure supports the Stacked Registers calling 2562 convention. It could be called at physical and Virtual mode. 2563 2564 @param Index Index of PAL_BRAND_INFO within the list of PAL 2565 procedures. 2566 @param InfoRequest Unsigned 64-bit integer specifying the 2567 information that is being requested. (See 2568 PAL_BRAND_INFO_ID_REQUEST) 2569 @param Address Unsigned 64-bit integer specifying the 2570 address of the 128-byte block to which the 2571 processor brand string shall be written. 2572 2573 @retval 0 Call completed without error 2574 @retval -1 Unimplemented procedure 2575 @retval -2 Invalid argument 2576 @retval -3 Call completed with error. 2577 @retval -6 Input argument is not implemented. 2578 2579 @return R9 Brand information returned. The format of this 2580 value is dependent on the input values passed. 2581 2582**/ 2583#define PAL_BRAND_INFO 274 2584 2585/** 2586 PAL Procedure - PAL_GET_HW_POLICY. 2587 2588 Returns the current hardware resource sharing policy of the 2589 processor. It is optional by Itanium processors. The PAL procedure supports 2590 the Static Registers calling convention. It could be called at 2591 physical and Virtual mode. 2592 2593 2594 @param Index Index of PAL_GET_HW_POLICY within the list of PAL 2595 procedures. 2596 @param ProcessorNumber Unsigned 64-bit integer that specifies 2597 for which logical processor 2598 information is being requested. This 2599 input argument must be zero for the 2600 first call to this procedure and can 2601 be a maximum value of one less than 2602 the number of logical processors 2603 impacted by the hardware resource 2604 sharing policy, which is returned by 2605 the R10 return value. 2606 2607 @retval 0 Call completed without error 2608 @retval -1 Unimplemented procedure 2609 @retval -2 Invalid argument 2610 @retval -3 Call completed with error. 2611 @retval -9 Call requires PAL memory buffer. 2612 2613 @return R9 Unsigned 64-bit integer representing the current 2614 hardware resource sharing policy. 2615 @return R10 Unsigned 64-bit integer that returns the number 2616 of logical processors impacted by the policy 2617 input argument. 2618 @return R11 Unsigned 64-bit integer containing the logical 2619 address of one of the logical processors 2620 impacted by policy modification. 2621 2622**/ 2623#define PAL_GET_HW_POLICY 48 2624 2625 2626// 2627// Value of PAL_SET_HW_POLICY.Policy 2628// 2629#define PAL_SET_HW_POLICY_PERFORMANCE 0 2630#define PAL_SET_HW_POLICY_FAIRNESS 1 2631#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2 2632#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3 2633 2634/** 2635 PAL Procedure - PAL_SET_HW_POLICY. 2636 2637 Sets the current hardware resource sharing policy of the 2638 processor. It is optional by Itanium processors. The PAL procedure supports 2639 the Static Registers calling convention. It could be called at 2640 physical and Virtual mode. 2641 2642 @param Index Index of PAL_SET_HW_POLICY within the list of PAL 2643 procedures. 2644 @param Policy Unsigned 64-bit integer specifying the hardware 2645 resource sharing policy the caller is setting. 2646 See Value of PAL_SET_HW_POLICY.Policy above. 2647 2648 @retval 1 Call completed successfully but could not 2649 change the hardware policy since a 2650 competing logical processor is set in 2651 exclusive high priority. 2652 @retval 0 Call completed without error 2653 @retval -1 Unimplemented procedure 2654 @retval -2 Invalid argument 2655 @retval -3 Call completed with error. 2656 @retval -9 Call requires PAL memory buffer. 2657 2658**/ 2659#define PAL_SET_HW_POLICY 49 2660 2661typedef struct { 2662 UINT64 Mode:3; ///< Bit2:0, Indicates the mode of operation for this 2663 ///< procedure: 0 - Query mode 1 - Error inject mode 2664 ///< (err_inj should also be specified) 2 - Cancel 2665 ///< outstanding trigger. All other fields in 2666 ///< PAL_MC_ERROR_TYPE_INFO, 2667 ///< PAL_MC_ERROR_STRUCTURE_INFO and 2668 ///< PAL_MC_ERROR_DATA_BUFFER are ignored. All other 2669 ///< values are reserved. 2670 2671 UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of error 2672 ///< injection: 0 - Error inject only (no 2673 ///< error consumption) 1 - Error inject 2674 ///< and consume All other values are 2675 ///< reserved. 2676 2677 UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity desired 2678 ///< for error injection/query. Definitions 2679 ///< of the different error severity types 2680 ///< 0 - Corrected error 1 - Recoverable 2681 ///< error 2 - Fatal error 3 - Reserved 2682 2683 UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure 2684 ///< identification for error 2685 ///< injection/query: 0 - Any structure 2686 ///< (cannot be used during query mode). 2687 ///< When selected, the structure type used 2688 ///< for error injection is determined by 2689 ///< PAL. 1 - Cache 2 - TLB 3 - Register 2690 ///< file 4 - Bus/System interconnect 5-15 2691 ///< - Reserved 16-31 - Processor 2692 ///< specific error injection 2693 ///< capabilities.ErrorDataBuffer is used 2694 ///< to specify error types. Please refer 2695 ///< to the processor specific 2696 ///< documentation for additional details. 2697 2698 UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure 2699 ///< hierarchy for error 2700 ///< injection/query: 0 - Any level of 2701 ///< hierarchy (cannot be used during 2702 ///< query mode). When selected, the 2703 ///< structure hierarchy used for error 2704 ///< injection is determined by PAL. 1 2705 ///< - Error structure hierarchy 2706 ///< level-1 2 - Error structure 2707 ///< hierarchy level-2 3 - Error 2708 ///< structure hierarchy level-3 4 - 2709 ///< Error structure hierarchy level-4 2710 ///< All other values are reserved. 2711 2712 UINT64 Reserved:32; ///< Reserved 47:16 Reserved 2713 2714 UINT64 ImplSpec:16; ///< Bit63:48, Processor specific error injection capabilities. 2715} PAL_MC_ERROR_TYPE_INFO; 2716 2717typedef struct { 2718 UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates that the 2719 ///< structure information fields 2720 ///< (c_t,cl_p,cl_id) are valid and 2721 ///< should be used for error injection. 2722 ///< When 0, the structure information 2723 ///< fields are ignored, and the values 2724 ///< of these fields used for error 2725 ///< injection are 2726 ///< implementation-specific. 2727 2728 UINT64 CacheType:2; ///< Bit2:1 Indicates which cache should be used 2729 ///< for error injection: 0 - Reserved 1 - 2730 ///< Instruction cache 2 - Data or unified cache 2731 ///< 3 - Reserved 2732 2733 UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the portion of the 2734 ///< cache line where the error should 2735 ///< be injected: 0 - Reserved 1 - Tag 2736 ///< 2 - Data 3 - mesi All other 2737 ///< values are reserved. 2738 2739 UINT64 Mechanism:3; ///< Bit8:6 Indicates which mechanism is used to 2740 ///< identify the cache line to be used for error 2741 ///< injection: 0 - Reserved 1 - Virtual address 2742 ///< provided in the inj_addr field of the buffer 2743 ///< pointed to by err_data_buffer should be used 2744 ///< to identify the cache line for error 2745 ///< injection. 2 - Physical address provided in 2746 ///< the inj_addr field of the buffer pointed to 2747 ///< by err_data_buffershould be used to identify 2748 ///< the cache line for error injection. 3 - way 2749 ///< and index fields provided in err_data_buffer 2750 ///< should be used to identify the cache line 2751 ///< for error injection. All other values are 2752 ///< reserved. 2753 2754 UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates that a 2755 ///< multiple bit, non-correctable 2756 ///< error should be injected in the 2757 ///< cache line specified by cl_id. 2758 ///< If this injected error is not 2759 ///< consumed, it may eventually 2760 ///< cause a data-poisoning event 2761 ///< resulting in a corrected error 2762 ///< signal, when the associated 2763 ///< cache line is cast out (implicit 2764 ///< or explicit write-back of the 2765 ///< cache line). The error severity 2766 ///< specified by err_sev in 2767 ///< err_type_info must be set to 0 2768 ///< (corrected error) when this bit 2769 ///< is set. 2770 2771 UINT64 Reserved1:22; 2772 2773 UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates that the 2774 ///< trigger information fields (trigger, 2775 ///< trigger_pl) are valid and should be 2776 ///< used for error injection. When 0, 2777 ///< the trigger information fields are 2778 ///< ignored and error injection is 2779 ///< performed immediately. 2780 2781 UINT64 Triger:4; ///< Bit36:33 Indicates the operation type to be 2782 ///< used as the error trigger condition. The 2783 ///< address corresponding to the trigger is 2784 ///< specified in the trigger_addr field of the 2785 ///< buffer pointed to by err_data_buffer: 0 - 2786 ///< Instruction memory access. The trigger match 2787 ///< conditions for this operation type are similar 2788 ///< to the IBR address breakpoint match conditions 2789 ///< 1 - Data memory access. The trigger match 2790 ///< conditions for this operation type are similar 2791 ///< to the DBR address breakpoint match conditions 2792 ///< All other values are reserved. 2793 2794 UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the privilege 2795 ///< level of the context during which 2796 ///< the error should be injected: 0 - 2797 ///< privilege level 0 1 - privilege 2798 ///< level 1 2 - privilege level 2 3 - 2799 ///< privilege level 3 All other values 2800 ///< are reserved. If the implementation 2801 ///< does not support privilege level 2802 ///< qualifier for triggers (i.e. if 2803 ///< trigger_pl is 0 in the capabilities 2804 ///< vector), this field is ignored and 2805 ///< triggers can be taken at any 2806 ///< privilege level. 2807 2808 UINT64 Reserved2:24; 2809} PAL_MC_ERROR_STRUCT_INFO; 2810 2811/** 2812 2813 Buffer Pointed to by err_data_buffer - TLB 2814 2815**/ 2816typedef struct { 2817 UINT64 TrigerAddress; 2818 UINT64 VirtualPageNumber:52; 2819 UINT64 Reserved1:8; 2820 UINT64 RegionId:24; 2821 UINT64 Reserved2:40; 2822} PAL_MC_ERROR_DATA_BUFFER_TLB; 2823 2824/** 2825 PAL Procedure - PAL_MC_ERROR_INJECT. 2826 2827 Injects the requested processor error or returns information 2828 on the supported injection capabilities for this particular 2829 processor implementation. It is optional by Itanium processors. The PAL 2830 procedure supports the Stacked Registers calling convention. 2831 It could be called at physical and Virtual mode. 2832 2833 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL 2834 procedures. 2835 @param ErrorTypeInfo Unsigned 64-bit integer specifying the 2836 first level error information which 2837 identifies the error structure and 2838 corresponding structure hierarchy, and 2839 the error severity. 2840 @param ErrorStructInfo Unsigned 64-bit integer identifying 2841 the optional structure specific 2842 information that provides the second 2843 level details for the requested error. 2844 @param ErrorDataBuffer 64-bit physical address of a buffer 2845 providing additional parameters for 2846 the requested error. The address of 2847 this buffer must be 8-byte aligned. 2848 2849 @retval 0 Call completed without error 2850 @retval -1 Unimplemented procedure 2851 @retval -2 Invalid argument 2852 @retval -3 Call completed with error. 2853 @retval -4 Call completed with error; the requested 2854 error could not be injected due to failure in 2855 locating the target location in the specified 2856 structure. 2857 @retval -5 Argument was valid, but requested error 2858 injection capability is not supported. 2859 @retval -9 Call requires PAL memory buffer. 2860 2861 @return R9 64-bit vector specifying the supported error 2862 injection capabilities for the input argument 2863 combination of struct_hier, err_struct and 2864 err_sev fields in ErrorTypeInfo. 2865 @return R10 64-bit vector specifying the architectural 2866 resources that are used by the procedure. 2867 2868**/ 2869#define PAL_MC_ERROR_INJECT 276 2870 2871 2872// 2873// Types of PAL_GET_PSTATE.Type 2874// 2875#define PAL_GET_PSTATE_RECENT 0 2876#define PAL_GET_PSTATE_AVERAGE_NEW_START 1 2877#define PAL_GET_PSTATE_AVERAGE 2 2878#define PAL_GET_PSTATE_NOW 3 2879 2880/** 2881 PAL Procedure - PAL_GET_PSTATE. 2882 2883 Returns the performance index of the processor. It is optional 2884 by Itanium processors. The PAL procedure supports the Stacked Registers 2885 calling convention. It could be called at physical and Virtual 2886 mode. 2887 2888 @param Index Index of PAL_GET_PSTATE within the list of PAL 2889 procedures. 2890 @param Type Type of performance_index value to be returned 2891 by this procedure.See PAL_GET_PSTATE.Type above. 2892 2893 @retval 1 Call completed without error, but accuracy 2894 of performance index has been impacted by a 2895 thermal throttling event, or a 2896 hardware-initiated event. 2897 @retval 0 Call completed without error 2898 @retval -1 Unimplemented procedure 2899 @retval -2 Invalid argument 2900 @retval -3 Call completed with error. 2901 @retval -9 Call requires PAL memory buffer. 2902 2903 @return R9 Unsigned integer denoting the processor 2904 performance for the time duration since the last 2905 PAL_GET_PSTATE procedure call was made. The 2906 value returned is between 0 and 100, and is 2907 relative to the performance index of the highest 2908 available P-state. 2909 2910**/ 2911#define PAL_GET_PSTATE 262 2912 2913/** 2914 2915 Layout of PAL_PSTATE_INFO.PStateBuffer 2916 2917**/ 2918typedef struct { 2919 UINT32 PerformanceIndex:7; 2920 UINT32 Reserved1:5; 2921 UINT32 TypicalPowerDissipation:20; 2922 UINT32 TransitionLatency1; 2923 UINT32 TransitionLatency2; 2924 UINT32 Reserved2; 2925} PAL_PSTATE_INFO_BUFFER; 2926 2927 2928/** 2929 PAL Procedure - PAL_PSTATE_INFO. 2930 2931 Returns information about the P-states supported by the 2932 processor. It is optional by Itanium processors. The PAL procedure supports 2933 the Static Registers calling convention. It could be called 2934 at physical and Virtual mode. 2935 2936 @param Index Index of PAL_PSTATE_INFO within the list of PAL 2937 procedures. 2938 @param PStateBuffer 64-bit pointer to a 256-byte buffer 2939 aligned on an 8-byte boundary. See 2940 PAL_PSTATE_INFO_BUFFER above. 2941 2942 @retval 0 Call completed without error 2943 @retval -1 Unimplemented procedure 2944 @retval -2 Invalid argument 2945 @retval -3 Call completed with error. 2946 2947 @return R9 Unsigned integer denoting the number of P-states 2948 supported. The maximum value of this field is 16. 2949 @return R10 Dependency domain information 2950 2951**/ 2952#define PAL_PSTATE_INFO 44 2953 2954 2955/** 2956 PAL Procedure - PAL_SET_PSTATE. 2957 2958 To request a processor transition to a given P-state. It is 2959 optional by Itanium processors. The PAL procedure supports the Stacked 2960 Registers calling convention. It could be called at physical 2961 and Virtual mode. 2962 2963 @param Index Index of PAL_SET_PSTATE within the list of PAL 2964 procedures. 2965 @param PState Unsigned integer denoting the processor 2966 P-state being requested. 2967 @param ForcePState Unsigned integer denoting whether the 2968 P-state change should be forced for the 2969 logical processor. 2970 2971 @retval 1 Call completed without error, but 2972 transition request was not accepted 2973 @retval 0 Call completed without error 2974 @retval -1 Unimplemented procedure 2975 @retval -2 Invalid argument 2976 @retval -3 Call completed with error. 2977 @retval -9 Call requires PAL memory buffer. 2978 2979**/ 2980#define PAL_SET_PSTATE 263 2981 2982/** 2983 PAL Procedure - PAL_SHUTDOWN. 2984 2985 Put the logical processor into a low power state which can be 2986 exited only by a reset event. It is optional by Itanium processors. The PAL 2987 procedure supports the Static Registers calling convention. It 2988 could be called at physical mode. 2989 2990 @param Index Index of PAL_SHUTDOWN within the list of PAL 2991 procedures. 2992 @param NotifyPlatform 8-byte aligned physical address 2993 pointer providing details on how to 2994 optionally notify the platform that 2995 the processor is entering a shutdown 2996 state. 2997 2998 @retval -1 Unimplemented procedure 2999 @retval -2 Invalid argument 3000 @retval -3 Call completed with error. 3001 @retval -9 Call requires PAL memory buffer. 3002 3003**/ 3004#define PAL_SHUTDOWN 45 3005 3006/** 3007 3008 Layout of PAL_MEMORY_BUFFER.ControlWord 3009 3010**/ 3011typedef struct { 3012 UINT64 Registration:1; 3013 UINT64 ProbeInterrupt:1; 3014 UINT64 Reserved:62; 3015} PAL_MEMORY_CONTROL_WORD; 3016 3017/** 3018 PAL Procedure - PAL_MEMORY_BUFFER. 3019 3020 Provides cacheable memory to PAL for exclusive use during 3021 runtime. It is optional by Itanium processors. The PAL procedure supports the 3022 Static Registers calling convention. It could be called at 3023 physical mode. 3024 3025 @param Index Index of PAL_MEMORY_BUFFER within the list of PAL 3026 procedures. 3027 @param BaseAddress Physical address of the memory buffer 3028 allocated for PAL use. 3029 @param AllocSize Unsigned integer denoting the size of the 3030 memory buffer. 3031 @param ControlWord Formatted bit vector that provides control 3032 options for this procedure. See 3033 PAL_MEMORY_CONTROL_WORD above. 3034 3035 @retval 1 Call has not completed a buffer relocation 3036 due to a pending interrupt 3037 @retval 0 Call completed without error 3038 @retval -1 Unimplemented procedure 3039 @retval -2 Invalid argument 3040 @retval -3 Call completed with error. 3041 @retval -9 Call requires PAL memory buffer. 3042 3043 @return R9 Returns the minimum size of the memory buffer 3044 required if the alloc_size input argument was 3045 not large enough. 3046 3047**/ 3048#define PAL_MEMORY_BUFFER 277 3049 3050 3051/** 3052 PAL Procedure - PAL_VP_CREATE. 3053 3054 Initializes a new vpd for the operation of a new virtual 3055 processor in the virtual environment. It is optional by Itanium processors. 3056 The PAL procedure supports the Stacked Registers calling 3057 convention. It could be called at Virtual mode. 3058 3059 @param Index Index of PAL_VP_CREATE within the list of PAL 3060 procedures. 3061 @param Vpd 64-bit host virtual pointer to the Virtual 3062 Processor Descriptor (VPD). 3063 @param HostIva 64-bit host virtual pointer to the host IVT 3064 for the virtual processor 3065 @param OptionalHandler 64-bit non-zero host-virtual pointer 3066 to an optional handler for 3067 virtualization intercepts. 3068 3069 @retval 0 Call completed without error 3070 @retval -1 Unimplemented procedure 3071 @retval -2 Invalid argument 3072 @retval -3 Call completed with error. 3073 @retval -9 Call requires PAL memory buffer. 3074 3075**/ 3076#define PAL_VP_CREATE 265 3077 3078/** 3079 3080 Virtual Environment Information Parameter 3081 3082**/ 3083typedef struct { 3084 UINT64 Reserved1:8; 3085 UINT64 Opcode:1; 3086 UINT64 Reserved:53; 3087} PAL_VP_ENV_INFO_RETURN; 3088 3089/** 3090 PAL Procedure - PAL_VP_ENV_INFO. 3091 3092 Returns the parameters needed to enter a virtual environment. 3093 It is optional by Itanium processors. The PAL procedure supports the Stacked 3094 Registers calling convention. It could be called at Virtual 3095 mode. 3096 3097 @param Index Index of PAL_VP_ENV_INFO within the list of PAL 3098 procedures. 3099 @param Vpd 64-bit host virtual pointer to the Virtual 3100 Processor Descriptor (VPD). 3101 @param HostIva 64-bit host virtual pointer to the host IVT 3102 for the virtual processor 3103 @param OptionalHandler 64-bit non-zero host-virtual pointer 3104 to an optional handler for 3105 virtualization intercepts. 3106 3107 @retval 0 Call completed without error 3108 @retval -1 Unimplemented procedure 3109 @retval -2 Invalid argument 3110 @retval -3 Call completed with error. 3111 @retval -9 Call requires PAL memory buffer. 3112 3113 @return R9 Unsigned integer denoting the number of bytes 3114 required by the PAL virtual environment buffer 3115 during PAL_VP_INIT_ENV 3116 @return R10 64-bit vector of virtual environment 3117 information. See PAL_VP_ENV_INFO_RETURN. 3118 3119 3120**/ 3121#define PAL_VP_ENV_INFO 266 3122 3123/** 3124 PAL Procedure - PAL_VP_EXIT_ENV. 3125 3126 Allows a logical processor to exit a virtual environment. 3127 It is optional by Itanium processors. The PAL procedure supports the Stacked 3128 Registers calling convention. It could be called at Virtual 3129 mode. 3130 3131 @param Index Index of PAL_VP_EXIT_ENV within the list of PAL 3132 procedures. 3133 @param Iva Optional 64-bit host virtual pointer to the IVT 3134 when this procedure is done 3135 3136 @retval 0 Call completed without error 3137 @retval -1 Unimplemented procedure 3138 @retval -2 Invalid argument 3139 @retval -3 Call completed with error. 3140 @retval -9 Call requires PAL memory buffer. 3141 3142**/ 3143#define PAL_VP_EXIT_ENV 267 3144 3145 3146 3147/** 3148 PAL Procedure - PAL_VP_INIT_ENV. 3149 3150 Allows a logical processor to enter a virtual environment. It 3151 is optional by Itanium processors. The PAL procedure supports the Stacked 3152 Registers calling convention. It could be called at Virtual 3153 mode. 3154 3155 @param Index Index of PAL_VP_INIT_ENV within the list of PAL 3156 procedures. 3157 @param ConfigOptions 64-bit vector of global configuration 3158 settings. 3159 @param PhysicalBase Host physical base address of a block of 3160 contiguous physical memory for the PAL 3161 virtual environment buffer 1) This 3162 memory area must be allocated by the VMM 3163 and be 4K aligned. The first logical 3164 processor to enter the environment will 3165 initialize the physical block for 3166 virtualization operations. 3167 @param VirtualBase Host virtual base address of the 3168 corresponding physical memory block for 3169 the PAL virtual environment buffer : The 3170 VMM must maintain the host virtual to host 3171 physical data and instruction translations 3172 in TRs for addresses within the allocated 3173 address space. Logical processors in this 3174 virtual environment will use this address 3175 when transitioning to virtual mode 3176 operations. 3177 3178 @retval 0 Call completed without error 3179 @retval -1 Unimplemented procedure 3180 @retval -2 Invalid argument 3181 @retval -3 Call completed with error. 3182 @retval -9 Call requires PAL memory buffer. 3183 3184 @return R9 Virtualization Service Address - VSA specifies 3185 the virtual base address of the PAL 3186 virtualization services in this virtual 3187 environment. 3188 3189 3190**/ 3191#define PAL_VP_INIT_ENV 268 3192 3193 3194/** 3195 PAL Procedure - PAL_VP_REGISTER. 3196 3197 Register a different host IVT and/or a different optional 3198 virtualization intercept handler for the virtual processor 3199 specified by vpd. It is optional by Itanium processors. The PAL procedure 3200 supports the Stacked Registers calling convention. It could be 3201 called at Virtual mode. 3202 3203 @param Index Index of PAL_VP_REGISTER within the list of PAL 3204 procedures. 3205 @param Vpd 64-bit host virtual pointer to the Virtual 3206 Processor Descriptor (VPD) host_iva 64-bit host 3207 virtual pointer to the host IVT for the virtual 3208 processor 3209 @param OptionalHandler 64-bit non-zero host-virtual pointer 3210 to an optional handler for 3211 virtualization intercepts. 3212 3213 @retval 0 Call completed without error 3214 @retval -1 Unimplemented procedure 3215 @retval -2 Invalid argument 3216 @retval -3 Call completed with error. 3217 @retval -9 Call requires PAL memory buffer. 3218 3219**/ 3220#define PAL_VP_REGISTER 269 3221 3222 3223/** 3224 PAL Procedure - PAL_VP_RESTORE. 3225 3226 Restores virtual processor state for the specified vpd on the 3227 logical processor. It is optional by Itanium processors. The PAL procedure 3228 supports the Stacked Registers calling convention. It could be 3229 called at Virtual mode. 3230 3231 @param Index Index of PAL_VP_RESTORE within the list of PAL 3232 procedures. 3233 @param Vpd 64-bit host virtual pointer to the Virtual 3234 Processor Descriptor (VPD) host_iva 64-bit host 3235 virtual pointer to the host IVT for the virtual 3236 processor 3237 @param PalVector Vector specifies PAL procedure 3238 implementation-specific state to be 3239 restored. 3240 3241 @retval 0 Call completed without error 3242 @retval -1 Unimplemented procedure 3243 @retval -2 Invalid argument 3244 @retval -3 Call completed with error. 3245 @retval -9 Call requires PAL memory buffer. 3246 3247**/ 3248#define PAL_VP_RESTORE 270 3249 3250/** 3251 PAL Procedure - PAL_VP_SAVE. 3252 3253 Saves virtual processor state for the specified vpd on the 3254 logical processor. It is optional by Itanium processors. The PAL procedure 3255 supports the Stacked Registers calling convention. It could be 3256 called at Virtual mode. 3257 3258 @param Index Index of PAL_VP_SAVE within the list of PAL 3259 procedures. 3260 @param Vpd 64-bit host virtual pointer to the Virtual 3261 Processor Descriptor (VPD) host_iva 64-bit host 3262 virtual pointer to the host IVT for the virtual 3263 processor 3264 @param PalVector Vector specifies PAL procedure 3265 implementation-specific state to be 3266 restored. 3267 3268 @retval 0 Call completed without error 3269 @retval -1 Unimplemented procedure 3270 @retval -2 Invalid argument 3271 @retval -3 Call completed with error. 3272 @retval -9 Call requires PAL memory buffer. 3273 3274**/ 3275#define PAL_VP_SAVE 271 3276 3277 3278/** 3279 PAL Procedure - PAL_VP_TERMINATE. 3280 3281 Terminates operation for the specified virtual processor. It 3282 is optional by Itanium processors. The PAL procedure supports the Stacked 3283 Registers calling convention. It could be called at Virtual 3284 mode. 3285 3286 @param Index Index of PAL_VP_TERMINATE within the list of PAL 3287 procedures. 3288 @param Vpd 64-bit host virtual pointer to the Virtual 3289 Processor Descriptor (VPD) 3290 @param Iva Optional 64-bit host virtual pointer to the IVT 3291 when this procedure is done. 3292 3293 @retval 0 Call completed without error 3294 @retval -1 Unimplemented procedure 3295 @retval -2 Invalid argument 3296 @retval -3 Call completed with error. 3297 @retval -9 Call requires PAL memory buffer. 3298 3299**/ 3300#define PAL_VP_TERMINATE 272 3301 3302#endif 3303