1/** @file
2  This file declares PciCfg2 PPI.
3
4  This ppi Provides platform or chipset-specific access to
5  the PCI configuration space for a specific PCI segment.
6
7  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
8  This program and the accompanying materials
9  are licensed and made available under the terms and conditions of the BSD License
10  which accompanies this distribution.  The full text of the license may be found at
11  http://opensource.org/licenses/bsd-license.php
12
13  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16  @par Revision Reference:
17  This PPI is introduced in PI Version 1.0.
18
19**/
20
21#ifndef __PEI_PCI_CFG2_H__
22#define __PEI_PCI_CFG2_H__
23
24#include <Library/BaseLib.h>
25
26#define EFI_PEI_PCI_CFG2_PPI_GUID \
27  { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
28
29typedef struct _EFI_PEI_PCI_CFG2_PPI   EFI_PEI_PCI_CFG2_PPI;
30
31#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
32  (UINT64) ( \
33  (((UINTN) bus) << 24) | \
34  (((UINTN) dev) << 16) | \
35  (((UINTN) func) << 8) | \
36  (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
37
38///
39/// EFI_PEI_PCI_CFG_PPI_WIDTH
40///
41typedef enum {
42  ///
43  ///  8-bit access
44  ///
45  EfiPeiPciCfgWidthUint8  = 0,
46  ///
47  /// 16-bit access
48  ///
49  EfiPeiPciCfgWidthUint16 = 1,
50  ///
51  /// 32-bit access
52  ///
53  EfiPeiPciCfgWidthUint32 = 2,
54  ///
55  /// 64-bit access
56  ///
57  EfiPeiPciCfgWidthUint64 = 3,
58  EfiPeiPciCfgWidthMaximum
59} EFI_PEI_PCI_CFG_PPI_WIDTH;
60
61///
62/// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
63///
64typedef struct {
65  ///
66  /// 8-bit register offset within the PCI configuration space for a given device's function
67  /// space.
68  ///
69  UINT8   Register;
70  ///
71  /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a
72  /// given device.
73  ///
74  UINT8   Function;
75  ///
76  /// Only the 5 least-significant bits are used to encode one of 32 possible devices.
77  ///
78  UINT8   Device;
79  ///
80  /// 8-bit value to encode between 0 and 255 buses.
81  ///
82  UINT8   Bus;
83  ///
84  /// Register number in PCI configuration space. If this field is zero, then Register is used
85  /// for the register number. If this field is non-zero, then Register is ignored and this field
86  /// is used for the register number.
87  ///
88  UINT32  ExtendedRegister;
89} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
90
91/**
92  Reads from or write to a given location in the PCI configuration space.
93
94  @param  PeiServices     An indirect pointer to the PEI Services Table published by the PEI Foundation.
95
96  @param  This            Pointer to local data for the interface.
97
98  @param  Width           The width of the access. Enumerated in bytes.
99                          See EFI_PEI_PCI_CFG_PPI_WIDTH above.
100
101  @param  Address         The physical address of the access. The format of
102                          the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
103
104  @param  Buffer          A pointer to the buffer of data..
105
106
107  @retval EFI_SUCCESS           The function completed successfully.
108
109  @retval EFI_DEVICE_ERROR      There was a problem with the transaction.
110
111  @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting the operation at this
112                                time.
113
114**/
115typedef
116EFI_STATUS
117(EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO)(
118  IN CONST  EFI_PEI_SERVICES          **PeiServices,
119  IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,
120  IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
121  IN        UINT64                    Address,
122  IN OUT    VOID                      *Buffer
123);
124
125
126/**
127  Performs a read-modify-write operation on the contents
128  from a given location in the PCI configuration space.
129
130  @param  PeiServices     An indirect pointer to the PEI Services Table
131                          published by the PEI Foundation.
132
133  @param  This            Pointer to local data for the interface.
134
135  @param  Width           The width of the access. Enumerated in bytes. Type
136                          EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
137
138  @param  Address         The physical address of the access.
139
140  @param  SetBits         Points to value to bitwise-OR with the read configuration value.
141
142                          The size of the value is determined by Width.
143
144  @param  ClearBits       Points to the value to negate and bitwise-AND with the read configuration value.
145                          The size of the value is determined by Width.
146
147
148  @retval EFI_SUCCESS           The function completed successfully.
149
150  @retval EFI_DEVICE_ERROR      There was a problem with the transaction.
151
152  @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting
153                                the operation at this time.
154
155**/
156typedef
157EFI_STATUS
158(EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW)(
159  IN CONST  EFI_PEI_SERVICES          **PeiServices,
160  IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,
161  IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
162  IN        UINT64                    Address,
163  IN        VOID                      *SetBits,
164  IN        VOID                      *ClearBits
165);
166
167///
168/// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
169/// controllers behind a PCI root bridge controller.
170///
171struct _EFI_PEI_PCI_CFG2_PPI {
172  EFI_PEI_PCI_CFG2_PPI_IO  Read;
173  EFI_PEI_PCI_CFG2_PPI_IO  Write;
174  EFI_PEI_PCI_CFG2_PPI_RW  Modify;
175  ///
176  /// The PCI bus segment which the specified functions will access.
177  ///
178  UINT16                  Segment;
179};
180
181
182extern EFI_GUID gEfiPciCfg2PpiGuid;
183
184#endif
185