1/** @file
2  Cache Maintenance Functions.
3
4  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
5  This program and the accompanying materials
6  are licensed and made available under the terms and conditions of the BSD License
7  which accompanies this distribution.  The full text of the license may be found at
8  http://opensource.org/licenses/bsd-license.php.
9
10  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15#include <Base.h>
16#include <Library/DebugLib.h>
17
18/**
19  Invalidates the entire instruction cache in cache coherency domain of the
20  calling CPU.
21
22**/
23VOID
24EFIAPI
25InvalidateInstructionCache (
26  VOID
27  )
28{
29}
30
31/**
32  Invalidates a range of instruction cache lines in the cache coherency domain
33  of the calling CPU.
34
35  Invalidates the instruction cache lines specified by Address and Length. If
36  Address is not aligned on a cache line boundary, then entire instruction
37  cache line containing Address is invalidated. If Address + Length is not
38  aligned on a cache line boundary, then the entire instruction cache line
39  containing Address + Length -1 is invalidated. This function may choose to
40  invalidate the entire instruction cache if that is more efficient than
41  invalidating the specified range. If Length is 0, then no instruction cache
42  lines are invalidated. Address is returned.
43
44  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
45
46  @param  Address The base address of the instruction cache lines to
47                  invalidate. If the CPU is in a physical addressing mode, then
48                  Address is a physical address. If the CPU is in a virtual
49                  addressing mode, then Address is a virtual address.
50
51  @param  Length  The number of bytes to invalidate from the instruction cache.
52
53  @return Address.
54
55**/
56VOID *
57EFIAPI
58InvalidateInstructionCacheRange (
59  IN      VOID                      *Address,
60  IN      UINTN                     Length
61  )
62{
63  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
64  return Address;
65}
66
67/**
68  Writes back and invalidates the entire data cache in cache coherency domain
69  of the calling CPU.
70
71  Writes back and invalidates the entire data cache in cache coherency domain
72  of the calling CPU. This function guarantees that all dirty cache lines are
73  written back to system memory, and also invalidates all the data cache lines
74  in the cache coherency domain of the calling CPU.
75
76**/
77VOID
78EFIAPI
79WriteBackInvalidateDataCache (
80  VOID
81  )
82{
83}
84
85/**
86  Writes back and invalidates a range of data cache lines in the cache
87  coherency domain of the calling CPU.
88
89  Writes Back and Invalidate the data cache lines specified by Address and
90  Length. If Address is not aligned on a cache line boundary, then entire data
91  cache line containing Address is written back and invalidated. If Address +
92  Length is not aligned on a cache line boundary, then the entire data cache
93  line containing Address + Length -1 is written back and invalidated. This
94  function may choose to write back and invalidate the entire data cache if
95  that is more efficient than writing back and invalidating the specified
96  range. If Length is 0, then no data cache lines are written back and
97  invalidated. Address is returned.
98
99  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
100
101  @param  Address The base address of the data cache lines to write back and
102                  invalidate. If the CPU is in a physical addressing mode, then
103                  Address is a physical address. If the CPU is in a virtual
104                  addressing mode, then Address is a virtual address.
105  @param  Length  The number of bytes to write back and invalidate from the
106                  data cache.
107
108  @return Address of cache invalidation.
109
110**/
111VOID *
112EFIAPI
113WriteBackInvalidateDataCacheRange (
114  IN      VOID                      *Address,
115  IN      UINTN                     Length
116  )
117{
118  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
119  return Address;
120}
121
122/**
123  Writes back the entire data cache in cache coherency domain of the calling
124  CPU.
125
126  Writes back the entire data cache in cache coherency domain of the calling
127  CPU. This function guarantees that all dirty cache lines are written back to
128  system memory. This function may also invalidate all the data cache lines in
129  the cache coherency domain of the calling CPU.
130
131**/
132VOID
133EFIAPI
134WriteBackDataCache (
135  VOID
136  )
137{
138}
139
140/**
141  Writes back a range of data cache lines in the cache coherency domain of the
142  calling CPU.
143
144  Writes back the data cache lines specified by Address and Length. If Address
145  is not aligned on a cache line boundary, then entire data cache line
146  containing Address is written back. If Address + Length is not aligned on a
147  cache line boundary, then the entire data cache line containing Address +
148  Length -1 is written back. This function may choose to write back the entire
149  data cache if that is more efficient than writing back the specified range.
150  If Length is 0, then no data cache lines are written back. This function may
151  also invalidate all the data cache lines in the specified range of the cache
152  coherency domain of the calling CPU. Address is returned.
153
154  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
155
156  @param  Address The base address of the data cache lines to write back. If
157                  the CPU is in a physical addressing mode, then Address is a
158                  physical address. If the CPU is in a virtual addressing
159                  mode, then Address is a virtual address.
160  @param  Length  The number of bytes to write back from the data cache.
161
162  @return Address of cache written in main memory.
163
164**/
165VOID *
166EFIAPI
167WriteBackDataCacheRange (
168  IN      VOID                      *Address,
169  IN      UINTN                     Length
170  )
171{
172  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
173  return Address;
174}
175
176/**
177  Invalidates the entire data cache in cache coherency domain of the calling
178  CPU.
179
180  Invalidates the entire data cache in cache coherency domain of the calling
181  CPU. This function must be used with care because dirty cache lines are not
182  written back to system memory. It is typically used for cache diagnostics. If
183  the CPU does not support invalidation of the entire data cache, then a write
184  back and invalidate operation should be performed on the entire data cache.
185
186**/
187VOID
188EFIAPI
189InvalidateDataCache (
190  VOID
191  )
192{
193}
194
195/**
196  Invalidates a range of data cache lines in the cache coherency domain of the
197  calling CPU.
198
199  Invalidates the data cache lines specified by Address and Length. If Address
200  is not aligned on a cache line boundary, then entire data cache line
201  containing Address is invalidated. If Address + Length is not aligned on a
202  cache line boundary, then the entire data cache line containing Address +
203  Length -1 is invalidated. This function must never invalidate any cache lines
204  outside the specified range. If Length is 0, then no data cache lines are
205  invalidated. Address is returned. This function must be used with care
206  because dirty cache lines are not written back to system memory. It is
207  typically used for cache diagnostics. If the CPU does not support
208  invalidation of a data cache range, then a write back and invalidate
209  operation should be performed on the data cache range.
210
211  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
212
213  @param  Address The base address of the data cache lines to invalidate. If
214                  the CPU is in a physical addressing mode, then Address is a
215                  physical address. If the CPU is in a virtual addressing mode,
216                  then Address is a virtual address.
217  @param  Length  The number of bytes to invalidate from the data cache.
218
219  @return Address.
220
221**/
222VOID *
223EFIAPI
224InvalidateDataCacheRange (
225  IN      VOID                      *Address,
226  IN      UINTN                     Length
227  )
228{
229  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
230  return Address;
231}
232