ArchitecturalMsr.h revision a03bb3d2a9f7486f3bd9539cd35561661c5b38a2
1/** @file 2 Architectural MSR Definitions. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1. 21 22 @par Specification Reference: 23 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 24 September 2016, Appendix A VMX Capability Reporting Facility, Section A.1. 25 26 @par Specification Reference: 27 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 28 September 2016, Appendix A VMX Capability Reporting Facility, Section A.6. 29 30**/ 31 32#ifndef __ARCHITECTURAL_MSR_H__ 33#define __ARCHITECTURAL_MSR_H__ 34 35/** 36 See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H). 37 38 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000) 39 @param EAX Lower 32-bits of MSR value. 40 @param EDX Upper 32-bits of MSR value. 41 42 <b>Example usage</b> 43 @code 44 UINT64 Msr; 45 46 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR); 47 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr); 48 @endcode 49 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM. 50**/ 51#define MSR_IA32_P5_MC_ADDR 0x00000000 52 53 54/** 55 See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H. 56 57 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001) 58 @param EAX Lower 32-bits of MSR value. 59 @param EDX Upper 32-bits of MSR value. 60 61 <b>Example usage</b> 62 @code 63 UINT64 Msr; 64 65 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE); 66 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr); 67 @endcode 68 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM. 69**/ 70#define MSR_IA32_P5_MC_TYPE 0x00000001 71 72 73/** 74 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced 75 at Display Family / Display Model 0F_03H. 76 77 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006) 78 @param EAX Lower 32-bits of MSR value. 79 @param EDX Upper 32-bits of MSR value. 80 81 <b>Example usage</b> 82 @code 83 UINT64 Msr; 84 85 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE); 86 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr); 87 @endcode 88 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM. 89**/ 90#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006 91 92 93/** 94 See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family / 95 Display Model 05_01H. 96 97 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010) 98 @param EAX Lower 32-bits of MSR value. 99 @param EDX Upper 32-bits of MSR value. 100 101 <b>Example usage</b> 102 @code 103 UINT64 Msr; 104 105 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER); 106 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr); 107 @endcode 108 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM. 109**/ 110#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010 111 112 113/** 114 Platform ID (RO) The operating system can use this MSR to determine "slot" 115 information for the processor and the proper microcode update to load. 116 Introduced at Display Family / Display Model 06_01H. 117 118 @param ECX MSR_IA32_PLATFORM_ID (0x00000017) 119 @param EAX Lower 32-bits of MSR value. 120 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 121 @param EDX Upper 32-bits of MSR value. 122 Described by the type MSR_IA32_PLATFORM_ID_REGISTER. 123 124 <b>Example usage</b> 125 @code 126 MSR_IA32_PLATFORM_ID_REGISTER Msr; 127 128 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); 129 @endcode 130 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM. 131**/ 132#define MSR_IA32_PLATFORM_ID 0x00000017 133 134/** 135 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID 136**/ 137typedef union { 138 /// 139 /// Individual bit fields 140 /// 141 struct { 142 UINT32 Reserved1:32; 143 UINT32 Reserved2:18; 144 /// 145 /// [Bits 52:50] Platform Id (RO) Contains information concerning the 146 /// intended platform for the processor. 147 /// 52 51 50 148 /// -- -- -- 149 /// 0 0 0 Processor Flag 0. 150 /// 0 0 1 Processor Flag 1 151 /// 0 1 0 Processor Flag 2 152 /// 0 1 1 Processor Flag 3 153 /// 1 0 0 Processor Flag 4 154 /// 1 0 1 Processor Flag 5 155 /// 1 1 0 Processor Flag 6 156 /// 1 1 1 Processor Flag 7 157 /// 158 UINT32 PlatformId:3; 159 UINT32 Reserved3:11; 160 } Bits; 161 /// 162 /// All bit fields as a 64-bit value 163 /// 164 UINT64 Uint64; 165} MSR_IA32_PLATFORM_ID_REGISTER; 166 167 168/** 169 06_01H. 170 171 @param ECX MSR_IA32_APIC_BASE (0x0000001B) 172 @param EAX Lower 32-bits of MSR value. 173 Described by the type MSR_IA32_APIC_BASE_REGISTER. 174 @param EDX Upper 32-bits of MSR value. 175 Described by the type MSR_IA32_APIC_BASE_REGISTER. 176 177 <b>Example usage</b> 178 @code 179 MSR_IA32_APIC_BASE_REGISTER Msr; 180 181 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); 182 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64); 183 @endcode 184 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM. 185**/ 186#define MSR_IA32_APIC_BASE 0x0000001B 187 188/** 189 MSR information returned for MSR index #MSR_IA32_APIC_BASE 190**/ 191typedef union { 192 /// 193 /// Individual bit fields 194 /// 195 struct { 196 UINT32 Reserved1:8; 197 /// 198 /// [Bit 8] BSP flag (R/W). 199 /// 200 UINT32 BSP:1; 201 UINT32 Reserved2:1; 202 /// 203 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display 204 /// Model 06_1AH. 205 /// 206 UINT32 EXTD:1; 207 /// 208 /// [Bit 11] APIC Global Enable (R/W). 209 /// 210 UINT32 EN:1; 211 /// 212 /// [Bits 31:12] APIC Base (R/W). 213 /// 214 UINT32 ApicBase:20; 215 /// 216 /// [Bits 63:32] APIC Base (R/W). 217 /// 218 UINT32 ApicBaseHi:32; 219 } Bits; 220 /// 221 /// All bit fields as a 64-bit value 222 /// 223 UINT64 Uint64; 224} MSR_IA32_APIC_BASE_REGISTER; 225 226 227/** 228 Control Features in Intel 64 Processor (R/W). If any one enumeration 229 condition for defined bit field holds. 230 231 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A) 232 @param EAX Lower 32-bits of MSR value. 233 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 234 @param EDX Upper 32-bits of MSR value. 235 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. 236 237 <b>Example usage</b> 238 @code 239 MSR_IA32_FEATURE_CONTROL_REGISTER Msr; 240 241 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL); 242 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64); 243 @endcode 244 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. 245**/ 246#define MSR_IA32_FEATURE_CONTROL 0x0000003A 247 248/** 249 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL 250**/ 251typedef union { 252 /// 253 /// Individual bit fields 254 /// 255 struct { 256 /// 257 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from 258 /// being written, writes to this bit will result in GP(0). Note: Once the 259 /// Lock bit is set, the contents of this register cannot be modified. 260 /// Therefore the lock bit must be set after configuring support for Intel 261 /// Virtualization Technology and prior to transferring control to an 262 /// option ROM or the OS. Hence, once the Lock bit is set, the entire 263 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD 264 /// is not deasserted. If any one enumeration condition for defined bit 265 /// field position greater than bit 0 holds. 266 /// 267 UINT32 Lock:1; 268 /// 269 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a 270 /// system executive to use VMX in conjunction with SMX to support 271 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only 272 /// when the CPUID function 1 returns VMX feature flag and SMX feature 273 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 && 274 /// CPUID.01H:ECX[6] = 1. 275 /// 276 UINT32 EnableVmxInsideSmx:1; 277 /// 278 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX 279 /// for system executive that do not require SMX. BIOS must set this bit 280 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit 281 /// 5). If CPUID.01H:ECX[5] = 1. 282 /// 283 UINT32 EnableVmxOutsideSmx:1; 284 UINT32 Reserved1:5; 285 /// 286 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit 287 /// in the field represents an enable control for a corresponding SENTER 288 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If 289 /// CPUID.01H:ECX[6] = 1. 290 /// 291 UINT32 SenterLocalFunctionEnables:7; 292 /// 293 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable 294 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit 295 /// 6] is set. If CPUID.01H:ECX[6] = 1. 296 /// 297 UINT32 SenterGlobalEnable:1; 298 UINT32 Reserved2:1; 299 /// 300 /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to 301 /// enable runtime reconfiguration of SGX Launch Control via 302 /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1. 303 /// 304 UINT32 SgxLaunchControlEnable:1; 305 /// 306 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX 307 /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1. 308 /// 309 UINT32 SgxEnable:1; 310 UINT32 Reserved3:1; 311 /// 312 /// [Bit 20] LMCE On (R/WL): When set, system software can program the 313 /// MSRs associated with LMCE to configure delivery of some machine check 314 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1. 315 /// 316 UINT32 LmceOn:1; 317 UINT32 Reserved4:11; 318 UINT32 Reserved5:32; 319 } Bits; 320 /// 321 /// All bit fields as a 32-bit value 322 /// 323 UINT32 Uint32; 324 /// 325 /// All bit fields as a 64-bit value 326 /// 327 UINT64 Uint64; 328} MSR_IA32_FEATURE_CONTROL_REGISTER; 329 330 331/** 332 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H, 333 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for 334 a logical processor. Reset value is Zero. A write to IA32_TSC will modify 335 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does 336 not affect the internal invariant TSC hardware. 337 338 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B) 339 @param EAX Lower 32-bits of MSR value. 340 @param EDX Upper 32-bits of MSR value. 341 342 <b>Example usage</b> 343 @code 344 UINT64 Msr; 345 346 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST); 347 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr); 348 @endcode 349 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM. 350**/ 351#define MSR_IA32_TSC_ADJUST 0x0000003B 352 353 354/** 355 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a 356 microcode update to be loaded into the processor. See Section 9.11.6, 357 "Microcode Update Loader." A processor may prevent writing to this MSR when 358 loading guest states on VM entries or saving guest states on VM exits. 359 Introduced at Display Family / Display Model 06_01H. 360 361 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079) 362 @param EAX Lower 32-bits of MSR value. 363 @param EDX Upper 32-bits of MSR value. 364 365 <b>Example usage</b> 366 @code 367 UINT64 Msr; 368 369 Msr = 0; 370 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr); 371 @endcode 372 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM. 373**/ 374#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 375 376 377/** 378 BIOS Update Signature (RO) Returns the microcode update signature following 379 the execution of CPUID.01H. A processor may prevent writing to this MSR when 380 loading guest states on VM entries or saving guest states on VM exits. 381 Introduced at Display Family / Display Model 06_01H. 382 383 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B) 384 @param EAX Lower 32-bits of MSR value. 385 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 386 @param EDX Upper 32-bits of MSR value. 387 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. 388 389 <b>Example usage</b> 390 @code 391 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr; 392 393 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID); 394 @endcode 395 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM. 396**/ 397#define MSR_IA32_BIOS_SIGN_ID 0x0000008B 398 399/** 400 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID 401**/ 402typedef union { 403 /// 404 /// Individual bit fields 405 /// 406 struct { 407 UINT32 Reserved:32; 408 /// 409 /// [Bits 63:32] Microcode update signature. This field contains the 410 /// signature of the currently loaded microcode update when read following 411 /// the execution of the CPUID instruction, function 1. It is required 412 /// that this register field be pre-loaded with zero prior to executing 413 /// the CPUID, function 1. If the field remains equal to zero, then there 414 /// is no microcode update loaded. Another nonzero value will be the 415 /// signature. 416 /// 417 UINT32 MicrocodeUpdateSignature:32; 418 } Bits; 419 /// 420 /// All bit fields as a 64-bit value 421 /// 422 UINT64 Uint64; 423} MSR_IA32_BIOS_SIGN_ID_REGISTER; 424 425 426/** 427 IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the 428 SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the 429 default value is the digest of Intel's signing key. Read permitted If 430 CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): 431 EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1. 432 433 @param ECX MSR_IA32_SGXLEPUBKEYHASHn 434 @param EAX Lower 32-bits of MSR value. 435 @param EDX Upper 32-bits of MSR value. 436 437 <b>Example usage</b> 438 @code 439 UINT64 Msr; 440 441 Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn); 442 AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr); 443 @endcode 444 @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. 445 MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. 446 MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. 447 MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM. 448 @{ 449**/ 450#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 451#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 452#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 453#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 454/// @} 455 456 457/** 458 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] = 459 1. 460 461 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B) 462 @param EAX Lower 32-bits of MSR value. 463 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. 464 @param EDX Upper 32-bits of MSR value. 465 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. 466 467 <b>Example usage</b> 468 @code 469 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr; 470 471 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL); 472 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64); 473 @endcode 474 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM. 475**/ 476#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B 477 478/** 479 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL 480**/ 481typedef union { 482 /// 483 /// Individual bit fields 484 /// 485 struct { 486 /// 487 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this 488 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment 489 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated 490 /// if the bit is 0. This bit is cleared when the logical processor is 491 /// reset. 492 /// 493 UINT32 Valid:1; 494 UINT32 Reserved1:1; 495 /// 496 /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the 497 /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs 498 /// unless bit 2 is 1 (the value of bit 0 is irrelevant). 499 /// 500 UINT32 BlockSmi:1; 501 UINT32 Reserved2:9; 502 /// 503 /// [Bits 31:12] MSEG Base (R/W). 504 /// 505 UINT32 MsegBase:20; 506 UINT32 Reserved3:32; 507 } Bits; 508 /// 509 /// All bit fields as a 32-bit value 510 /// 511 UINT32 Uint32; 512 /// 513 /// All bit fields as a 64-bit value 514 /// 515 UINT64 Uint64; 516} MSR_IA32_SMM_MONITOR_CTL_REGISTER; 517 518/** 519 MSEG header that is located at the physical address specified by the MsegBase 520 field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER. 521**/ 522typedef struct { 523 /// 524 /// Different processors may use different MSEG revision identifiers. These 525 /// identifiers enable software to avoid using an MSEG header formatted for 526 /// one processor on a processor that uses a different format. Software can 527 /// discover the MSEG revision identifier that a processor uses by reading 528 /// the VMX capability MSR IA32_VMX_MISC. 529 // 530 UINT32 MsegHeaderRevision; 531 /// 532 /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field 533 /// is the IA-32e mode SMM feature bit. It indicates whether the logical 534 /// processor will be in IA-32e mode after the STM is activated. 535 /// 536 UINT32 MonitorFeatures; 537 UINT32 GdtrLimit; 538 UINT32 GdtrBaseOffset; 539 UINT32 CsSelector; 540 UINT32 EipOffset; 541 UINT32 EspOffset; 542 UINT32 Cr3Offset; 543 /// 544 /// Pad header so total size is 2KB 545 /// 546 UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)]; 547} MSEG_HEADER; 548 549/// 550/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER 551/// 552#define STM_FEATURES_IA32E 0x1 553/// 554/// @} 555/// 556 557/** 558 Base address of the logical processor's SMRAM image (RO, SMM only). If 559 IA32_VMX_MISC[15]. 560 561 @param ECX MSR_IA32_SMBASE (0x0000009E) 562 @param EAX Lower 32-bits of MSR value. 563 @param EDX Upper 32-bits of MSR value. 564 565 <b>Example usage</b> 566 @code 567 UINT64 Msr; 568 569 Msr = AsmReadMsr64 (MSR_IA32_SMBASE); 570 @endcode 571 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM. 572**/ 573#define MSR_IA32_SMBASE 0x0000009E 574 575 576/** 577 General Performance Counters (R/W). 578 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n. 579 580 @param ECX MSR_IA32_PMCn 581 @param EAX Lower 32-bits of MSR value. 582 @param EDX Upper 32-bits of MSR value. 583 584 <b>Example usage</b> 585 @code 586 UINT64 Msr; 587 588 Msr = AsmReadMsr64 (MSR_IA32_PMC0); 589 AsmWriteMsr64 (MSR_IA32_PMC0, Msr); 590 @endcode 591 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. 592 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. 593 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. 594 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. 595 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. 596 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. 597 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. 598 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM. 599 @{ 600**/ 601#define MSR_IA32_PMC0 0x000000C1 602#define MSR_IA32_PMC1 0x000000C2 603#define MSR_IA32_PMC2 0x000000C3 604#define MSR_IA32_PMC3 0x000000C4 605#define MSR_IA32_PMC4 0x000000C5 606#define MSR_IA32_PMC5 0x000000C6 607#define MSR_IA32_PMC6 0x000000C7 608#define MSR_IA32_PMC7 0x000000C8 609/// @} 610 611 612/** 613 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1. 614 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative 615 to TSC freq.) when the logical processor is in C0. Cleared upon overflow / 616 wrap-around of IA32_APERF. 617 618 @param ECX MSR_IA32_MPERF (0x000000E7) 619 @param EAX Lower 32-bits of MSR value. 620 @param EDX Upper 32-bits of MSR value. 621 622 <b>Example usage</b> 623 @code 624 UINT64 Msr; 625 626 Msr = AsmReadMsr64 (MSR_IA32_MPERF); 627 AsmWriteMsr64 (MSR_IA32_MPERF, Msr); 628 @endcode 629 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM. 630**/ 631#define MSR_IA32_MPERF 0x000000E7 632 633 634/** 635 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 636 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at 637 the coordinated clock frequency, when the logical processor is in C0. 638 Cleared upon overflow / wrap-around of IA32_MPERF. 639 640 @param ECX MSR_IA32_APERF (0x000000E8) 641 @param EAX Lower 32-bits of MSR value. 642 @param EDX Upper 32-bits of MSR value. 643 644 <b>Example usage</b> 645 @code 646 UINT64 Msr; 647 648 Msr = AsmReadMsr64 (MSR_IA32_APERF); 649 AsmWriteMsr64 (MSR_IA32_APERF, Msr); 650 @endcode 651 @note MSR_IA32_APERF is defined as IA32_APERF in SDM. 652**/ 653#define MSR_IA32_APERF 0x000000E8 654 655 656/** 657 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.". 658 Introduced at Display Family / Display Model 06_01H. 659 660 @param ECX MSR_IA32_MTRRCAP (0x000000FE) 661 @param EAX Lower 32-bits of MSR value. 662 Described by the type MSR_IA32_MTRRCAP_REGISTER. 663 @param EDX Upper 32-bits of MSR value. 664 Described by the type MSR_IA32_MTRRCAP_REGISTER. 665 666 <b>Example usage</b> 667 @code 668 MSR_IA32_MTRRCAP_REGISTER Msr; 669 670 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP); 671 @endcode 672 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM. 673**/ 674#define MSR_IA32_MTRRCAP 0x000000FE 675 676/** 677 MSR information returned for MSR index #MSR_IA32_MTRRCAP 678**/ 679typedef union { 680 /// 681 /// Individual bit fields 682 /// 683 struct { 684 /// 685 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the 686 /// processor. 687 /// 688 UINT32 VCNT:8; 689 /// 690 /// [Bit 8] Fixed range MTRRs are supported when set. 691 /// 692 UINT32 FIX:1; 693 UINT32 Reserved1:1; 694 /// 695 /// [Bit 10] WC Supported when set. 696 /// 697 UINT32 WC:1; 698 /// 699 /// [Bit 11] SMRR Supported when set. 700 /// 701 UINT32 SMRR:1; 702 UINT32 Reserved2:20; 703 UINT32 Reserved3:32; 704 } Bits; 705 /// 706 /// All bit fields as a 32-bit value 707 /// 708 UINT32 Uint32; 709 /// 710 /// All bit fields as a 64-bit value 711 /// 712 UINT64 Uint64; 713} MSR_IA32_MTRRCAP_REGISTER; 714 715 716/** 717 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H. 718 719 @param ECX MSR_IA32_SYSENTER_CS (0x00000174) 720 @param EAX Lower 32-bits of MSR value. 721 Described by the type MSR_IA32_SYSENTER_CS_REGISTER. 722 @param EDX Upper 32-bits of MSR value. 723 Described by the type MSR_IA32_SYSENTER_CS_REGISTER. 724 725 <b>Example usage</b> 726 @code 727 MSR_IA32_SYSENTER_CS_REGISTER Msr; 728 729 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS); 730 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64); 731 @endcode 732 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM. 733**/ 734#define MSR_IA32_SYSENTER_CS 0x00000174 735 736/** 737 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS 738**/ 739typedef union { 740 /// 741 /// Individual bit fields 742 /// 743 struct { 744 /// 745 /// [Bits 15:0] CS Selector. 746 /// 747 UINT32 CS:16; 748 UINT32 Reserved1:16; 749 UINT32 Reserved2:32; 750 } Bits; 751 /// 752 /// All bit fields as a 32-bit value 753 /// 754 UINT32 Uint32; 755 /// 756 /// All bit fields as a 64-bit value 757 /// 758 UINT64 Uint64; 759} MSR_IA32_SYSENTER_CS_REGISTER; 760 761 762/** 763 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. 764 765 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175) 766 @param EAX Lower 32-bits of MSR value. 767 @param EDX Upper 32-bits of MSR value. 768 769 <b>Example usage</b> 770 @code 771 UINT64 Msr; 772 773 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP); 774 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr); 775 @endcode 776 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM. 777**/ 778#define MSR_IA32_SYSENTER_ESP 0x00000175 779 780 781/** 782 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. 783 784 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176) 785 @param EAX Lower 32-bits of MSR value. 786 @param EDX Upper 32-bits of MSR value. 787 788 <b>Example usage</b> 789 @code 790 UINT64 Msr; 791 792 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP); 793 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr); 794 @endcode 795 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM. 796**/ 797#define MSR_IA32_SYSENTER_EIP 0x00000176 798 799 800/** 801 Global Machine Check Capability (RO). Introduced at Display Family / Display 802 Model 06_01H. 803 804 @param ECX MSR_IA32_MCG_CAP (0x00000179) 805 @param EAX Lower 32-bits of MSR value. 806 Described by the type MSR_IA32_MCG_CAP_REGISTER. 807 @param EDX Upper 32-bits of MSR value. 808 Described by the type MSR_IA32_MCG_CAP_REGISTER. 809 810 <b>Example usage</b> 811 @code 812 MSR_IA32_MCG_CAP_REGISTER Msr; 813 814 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); 815 @endcode 816 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. 817**/ 818#define MSR_IA32_MCG_CAP 0x00000179 819 820/** 821 MSR information returned for MSR index #MSR_IA32_MCG_CAP 822**/ 823typedef union { 824 /// 825 /// Individual bit fields 826 /// 827 struct { 828 /// 829 /// [Bits 7:0] Count: Number of reporting banks. 830 /// 831 UINT32 Count:8; 832 /// 833 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set. 834 /// 835 UINT32 MCG_CTL_P:1; 836 /// 837 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present 838 /// if this bit is set. 839 /// 840 UINT32 MCG_EXT_P:1; 841 /// 842 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present. 843 /// Introduced at Display Family / Display Model 06_01H. 844 /// 845 UINT32 MCP_CMCI_P:1; 846 /// 847 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present 848 /// if this bit is set. 849 /// 850 UINT32 MCG_TES_P:1; 851 UINT32 Reserved1:4; 852 /// 853 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state 854 /// registers present. 855 /// 856 UINT32 MCG_EXT_CNT:8; 857 /// 858 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if 859 /// this bit is set. 860 /// 861 UINT32 MCG_SER_P:1; 862 UINT32 Reserved2:1; 863 /// 864 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform 865 /// firmware to be invoked when an error is detected so that it may 866 /// provide additional platform specific information in an ACPI format 867 /// "Generic Error Data Entry" that augments the data included in machine 868 /// check bank registers. Introduced at Display Family / Display Model 869 /// 06_3EH. 870 /// 871 UINT32 MCG_ELOG_P:1; 872 /// 873 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended 874 /// state in IA32_MCG_STATUS and associated MSR necessary to configure 875 /// Local Machine Check Exception (LMCE). Introduced at Display Family / 876 /// Display Model 06_3EH. 877 /// 878 UINT32 MCG_LMCE_P:1; 879 UINT32 Reserved3:4; 880 UINT32 Reserved4:32; 881 } Bits; 882 /// 883 /// All bit fields as a 32-bit value 884 /// 885 UINT32 Uint32; 886 /// 887 /// All bit fields as a 64-bit value 888 /// 889 UINT64 Uint64; 890} MSR_IA32_MCG_CAP_REGISTER; 891 892 893/** 894 Global Machine Check Status (R/W0). Introduced at Display Family / Display 895 Model 06_01H. 896 897 @param ECX MSR_IA32_MCG_STATUS (0x0000017A) 898 @param EAX Lower 32-bits of MSR value. 899 Described by the type MSR_IA32_MCG_STATUS_REGISTER. 900 @param EDX Upper 32-bits of MSR value. 901 Described by the type MSR_IA32_MCG_STATUS_REGISTER. 902 903 <b>Example usage</b> 904 @code 905 MSR_IA32_MCG_STATUS_REGISTER Msr; 906 907 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS); 908 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64); 909 @endcode 910 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM. 911**/ 912#define MSR_IA32_MCG_STATUS 0x0000017A 913 914/** 915 MSR information returned for MSR index #MSR_IA32_MCG_STATUS 916**/ 917typedef union { 918 /// 919 /// Individual bit fields 920 /// 921 struct { 922 /// 923 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display 924 /// Model 06_01H. 925 /// 926 UINT32 RIPV:1; 927 /// 928 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display 929 /// Model 06_01H. 930 /// 931 UINT32 EIPV:1; 932 /// 933 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family 934 /// / Display Model 06_01H. 935 /// 936 UINT32 MCIP:1; 937 /// 938 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1. 939 /// 940 UINT32 LMCE_S:1; 941 UINT32 Reserved1:28; 942 UINT32 Reserved2:32; 943 } Bits; 944 /// 945 /// All bit fields as a 32-bit value 946 /// 947 UINT32 Uint32; 948 /// 949 /// All bit fields as a 64-bit value 950 /// 951 UINT64 Uint64; 952} MSR_IA32_MCG_STATUS_REGISTER; 953 954 955/** 956 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1. 957 958 @param ECX MSR_IA32_MCG_CTL (0x0000017B) 959 @param EAX Lower 32-bits of MSR value. 960 @param EDX Upper 32-bits of MSR value. 961 962 <b>Example usage</b> 963 @code 964 UINT64 Msr; 965 966 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL); 967 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr); 968 @endcode 969 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM. 970**/ 971#define MSR_IA32_MCG_CTL 0x0000017B 972 973 974/** 975 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n. 976 977 @param ECX MSR_IA32_PERFEVTSELn 978 @param EAX Lower 32-bits of MSR value. 979 Described by the type MSR_IA32_PERFEVTSEL_REGISTER. 980 @param EDX Upper 32-bits of MSR value. 981 Described by the type MSR_IA32_PERFEVTSEL_REGISTER. 982 983 <b>Example usage</b> 984 @code 985 MSR_IA32_PERFEVTSEL_REGISTER Msr; 986 987 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0); 988 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64); 989 @endcode 990 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. 991 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. 992 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. 993 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM. 994 @{ 995**/ 996#define MSR_IA32_PERFEVTSEL0 0x00000186 997#define MSR_IA32_PERFEVTSEL1 0x00000187 998#define MSR_IA32_PERFEVTSEL2 0x00000188 999#define MSR_IA32_PERFEVTSEL3 0x00000189 1000/// @} 1001 1002/** 1003 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to 1004 #MSR_IA32_PERFEVTSEL3 1005**/ 1006typedef union { 1007 /// 1008 /// Individual bit fields 1009 /// 1010 struct { 1011 /// 1012 /// [Bits 7:0] Event Select: Selects a performance event logic unit. 1013 /// 1014 UINT32 EventSelect:8; 1015 /// 1016 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to 1017 /// detect on the selected event logic. 1018 /// 1019 UINT32 UMASK:8; 1020 /// 1021 /// [Bit 16] USR: Counts while in privilege level is not ring 0. 1022 /// 1023 UINT32 USR:1; 1024 /// 1025 /// [Bit 17] OS: Counts while in privilege level is ring 0. 1026 /// 1027 UINT32 OS:1; 1028 /// 1029 /// [Bit 18] Edge: Enables edge detection if set. 1030 /// 1031 UINT32 E:1; 1032 /// 1033 /// [Bit 19] PC: enables pin control. 1034 /// 1035 UINT32 PC:1; 1036 /// 1037 /// [Bit 20] INT: enables interrupt on counter overflow. 1038 /// 1039 UINT32 INT:1; 1040 /// 1041 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated 1042 /// event conditions occurring across all logical processors sharing a 1043 /// processor core. When set to 0, the counter only increments the 1044 /// associated event conditions occurring in the logical processor which 1045 /// programmed the MSR. 1046 /// 1047 UINT32 ANY:1; 1048 /// 1049 /// [Bit 22] EN: enables the corresponding performance counter to commence 1050 /// counting when this bit is set. 1051 /// 1052 UINT32 EN:1; 1053 /// 1054 /// [Bit 23] INV: invert the CMASK. 1055 /// 1056 UINT32 INV:1; 1057 /// 1058 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding 1059 /// performance counter increments each cycle if the event count is 1060 /// greater than or equal to the CMASK. 1061 /// 1062 UINT32 CMASK:8; 1063 UINT32 Reserved:32; 1064 } Bits; 1065 /// 1066 /// All bit fields as a 32-bit value 1067 /// 1068 UINT32 Uint32; 1069 /// 1070 /// All bit fields as a 64-bit value 1071 /// 1072 UINT64 Uint64; 1073} MSR_IA32_PERFEVTSEL_REGISTER; 1074 1075 1076/** 1077 Current performance state(P-State) operating point (RO). Introduced at 1078 Display Family / Display Model 0F_03H. 1079 1080 @param ECX MSR_IA32_PERF_STATUS (0x00000198) 1081 @param EAX Lower 32-bits of MSR value. 1082 Described by the type MSR_IA32_PERF_STATUS_REGISTER. 1083 @param EDX Upper 32-bits of MSR value. 1084 Described by the type MSR_IA32_PERF_STATUS_REGISTER. 1085 1086 <b>Example usage</b> 1087 @code 1088 MSR_IA32_PERF_STATUS_REGISTER Msr; 1089 1090 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS); 1091 @endcode 1092 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM. 1093**/ 1094#define MSR_IA32_PERF_STATUS 0x00000198 1095 1096/** 1097 MSR information returned for MSR index #MSR_IA32_PERF_STATUS 1098**/ 1099typedef union { 1100 /// 1101 /// Individual bit fields 1102 /// 1103 struct { 1104 /// 1105 /// [Bits 15:0] Current performance State Value. 1106 /// 1107 UINT32 State:16; 1108 UINT32 Reserved1:16; 1109 UINT32 Reserved2:32; 1110 } Bits; 1111 /// 1112 /// All bit fields as a 32-bit value 1113 /// 1114 UINT32 Uint32; 1115 /// 1116 /// All bit fields as a 64-bit value 1117 /// 1118 UINT64 Uint64; 1119} MSR_IA32_PERF_STATUS_REGISTER; 1120 1121 1122/** 1123 (R/W). Introduced at Display Family / Display Model 0F_03H. 1124 1125 @param ECX MSR_IA32_PERF_CTL (0x00000199) 1126 @param EAX Lower 32-bits of MSR value. 1127 Described by the type MSR_IA32_PERF_CTL_REGISTER. 1128 @param EDX Upper 32-bits of MSR value. 1129 Described by the type MSR_IA32_PERF_CTL_REGISTER. 1130 1131 <b>Example usage</b> 1132 @code 1133 MSR_IA32_PERF_CTL_REGISTER Msr; 1134 1135 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL); 1136 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64); 1137 @endcode 1138 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM. 1139**/ 1140#define MSR_IA32_PERF_CTL 0x00000199 1141 1142/** 1143 MSR information returned for MSR index #MSR_IA32_PERF_CTL 1144**/ 1145typedef union { 1146 /// 1147 /// Individual bit fields 1148 /// 1149 struct { 1150 /// 1151 /// [Bits 15:0] Target performance State Value. 1152 /// 1153 UINT32 TargetState:16; 1154 UINT32 Reserved1:16; 1155 /// 1156 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH 1157 /// (Mobile only). 1158 /// 1159 UINT32 IDA:1; 1160 UINT32 Reserved2:31; 1161 } Bits; 1162 /// 1163 /// All bit fields as a 64-bit value 1164 /// 1165 UINT64 Uint64; 1166} MSR_IA32_PERF_CTL_REGISTER; 1167 1168 1169/** 1170 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled 1171 Clock Modulation.". If CPUID.01H:EDX[22] = 1. 1172 1173 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A) 1174 @param EAX Lower 32-bits of MSR value. 1175 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. 1176 @param EDX Upper 32-bits of MSR value. 1177 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. 1178 1179 <b>Example usage</b> 1180 @code 1181 MSR_IA32_CLOCK_MODULATION_REGISTER Msr; 1182 1183 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION); 1184 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64); 1185 @endcode 1186 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM. 1187**/ 1188#define MSR_IA32_CLOCK_MODULATION 0x0000019A 1189 1190/** 1191 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION 1192**/ 1193typedef union { 1194 /// 1195 /// Individual bit fields 1196 /// 1197 struct { 1198 /// 1199 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If 1200 /// CPUID.06H:EAX[5] = 1. 1201 /// 1202 UINT32 ExtendedOnDemandClockModulationDutyCycle:1; 1203 /// 1204 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded 1205 /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1. 1206 /// 1207 UINT32 OnDemandClockModulationDutyCycle:3; 1208 /// 1209 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation. 1210 /// If CPUID.01H:EDX[22] = 1. 1211 /// 1212 UINT32 OnDemandClockModulationEnable:1; 1213 UINT32 Reserved1:27; 1214 UINT32 Reserved2:32; 1215 } Bits; 1216 /// 1217 /// All bit fields as a 32-bit value 1218 /// 1219 UINT32 Uint32; 1220 /// 1221 /// All bit fields as a 64-bit value 1222 /// 1223 UINT64 Uint64; 1224} MSR_IA32_CLOCK_MODULATION_REGISTER; 1225 1226 1227/** 1228 Thermal Interrupt Control (R/W) Enables and disables the generation of an 1229 interrupt on temperature transitions detected with the processor's thermal 1230 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.". 1231 If CPUID.01H:EDX[22] = 1 1232 1233 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B) 1234 @param EAX Lower 32-bits of MSR value. 1235 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. 1236 @param EDX Upper 32-bits of MSR value. 1237 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. 1238 1239 <b>Example usage</b> 1240 @code 1241 MSR_IA32_THERM_INTERRUPT_REGISTER Msr; 1242 1243 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT); 1244 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64); 1245 @endcode 1246 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM. 1247**/ 1248#define MSR_IA32_THERM_INTERRUPT 0x0000019B 1249 1250/** 1251 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT 1252**/ 1253typedef union { 1254 /// 1255 /// Individual bit fields 1256 /// 1257 struct { 1258 /// 1259 /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1260 /// 1261 UINT32 HighTempEnable:1; 1262 /// 1263 /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1264 /// 1265 UINT32 LowTempEnable:1; 1266 /// 1267 /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1268 /// 1269 UINT32 PROCHOT_Enable:1; 1270 /// 1271 /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1272 /// 1273 UINT32 FORCEPR_Enable:1; 1274 /// 1275 /// [Bit 4] Critical Temperature Interrupt Enable. 1276 /// If CPUID.01H:EDX[22] = 1. 1277 /// 1278 UINT32 CriticalTempEnable:1; 1279 UINT32 Reserved1:3; 1280 /// 1281 /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1. 1282 /// 1283 UINT32 Threshold1:7; 1284 /// 1285 /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1286 /// 1287 UINT32 Threshold1Enable:1; 1288 /// 1289 /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1. 1290 /// 1291 UINT32 Threshold2:7; 1292 /// 1293 /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1. 1294 /// 1295 UINT32 Threshold2Enable:1; 1296 /// 1297 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1. 1298 /// 1299 UINT32 PowerLimitNotificationEnable:1; 1300 UINT32 Reserved2:7; 1301 UINT32 Reserved3:32; 1302 } Bits; 1303 /// 1304 /// All bit fields as a 32-bit value 1305 /// 1306 UINT32 Uint32; 1307 /// 1308 /// All bit fields as a 64-bit value 1309 /// 1310 UINT64 Uint64; 1311} MSR_IA32_THERM_INTERRUPT_REGISTER; 1312 1313 1314/** 1315 Thermal Status Information (RO) Contains status information about the 1316 processor's thermal sensor and automatic thermal monitoring facilities. See 1317 Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1. 1318 1319 @param ECX MSR_IA32_THERM_STATUS (0x0000019C) 1320 @param EAX Lower 32-bits of MSR value. 1321 Described by the type MSR_IA32_THERM_STATUS_REGISTER. 1322 @param EDX Upper 32-bits of MSR value. 1323 Described by the type MSR_IA32_THERM_STATUS_REGISTER. 1324 1325 <b>Example usage</b> 1326 @code 1327 MSR_IA32_THERM_STATUS_REGISTER Msr; 1328 1329 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS); 1330 @endcode 1331 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM. 1332**/ 1333#define MSR_IA32_THERM_STATUS 0x0000019C 1334 1335/** 1336 MSR information returned for MSR index #MSR_IA32_THERM_STATUS 1337**/ 1338typedef union { 1339 /// 1340 /// Individual bit fields 1341 /// 1342 struct { 1343 /// 1344 /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1. 1345 /// 1346 UINT32 ThermalStatus:1; 1347 /// 1348 /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1. 1349 /// 1350 UINT32 ThermalStatusLog:1; 1351 /// 1352 /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1. 1353 /// 1354 UINT32 PROCHOT_FORCEPR_Event:1; 1355 /// 1356 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1. 1357 /// 1358 UINT32 PROCHOT_FORCEPR_Log:1; 1359 /// 1360 /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1. 1361 /// 1362 UINT32 CriticalTempStatus:1; 1363 /// 1364 /// [Bit 5] Critical Temperature Status log (R/WC0). 1365 /// If CPUID.01H:EDX[22] = 1. 1366 /// 1367 UINT32 CriticalTempStatusLog:1; 1368 /// 1369 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1. 1370 /// 1371 UINT32 ThermalThreshold1Status:1; 1372 /// 1373 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1. 1374 /// 1375 UINT32 ThermalThreshold1Log:1; 1376 /// 1377 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1. 1378 /// 1379 UINT32 ThermalThreshold2Status:1; 1380 /// 1381 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1. 1382 /// 1383 UINT32 ThermalThreshold2Log:1; 1384 /// 1385 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1. 1386 /// 1387 UINT32 PowerLimitStatus:1; 1388 /// 1389 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1. 1390 /// 1391 UINT32 PowerLimitLog:1; 1392 /// 1393 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1. 1394 /// 1395 UINT32 CurrentLimitStatus:1; 1396 /// 1397 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. 1398 /// 1399 UINT32 CurrentLimitLog:1; 1400 /// 1401 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1. 1402 /// 1403 UINT32 CrossDomainLimitStatus:1; 1404 /// 1405 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. 1406 /// 1407 UINT32 CrossDomainLimitLog:1; 1408 /// 1409 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1. 1410 /// 1411 UINT32 DigitalReadout:7; 1412 UINT32 Reserved1:4; 1413 /// 1414 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] = 1415 /// 1. 1416 /// 1417 UINT32 ResolutionInDegreesCelsius:4; 1418 /// 1419 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1. 1420 /// 1421 UINT32 ReadingValid:1; 1422 UINT32 Reserved2:32; 1423 } Bits; 1424 /// 1425 /// All bit fields as a 32-bit value 1426 /// 1427 UINT32 Uint32; 1428 /// 1429 /// All bit fields as a 64-bit value 1430 /// 1431 UINT64 Uint64; 1432} MSR_IA32_THERM_STATUS_REGISTER; 1433 1434 1435/** 1436 Enable Misc. Processor Features (R/W) Allows a variety of processor 1437 functions to be enabled and disabled. 1438 1439 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0) 1440 @param EAX Lower 32-bits of MSR value. 1441 Described by the type MSR_IA32_MISC_ENABLE_REGISTER. 1442 @param EDX Upper 32-bits of MSR value. 1443 Described by the type MSR_IA32_MISC_ENABLE_REGISTER. 1444 1445 <b>Example usage</b> 1446 @code 1447 MSR_IA32_MISC_ENABLE_REGISTER Msr; 1448 1449 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); 1450 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64); 1451 @endcode 1452 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 1453**/ 1454#define MSR_IA32_MISC_ENABLE 0x000001A0 1455 1456/** 1457 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE 1458**/ 1459typedef union { 1460 /// 1461 /// Individual bit fields 1462 /// 1463 struct { 1464 /// 1465 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for 1466 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings 1467 /// are disabled. Introduced at Display Family / Display Model 0F_0H. 1468 /// 1469 UINT32 FastStrings:1; 1470 UINT32 Reserved1:2; 1471 /// 1472 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting 1473 /// this bit enables the thermal control circuit (TCC) portion of the 1474 /// Intel Thermal Monitor feature. This allows the processor to 1475 /// automatically reduce power consumption in response to TCC activation. 1476 /// 0 = Disabled. Note: In some products clearing this bit might be 1477 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive 1478 /// thermal throttling will still be activated. The default value of this 1479 /// field varies with product. See respective tables where default value is 1480 /// listed. Introduced at Display Family / Display Model 0F_0H. 1481 /// 1482 UINT32 AutomaticThermalControlCircuit:1; 1483 UINT32 Reserved2:3; 1484 /// 1485 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance 1486 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at 1487 /// Display Family / Display Model 0F_0H. 1488 /// 1489 UINT32 PerformanceMonitoring:1; 1490 UINT32 Reserved3:3; 1491 /// 1492 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't 1493 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at 1494 /// Display Family / Display Model 0F_0H. 1495 /// 1496 UINT32 BTS:1; 1497 /// 1498 /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 = 1499 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display 1500 /// Family / Display Model 06_0FH. 1501 /// 1502 UINT32 PEBS:1; 1503 UINT32 Reserved4:3; 1504 /// 1505 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced 1506 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep 1507 /// Technology enabled. If CPUID.01H: ECX[7] =1. 1508 /// 1509 UINT32 EIST:1; 1510 UINT32 Reserved5:1; 1511 /// 1512 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the 1513 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This 1514 /// indicates that MONITOR/MWAIT are not supported. Software attempts to 1515 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit 1516 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit 1517 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit 1518 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it 1519 /// in the default state. Writing this bit when the SSE3 feature flag is 1520 /// set to 0 may generate a #GP exception. Introduced at Display Family / 1521 /// Display Model 0F_03H. 1522 /// 1523 UINT32 MONITOR:1; 1524 UINT32 Reserved6:3; 1525 /// 1526 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H 1527 /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup 1528 /// question that allows users to specify when the installed OS does not 1529 /// support CPUID functions greater than 2. Before setting this bit, BIOS 1530 /// must execute the CPUID.0H and examine the maximum value returned in 1531 /// EAX[7:0]. If the maximum value is greater than 2, this bit is 1532 /// supported. Otherwise, this bit is not supported. Setting this bit when 1533 /// the maximum value is not greater than 2 may generate a #GP exception. 1534 /// Setting this bit may cause unexpected behavior in software that 1535 /// depends on the availability of CPUID leaves greater than 2. Introduced 1536 /// at Display Family / Display Model 0F_03H. 1537 /// 1538 UINT32 LimitCpuidMaxval:1; 1539 /// 1540 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are 1541 /// disabled. xTPR messages are optional messages that allow the processor 1542 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1. 1543 /// 1544 UINT32 xTPR_Message_Disable:1; 1545 UINT32 Reserved7:8; 1546 UINT32 Reserved8:2; 1547 /// 1548 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit 1549 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will 1550 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the 1551 /// Execute Disable Bit feature (if available) allows the OS to enable PAE 1552 /// paging and take advantage of data only pages. BIOS must not alter the 1553 /// contents of this bit location, if XD bit is not supported. Writing 1554 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may 1555 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1. 1556 /// 1557 UINT32 XD:1; 1558 UINT32 Reserved9:29; 1559 } Bits; 1560 /// 1561 /// All bit fields as a 64-bit value 1562 /// 1563 UINT64 Uint64; 1564} MSR_IA32_MISC_ENABLE_REGISTER; 1565 1566 1567/** 1568 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1. 1569 1570 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0) 1571 @param EAX Lower 32-bits of MSR value. 1572 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. 1573 @param EDX Upper 32-bits of MSR value. 1574 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. 1575 1576 <b>Example usage</b> 1577 @code 1578 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr; 1579 1580 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS); 1581 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64); 1582 @endcode 1583 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM. 1584**/ 1585#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0 1586 1587/** 1588 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS 1589**/ 1590typedef union { 1591 /// 1592 /// Individual bit fields 1593 /// 1594 struct { 1595 /// 1596 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest 1597 /// performance. 15 indicates preference to maximize energy saving. 1598 /// 1599 UINT32 PowerPolicyPreference:4; 1600 UINT32 Reserved1:28; 1601 UINT32 Reserved2:32; 1602 } Bits; 1603 /// 1604 /// All bit fields as a 32-bit value 1605 /// 1606 UINT32 Uint32; 1607 /// 1608 /// All bit fields as a 64-bit value 1609 /// 1610 UINT64 Uint64; 1611} MSR_IA32_ENERGY_PERF_BIAS_REGISTER; 1612 1613 1614/** 1615 Package Thermal Status Information (RO) Contains status information about 1616 the package's thermal sensor. See Section 14.8, "Package Level Thermal 1617 Management.". If CPUID.06H: EAX[6] = 1. 1618 1619 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1) 1620 @param EAX Lower 32-bits of MSR value. 1621 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. 1622 @param EDX Upper 32-bits of MSR value. 1623 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. 1624 1625 <b>Example usage</b> 1626 @code 1627 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr; 1628 1629 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS); 1630 @endcode 1631 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM. 1632**/ 1633#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1 1634 1635/** 1636 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS 1637**/ 1638typedef union { 1639 /// 1640 /// Individual bit fields 1641 /// 1642 struct { 1643 /// 1644 /// [Bit 0] Pkg Thermal Status (RO):. 1645 /// 1646 UINT32 ThermalStatus:1; 1647 /// 1648 /// [Bit 1] Pkg Thermal Status Log (R/W):. 1649 /// 1650 UINT32 ThermalStatusLog:1; 1651 /// 1652 /// [Bit 2] Pkg PROCHOT # event (RO). 1653 /// 1654 UINT32 PROCHOT_Event:1; 1655 /// 1656 /// [Bit 3] Pkg PROCHOT # log (R/WC0). 1657 /// 1658 UINT32 PROCHOT_Log:1; 1659 /// 1660 /// [Bit 4] Pkg Critical Temperature Status (RO). 1661 /// 1662 UINT32 CriticalTempStatus:1; 1663 /// 1664 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0). 1665 /// 1666 UINT32 CriticalTempStatusLog:1; 1667 /// 1668 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO). 1669 /// 1670 UINT32 ThermalThreshold1Status:1; 1671 /// 1672 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0). 1673 /// 1674 UINT32 ThermalThreshold1Log:1; 1675 /// 1676 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO). 1677 /// 1678 UINT32 ThermalThreshold2Status:1; 1679 /// 1680 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0). 1681 /// 1682 UINT32 ThermalThreshold2Log:1; 1683 /// 1684 /// [Bit 10] Pkg Power Limitation Status (RO). 1685 /// 1686 UINT32 PowerLimitStatus:1; 1687 /// 1688 /// [Bit 11] Pkg Power Limitation log (R/WC0). 1689 /// 1690 UINT32 PowerLimitLog:1; 1691 UINT32 Reserved1:4; 1692 /// 1693 /// [Bits 22:16] Pkg Digital Readout (RO). 1694 /// 1695 UINT32 DigitalReadout:7; 1696 UINT32 Reserved2:9; 1697 UINT32 Reserved3:32; 1698 } Bits; 1699 /// 1700 /// All bit fields as a 32-bit value 1701 /// 1702 UINT32 Uint32; 1703 /// 1704 /// All bit fields as a 64-bit value 1705 /// 1706 UINT64 Uint64; 1707} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER; 1708 1709 1710/** 1711 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of 1712 an interrupt on temperature transitions detected with the package's thermal 1713 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H: 1714 EAX[6] = 1. 1715 1716 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2) 1717 @param EAX Lower 32-bits of MSR value. 1718 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. 1719 @param EDX Upper 32-bits of MSR value. 1720 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. 1721 1722 <b>Example usage</b> 1723 @code 1724 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr; 1725 1726 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT); 1727 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64); 1728 @endcode 1729 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM. 1730**/ 1731#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2 1732 1733/** 1734 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT 1735**/ 1736typedef union { 1737 /// 1738 /// Individual bit fields 1739 /// 1740 struct { 1741 /// 1742 /// [Bit 0] Pkg High-Temperature Interrupt Enable. 1743 /// 1744 UINT32 HighTempEnable:1; 1745 /// 1746 /// [Bit 1] Pkg Low-Temperature Interrupt Enable. 1747 /// 1748 UINT32 LowTempEnable:1; 1749 /// 1750 /// [Bit 2] Pkg PROCHOT# Interrupt Enable. 1751 /// 1752 UINT32 PROCHOT_Enable:1; 1753 UINT32 Reserved1:1; 1754 /// 1755 /// [Bit 4] Pkg Overheat Interrupt Enable. 1756 /// 1757 UINT32 OverheatEnable:1; 1758 UINT32 Reserved2:3; 1759 /// 1760 /// [Bits 14:8] Pkg Threshold #1 Value. 1761 /// 1762 UINT32 Threshold1:7; 1763 /// 1764 /// [Bit 15] Pkg Threshold #1 Interrupt Enable. 1765 /// 1766 UINT32 Threshold1Enable:1; 1767 /// 1768 /// [Bits 22:16] Pkg Threshold #2 Value. 1769 /// 1770 UINT32 Threshold2:7; 1771 /// 1772 /// [Bit 23] Pkg Threshold #2 Interrupt Enable. 1773 /// 1774 UINT32 Threshold2Enable:1; 1775 /// 1776 /// [Bit 24] Pkg Power Limit Notification Enable. 1777 /// 1778 UINT32 PowerLimitNotificationEnable:1; 1779 UINT32 Reserved3:7; 1780 UINT32 Reserved4:32; 1781 } Bits; 1782 /// 1783 /// All bit fields as a 32-bit value 1784 /// 1785 UINT32 Uint32; 1786 /// 1787 /// All bit fields as a 64-bit value 1788 /// 1789 UINT64 Uint64; 1790} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER; 1791 1792 1793/** 1794 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display 1795 Model 06_0EH. 1796 1797 @param ECX MSR_IA32_DEBUGCTL (0x000001D9) 1798 @param EAX Lower 32-bits of MSR value. 1799 Described by the type MSR_IA32_DEBUGCTL_REGISTER. 1800 @param EDX Upper 32-bits of MSR value. 1801 Described by the type MSR_IA32_DEBUGCTL_REGISTER. 1802 1803 <b>Example usage</b> 1804 @code 1805 MSR_IA32_DEBUGCTL_REGISTER Msr; 1806 1807 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL); 1808 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64); 1809 @endcode 1810 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM. 1811**/ 1812#define MSR_IA32_DEBUGCTL 0x000001D9 1813 1814/** 1815 MSR information returned for MSR index #MSR_IA32_DEBUGCTL 1816**/ 1817typedef union { 1818 /// 1819 /// Individual bit fields 1820 /// 1821 struct { 1822 /// 1823 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a 1824 /// running trace of the most recent branches taken by the processor in 1825 /// the LBR stack. Introduced at Display Family / Display Model 06_01H. 1826 /// 1827 UINT32 LBR:1; 1828 /// 1829 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat 1830 /// EFLAGS.TF as single-step on branches instead of single-step on 1831 /// instructions. Introduced at Display Family / Display Model 06_01H. 1832 /// 1833 UINT32 BTF:1; 1834 UINT32 Reserved1:4; 1835 /// 1836 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be 1837 /// sent. Introduced at Display Family / Display Model 06_0EH. 1838 /// 1839 UINT32 TR:1; 1840 /// 1841 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to 1842 /// be logged in a BTS buffer. Introduced at Display Family / Display 1843 /// Model 06_0EH. 1844 /// 1845 UINT32 BTS:1; 1846 /// 1847 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular 1848 /// fashion. When this bit is set, an interrupt is generated by the BTS 1849 /// facility when the BTS buffer is full. Introduced at Display Family / 1850 /// Display Model 06_0EH. 1851 /// 1852 UINT32 BTINT:1; 1853 /// 1854 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. 1855 /// Introduced at Display Family / Display Model 06_0FH. 1856 /// 1857 UINT32 BTS_OFF_OS:1; 1858 /// 1859 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. 1860 /// Introduced at Display Family / Display Model 06_0FH. 1861 /// 1862 UINT32 BTS_OFF_USR:1; 1863 /// 1864 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a 1865 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. 1866 /// 1867 UINT32 FREEZE_LBRS_ON_PMI:1; 1868 /// 1869 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the 1870 /// global counter control MSR are frozen (address 38FH) on a PMI request. 1871 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. 1872 /// 1873 UINT32 FREEZE_PERFMON_ON_PMI:1; 1874 /// 1875 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to 1876 /// receive and generate PMI on behalf of the uncore. Introduced at 1877 /// Display Family / Display Model 06_1AH. 1878 /// 1879 UINT32 ENABLE_UNCORE_PMI:1; 1880 /// 1881 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace 1882 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1. 1883 /// 1884 UINT32 FREEZE_WHILE_SMM:1; 1885 /// 1886 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If 1887 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1). 1888 /// 1889 UINT32 RTM_DEBUG:1; 1890 UINT32 Reserved2:16; 1891 UINT32 Reserved3:32; 1892 } Bits; 1893 /// 1894 /// All bit fields as a 32-bit value 1895 /// 1896 UINT32 Uint32; 1897 /// 1898 /// All bit fields as a 64-bit value 1899 /// 1900 UINT64 Uint64; 1901} MSR_IA32_DEBUGCTL_REGISTER; 1902 1903 1904/** 1905 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range. 1906 If IA32_MTRRCAP.SMRR[11] = 1. 1907 1908 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2) 1909 @param EAX Lower 32-bits of MSR value. 1910 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. 1911 @param EDX Upper 32-bits of MSR value. 1912 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. 1913 1914 <b>Example usage</b> 1915 @code 1916 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr; 1917 1918 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE); 1919 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64); 1920 @endcode 1921 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM. 1922**/ 1923#define MSR_IA32_SMRR_PHYSBASE 0x000001F2 1924 1925/** 1926 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE 1927**/ 1928typedef union { 1929 /// 1930 /// Individual bit fields 1931 /// 1932 struct { 1933 /// 1934 /// [Bits 7:0] Type. Specifies memory type of the range. 1935 /// 1936 UINT32 Type:8; 1937 UINT32 Reserved1:4; 1938 /// 1939 /// [Bits 31:12] PhysBase. SMRR physical Base Address. 1940 /// 1941 UINT32 PhysBase:20; 1942 UINT32 Reserved2:32; 1943 } Bits; 1944 /// 1945 /// All bit fields as a 32-bit value 1946 /// 1947 UINT32 Uint32; 1948 /// 1949 /// All bit fields as a 64-bit value 1950 /// 1951 UINT64 Uint64; 1952} MSR_IA32_SMRR_PHYSBASE_REGISTER; 1953 1954 1955/** 1956 SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If 1957 IA32_MTRRCAP[SMRR] = 1. 1958 1959 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3) 1960 @param EAX Lower 32-bits of MSR value. 1961 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. 1962 @param EDX Upper 32-bits of MSR value. 1963 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. 1964 1965 <b>Example usage</b> 1966 @code 1967 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr; 1968 1969 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK); 1970 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64); 1971 @endcode 1972 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM. 1973**/ 1974#define MSR_IA32_SMRR_PHYSMASK 0x000001F3 1975 1976/** 1977 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK 1978**/ 1979typedef union { 1980 /// 1981 /// Individual bit fields 1982 /// 1983 struct { 1984 UINT32 Reserved1:11; 1985 /// 1986 /// [Bit 11] Valid Enable range mask. 1987 /// 1988 UINT32 Valid:1; 1989 /// 1990 /// [Bits 31:12] PhysMask SMRR address range mask. 1991 /// 1992 UINT32 PhysMask:20; 1993 UINT32 Reserved2:32; 1994 } Bits; 1995 /// 1996 /// All bit fields as a 32-bit value 1997 /// 1998 UINT32 Uint32; 1999 /// 2000 /// All bit fields as a 64-bit value 2001 /// 2002 UINT64 Uint64; 2003} MSR_IA32_SMRR_PHYSMASK_REGISTER; 2004 2005 2006/** 2007 DCA Capability (R). If CPUID.01H: ECX[18] = 1. 2008 2009 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8) 2010 @param EAX Lower 32-bits of MSR value. 2011 @param EDX Upper 32-bits of MSR value. 2012 2013 <b>Example usage</b> 2014 @code 2015 UINT64 Msr; 2016 2017 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP); 2018 @endcode 2019 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM. 2020**/ 2021#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8 2022 2023 2024/** 2025 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1. 2026 2027 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9) 2028 @param EAX Lower 32-bits of MSR value. 2029 @param EDX Upper 32-bits of MSR value. 2030 2031 <b>Example usage</b> 2032 @code 2033 UINT64 Msr; 2034 2035 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP); 2036 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr); 2037 @endcode 2038 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM. 2039**/ 2040#define MSR_IA32_CPU_DCA_CAP 0x000001F9 2041 2042 2043/** 2044 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1. 2045 2046 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA) 2047 @param EAX Lower 32-bits of MSR value. 2048 Described by the type MSR_IA32_DCA_0_CAP_REGISTER. 2049 @param EDX Upper 32-bits of MSR value. 2050 Described by the type MSR_IA32_DCA_0_CAP_REGISTER. 2051 2052 <b>Example usage</b> 2053 @code 2054 MSR_IA32_DCA_0_CAP_REGISTER Msr; 2055 2056 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP); 2057 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64); 2058 @endcode 2059 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM. 2060**/ 2061#define MSR_IA32_DCA_0_CAP 0x000001FA 2062 2063/** 2064 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP 2065**/ 2066typedef union { 2067 /// 2068 /// Individual bit fields 2069 /// 2070 struct { 2071 /// 2072 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no 2073 /// defeatures are set. 2074 /// 2075 UINT32 DCA_ACTIVE:1; 2076 /// 2077 /// [Bits 2:1] TRANSACTION. 2078 /// 2079 UINT32 TRANSACTION:2; 2080 /// 2081 /// [Bits 6:3] DCA_TYPE. 2082 /// 2083 UINT32 DCA_TYPE:4; 2084 /// 2085 /// [Bits 10:7] DCA_QUEUE_SIZE. 2086 /// 2087 UINT32 DCA_QUEUE_SIZE:4; 2088 UINT32 Reserved1:2; 2089 /// 2090 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW 2091 /// side-effect. 2092 /// 2093 UINT32 DCA_DELAY:4; 2094 UINT32 Reserved2:7; 2095 /// 2096 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit. 2097 /// 2098 UINT32 SW_BLOCK:1; 2099 UINT32 Reserved3:1; 2100 /// 2101 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1). 2102 /// 2103 UINT32 HW_BLOCK:1; 2104 UINT32 Reserved4:5; 2105 UINT32 Reserved5:32; 2106 } Bits; 2107 /// 2108 /// All bit fields as a 32-bit value 2109 /// 2110 UINT32 Uint32; 2111 /// 2112 /// All bit fields as a 64-bit value 2113 /// 2114 UINT64 Uint64; 2115} MSR_IA32_DCA_0_CAP_REGISTER; 2116 2117 2118/** 2119 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". 2120 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. 2121 2122 @param ECX MSR_IA32_MTRR_PHYSBASEn 2123 @param EAX Lower 32-bits of MSR value. 2124 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. 2125 @param EDX Upper 32-bits of MSR value. 2126 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. 2127 2128 <b>Example usage</b> 2129 @code 2130 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr; 2131 2132 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0); 2133 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64); 2134 @endcode 2135 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. 2136 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. 2137 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. 2138 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. 2139 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. 2140 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. 2141 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. 2142 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. 2143 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. 2144 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM. 2145 @{ 2146**/ 2147#define MSR_IA32_MTRR_PHYSBASE0 0x00000200 2148#define MSR_IA32_MTRR_PHYSBASE1 0x00000202 2149#define MSR_IA32_MTRR_PHYSBASE2 0x00000204 2150#define MSR_IA32_MTRR_PHYSBASE3 0x00000206 2151#define MSR_IA32_MTRR_PHYSBASE4 0x00000208 2152#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A 2153#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C 2154#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E 2155#define MSR_IA32_MTRR_PHYSBASE8 0x00000210 2156#define MSR_IA32_MTRR_PHYSBASE9 0x00000212 2157/// @} 2158 2159/** 2160 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to 2161 #MSR_IA32_MTRR_PHYSBASE9 2162**/ 2163typedef union { 2164 /// 2165 /// Individual bit fields 2166 /// 2167 struct { 2168 /// 2169 /// [Bits 7:0] Type. Specifies memory type of the range. 2170 /// 2171 UINT32 Type:8; 2172 UINT32 Reserved1:4; 2173 /// 2174 /// [Bits 31:12] PhysBase. MTRR physical Base Address. 2175 /// 2176 UINT32 PhysBase:20; 2177 /// 2178 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address. 2179 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the 2180 /// maximum physical address range supported by the processor. It is 2181 /// reported by CPUID leaf function 80000008H. If CPUID does not support 2182 /// leaf 80000008H, the processor supports 36-bit physical address size, 2183 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. 2184 /// 2185 UINT32 PhysBaseHi:32; 2186 } Bits; 2187 /// 2188 /// All bit fields as a 64-bit value 2189 /// 2190 UINT64 Uint64; 2191} MSR_IA32_MTRR_PHYSBASE_REGISTER; 2192 2193 2194/** 2195 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". 2196 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. 2197 2198 @param ECX MSR_IA32_MTRR_PHYSMASKn 2199 @param EAX Lower 32-bits of MSR value. 2200 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. 2201 @param EDX Upper 32-bits of MSR value. 2202 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. 2203 2204 <b>Example usage</b> 2205 @code 2206 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr; 2207 2208 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0); 2209 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64); 2210 @endcode 2211 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. 2212 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. 2213 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. 2214 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. 2215 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. 2216 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. 2217 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. 2218 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. 2219 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. 2220 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM. 2221 @{ 2222**/ 2223#define MSR_IA32_MTRR_PHYSMASK0 0x00000201 2224#define MSR_IA32_MTRR_PHYSMASK1 0x00000203 2225#define MSR_IA32_MTRR_PHYSMASK2 0x00000205 2226#define MSR_IA32_MTRR_PHYSMASK3 0x00000207 2227#define MSR_IA32_MTRR_PHYSMASK4 0x00000209 2228#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B 2229#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D 2230#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F 2231#define MSR_IA32_MTRR_PHYSMASK8 0x00000211 2232#define MSR_IA32_MTRR_PHYSMASK9 0x00000213 2233/// @} 2234 2235/** 2236 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to 2237 #MSR_IA32_MTRR_PHYSMASK9 2238**/ 2239typedef union { 2240 /// 2241 /// Individual bit fields 2242 /// 2243 struct { 2244 UINT32 Reserved1:11; 2245 /// 2246 /// [Bit 11] Valid Enable range mask. 2247 /// 2248 UINT32 V:1; 2249 /// 2250 /// [Bits 31:12] PhysMask. MTRR address range mask. 2251 /// 2252 UINT32 PhysMask:20; 2253 /// 2254 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask. 2255 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the 2256 /// maximum physical address range supported by the processor. It is 2257 /// reported by CPUID leaf function 80000008H. If CPUID does not support 2258 /// leaf 80000008H, the processor supports 36-bit physical address size, 2259 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. 2260 /// 2261 UINT32 PhysMaskHi:32; 2262 } Bits; 2263 /// 2264 /// All bit fields as a 64-bit value 2265 /// 2266 UINT64 Uint64; 2267} MSR_IA32_MTRR_PHYSMASK_REGISTER; 2268 2269 2270/** 2271 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1. 2272 2273 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250) 2274 @param EAX Lower 32-bits of MSR value. 2275 @param EDX Upper 32-bits of MSR value. 2276 2277 <b>Example usage</b> 2278 @code 2279 UINT64 Msr; 2280 2281 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000); 2282 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr); 2283 @endcode 2284 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM. 2285**/ 2286#define MSR_IA32_MTRR_FIX64K_00000 0x00000250 2287 2288 2289/** 2290 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1. 2291 2292 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258) 2293 @param EAX Lower 32-bits of MSR value. 2294 @param EDX Upper 32-bits of MSR value. 2295 2296 <b>Example usage</b> 2297 @code 2298 UINT64 Msr; 2299 2300 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000); 2301 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr); 2302 @endcode 2303 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM. 2304**/ 2305#define MSR_IA32_MTRR_FIX16K_80000 0x00000258 2306 2307 2308/** 2309 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1. 2310 2311 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259) 2312 @param EAX Lower 32-bits of MSR value. 2313 @param EDX Upper 32-bits of MSR value. 2314 2315 <b>Example usage</b> 2316 @code 2317 UINT64 Msr; 2318 2319 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000); 2320 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr); 2321 @endcode 2322 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM. 2323**/ 2324#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259 2325 2326 2327/** 2328 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1. 2329 2330 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268) 2331 @param EAX Lower 32-bits of MSR value. 2332 @param EDX Upper 32-bits of MSR value. 2333 2334 <b>Example usage</b> 2335 @code 2336 UINT64 Msr; 2337 2338 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000); 2339 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr); 2340 @endcode 2341 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM. 2342**/ 2343#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268 2344 2345 2346/** 2347 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1. 2348 2349 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269) 2350 @param EAX Lower 32-bits of MSR value. 2351 @param EDX Upper 32-bits of MSR value. 2352 2353 <b>Example usage</b> 2354 @code 2355 UINT64 Msr; 2356 2357 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000); 2358 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr); 2359 @endcode 2360 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM. 2361**/ 2362#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269 2363 2364 2365/** 2366 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1. 2367 2368 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A) 2369 @param EAX Lower 32-bits of MSR value. 2370 @param EDX Upper 32-bits of MSR value. 2371 2372 <b>Example usage</b> 2373 @code 2374 UINT64 Msr; 2375 2376 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000); 2377 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr); 2378 @endcode 2379 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM. 2380**/ 2381#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A 2382 2383 2384/** 2385 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1. 2386 2387 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B) 2388 @param EAX Lower 32-bits of MSR value. 2389 @param EDX Upper 32-bits of MSR value. 2390 2391 <b>Example usage</b> 2392 @code 2393 UINT64 Msr; 2394 2395 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000); 2396 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr); 2397 @endcode 2398 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM. 2399**/ 2400#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B 2401 2402 2403/** 2404 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1. 2405 2406 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C) 2407 @param EAX Lower 32-bits of MSR value. 2408 @param EDX Upper 32-bits of MSR value. 2409 2410 <b>Example usage</b> 2411 @code 2412 UINT64 Msr; 2413 2414 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000); 2415 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr); 2416 @endcode 2417 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM. 2418**/ 2419#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C 2420 2421 2422/** 2423 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1. 2424 2425 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D) 2426 @param EAX Lower 32-bits of MSR value. 2427 @param EDX Upper 32-bits of MSR value. 2428 2429 <b>Example usage</b> 2430 @code 2431 UINT64 Msr; 2432 2433 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000); 2434 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr); 2435 @endcode 2436 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM. 2437**/ 2438#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D 2439 2440 2441/** 2442 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1. 2443 2444 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E) 2445 @param EAX Lower 32-bits of MSR value. 2446 @param EDX Upper 32-bits of MSR value. 2447 2448 <b>Example usage</b> 2449 @code 2450 UINT64 Msr; 2451 2452 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000); 2453 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr); 2454 @endcode 2455 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM. 2456**/ 2457#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E 2458 2459 2460/** 2461 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1. 2462 2463 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F) 2464 @param EAX Lower 32-bits of MSR value. 2465 @param EDX Upper 32-bits of MSR value. 2466 2467 <b>Example usage</b> 2468 @code 2469 UINT64 Msr; 2470 2471 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000); 2472 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr); 2473 @endcode 2474 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM. 2475**/ 2476#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F 2477 2478 2479/** 2480 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1. 2481 2482 @param ECX MSR_IA32_PAT (0x00000277) 2483 @param EAX Lower 32-bits of MSR value. 2484 Described by the type MSR_IA32_PAT_REGISTER. 2485 @param EDX Upper 32-bits of MSR value. 2486 Described by the type MSR_IA32_PAT_REGISTER. 2487 2488 <b>Example usage</b> 2489 @code 2490 MSR_IA32_PAT_REGISTER Msr; 2491 2492 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT); 2493 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64); 2494 @endcode 2495 @note MSR_IA32_PAT is defined as IA32_PAT in SDM. 2496**/ 2497#define MSR_IA32_PAT 0x00000277 2498 2499/** 2500 MSR information returned for MSR index #MSR_IA32_PAT 2501**/ 2502typedef union { 2503 /// 2504 /// Individual bit fields 2505 /// 2506 struct { 2507 /// 2508 /// [Bits 2:0] PA0. 2509 /// 2510 UINT32 PA0:3; 2511 UINT32 Reserved1:5; 2512 /// 2513 /// [Bits 10:8] PA1. 2514 /// 2515 UINT32 PA1:3; 2516 UINT32 Reserved2:5; 2517 /// 2518 /// [Bits 18:16] PA2. 2519 /// 2520 UINT32 PA2:3; 2521 UINT32 Reserved3:5; 2522 /// 2523 /// [Bits 26:24] PA3. 2524 /// 2525 UINT32 PA3:3; 2526 UINT32 Reserved4:5; 2527 /// 2528 /// [Bits 34:32] PA4. 2529 /// 2530 UINT32 PA4:3; 2531 UINT32 Reserved5:5; 2532 /// 2533 /// [Bits 42:40] PA5. 2534 /// 2535 UINT32 PA5:3; 2536 UINT32 Reserved6:5; 2537 /// 2538 /// [Bits 50:48] PA6. 2539 /// 2540 UINT32 PA6:3; 2541 UINT32 Reserved7:5; 2542 /// 2543 /// [Bits 58:56] PA7. 2544 /// 2545 UINT32 PA7:3; 2546 UINT32 Reserved8:5; 2547 } Bits; 2548 /// 2549 /// All bit fields as a 64-bit value 2550 /// 2551 UINT64 Uint64; 2552} MSR_IA32_PAT_REGISTER; 2553 2554 2555/** 2556 Provides the programming interface to use corrected MC error signaling 2557 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n. 2558 2559 @param ECX MSR_IA32_MCn_CTL2 2560 @param EAX Lower 32-bits of MSR value. 2561 Described by the type MSR_IA32_MC_CTL2_REGISTER. 2562 @param EDX Upper 32-bits of MSR value. 2563 Described by the type MSR_IA32_MC_CTL2_REGISTER. 2564 2565 <b>Example usage</b> 2566 @code 2567 MSR_IA32_MC_CTL2_REGISTER Msr; 2568 2569 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2); 2570 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64); 2571 @endcode 2572 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. 2573 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. 2574 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. 2575 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. 2576 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. 2577 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. 2578 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. 2579 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. 2580 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. 2581 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. 2582 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. 2583 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. 2584 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. 2585 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. 2586 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. 2587 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. 2588 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. 2589 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. 2590 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. 2591 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. 2592 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. 2593 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. 2594 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. 2595 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. 2596 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. 2597 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. 2598 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. 2599 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. 2600 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. 2601 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. 2602 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. 2603 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM. 2604 @{ 2605**/ 2606#define MSR_IA32_MC0_CTL2 0x00000280 2607#define MSR_IA32_MC1_CTL2 0x00000281 2608#define MSR_IA32_MC2_CTL2 0x00000282 2609#define MSR_IA32_MC3_CTL2 0x00000283 2610#define MSR_IA32_MC4_CTL2 0x00000284 2611#define MSR_IA32_MC5_CTL2 0x00000285 2612#define MSR_IA32_MC6_CTL2 0x00000286 2613#define MSR_IA32_MC7_CTL2 0x00000287 2614#define MSR_IA32_MC8_CTL2 0x00000288 2615#define MSR_IA32_MC9_CTL2 0x00000289 2616#define MSR_IA32_MC10_CTL2 0x0000028A 2617#define MSR_IA32_MC11_CTL2 0x0000028B 2618#define MSR_IA32_MC12_CTL2 0x0000028C 2619#define MSR_IA32_MC13_CTL2 0x0000028D 2620#define MSR_IA32_MC14_CTL2 0x0000028E 2621#define MSR_IA32_MC15_CTL2 0x0000028F 2622#define MSR_IA32_MC16_CTL2 0x00000290 2623#define MSR_IA32_MC17_CTL2 0x00000291 2624#define MSR_IA32_MC18_CTL2 0x00000292 2625#define MSR_IA32_MC19_CTL2 0x00000293 2626#define MSR_IA32_MC20_CTL2 0x00000294 2627#define MSR_IA32_MC21_CTL2 0x00000295 2628#define MSR_IA32_MC22_CTL2 0x00000296 2629#define MSR_IA32_MC23_CTL2 0x00000297 2630#define MSR_IA32_MC24_CTL2 0x00000298 2631#define MSR_IA32_MC25_CTL2 0x00000299 2632#define MSR_IA32_MC26_CTL2 0x0000029A 2633#define MSR_IA32_MC27_CTL2 0x0000029B 2634#define MSR_IA32_MC28_CTL2 0x0000029C 2635#define MSR_IA32_MC29_CTL2 0x0000029D 2636#define MSR_IA32_MC30_CTL2 0x0000029E 2637#define MSR_IA32_MC31_CTL2 0x0000029F 2638/// @} 2639 2640/** 2641 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2 2642 to #MSR_IA32_MC31_CTL2 2643**/ 2644typedef union { 2645 /// 2646 /// Individual bit fields 2647 /// 2648 struct { 2649 /// 2650 /// [Bits 14:0] Corrected error count threshold. 2651 /// 2652 UINT32 CorrectedErrorCountThreshold:15; 2653 UINT32 Reserved1:15; 2654 /// 2655 /// [Bit 30] CMCI_EN. 2656 /// 2657 UINT32 CMCI_EN:1; 2658 UINT32 Reserved2:1; 2659 UINT32 Reserved3:32; 2660 } Bits; 2661 /// 2662 /// All bit fields as a 32-bit value 2663 /// 2664 UINT32 Uint32; 2665 /// 2666 /// All bit fields as a 64-bit value 2667 /// 2668 UINT64 Uint64; 2669} MSR_IA32_MC_CTL2_REGISTER; 2670 2671 2672/** 2673 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1. 2674 2675 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF) 2676 @param EAX Lower 32-bits of MSR value. 2677 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. 2678 @param EDX Upper 32-bits of MSR value. 2679 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. 2680 2681 <b>Example usage</b> 2682 @code 2683 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr; 2684 2685 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); 2686 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64); 2687 @endcode 2688 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM. 2689**/ 2690#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF 2691 2692/** 2693 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE 2694**/ 2695typedef union { 2696 /// 2697 /// Individual bit fields 2698 /// 2699 struct { 2700 /// 2701 /// [Bits 2:0] Default Memory Type. 2702 /// 2703 UINT32 Type:3; 2704 UINT32 Reserved1:7; 2705 /// 2706 /// [Bit 10] Fixed Range MTRR Enable. 2707 /// 2708 UINT32 FE:1; 2709 /// 2710 /// [Bit 11] MTRR Enable. 2711 /// 2712 UINT32 E:1; 2713 UINT32 Reserved2:20; 2714 UINT32 Reserved3:32; 2715 } Bits; 2716 /// 2717 /// All bit fields as a 32-bit value 2718 /// 2719 UINT32 Uint32; 2720 /// 2721 /// All bit fields as a 64-bit value 2722 /// 2723 UINT64 Uint64; 2724} MSR_IA32_MTRR_DEF_TYPE_REGISTER; 2725 2726 2727/** 2728 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If 2729 CPUID.0AH: EDX[4:0] > 0. 2730 2731 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309) 2732 @param EAX Lower 32-bits of MSR value. 2733 @param EDX Upper 32-bits of MSR value. 2734 2735 <b>Example usage</b> 2736 @code 2737 UINT64 Msr; 2738 2739 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0); 2740 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr); 2741 @endcode 2742 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM. 2743**/ 2744#define MSR_IA32_FIXED_CTR0 0x00000309 2745 2746 2747/** 2748 Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If 2749 CPUID.0AH: EDX[4:0] > 1. 2750 2751 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A) 2752 @param EAX Lower 32-bits of MSR value. 2753 @param EDX Upper 32-bits of MSR value. 2754 2755 <b>Example usage</b> 2756 @code 2757 UINT64 Msr; 2758 2759 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1); 2760 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr); 2761 @endcode 2762 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM. 2763**/ 2764#define MSR_IA32_FIXED_CTR1 0x0000030A 2765 2766 2767/** 2768 Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If 2769 CPUID.0AH: EDX[4:0] > 2. 2770 2771 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B) 2772 @param EAX Lower 32-bits of MSR value. 2773 @param EDX Upper 32-bits of MSR value. 2774 2775 <b>Example usage</b> 2776 @code 2777 UINT64 Msr; 2778 2779 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2); 2780 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr); 2781 @endcode 2782 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM. 2783**/ 2784#define MSR_IA32_FIXED_CTR2 0x0000030B 2785 2786 2787/** 2788 RO. If CPUID.01H: ECX[15] = 1. 2789 2790 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345) 2791 @param EAX Lower 32-bits of MSR value. 2792 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. 2793 @param EDX Upper 32-bits of MSR value. 2794 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. 2795 2796 <b>Example usage</b> 2797 @code 2798 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr; 2799 2800 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES); 2801 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64); 2802 @endcode 2803 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM. 2804**/ 2805#define MSR_IA32_PERF_CAPABILITIES 0x00000345 2806 2807/** 2808 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES 2809**/ 2810typedef union { 2811 /// 2812 /// Individual bit fields 2813 /// 2814 struct { 2815 /// 2816 /// [Bits 5:0] LBR format. 2817 /// 2818 UINT32 LBR_FMT:6; 2819 /// 2820 /// [Bit 6] PEBS Trap. 2821 /// 2822 UINT32 PEBS_TRAP:1; 2823 /// 2824 /// [Bit 7] PEBSSaveArchRegs. 2825 /// 2826 UINT32 PEBS_ARCH_REG:1; 2827 /// 2828 /// [Bits 11:8] PEBS Record Format. 2829 /// 2830 UINT32 PEBS_REC_FMT:4; 2831 /// 2832 /// [Bit 12] 1: Freeze while SMM is supported. 2833 /// 2834 UINT32 SMM_FREEZE:1; 2835 /// 2836 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx. 2837 /// 2838 UINT32 FW_WRITE:1; 2839 UINT32 Reserved1:18; 2840 UINT32 Reserved2:32; 2841 } Bits; 2842 /// 2843 /// All bit fields as a 32-bit value 2844 /// 2845 UINT32 Uint32; 2846 /// 2847 /// All bit fields as a 64-bit value 2848 /// 2849 UINT64 Uint64; 2850} MSR_IA32_PERF_CAPABILITIES_REGISTER; 2851 2852 2853/** 2854 Fixed-Function Performance Counter Control (R/W) Counter increments while 2855 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with 2856 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0] 2857 > 1. 2858 2859 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D) 2860 @param EAX Lower 32-bits of MSR value. 2861 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. 2862 @param EDX Upper 32-bits of MSR value. 2863 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. 2864 2865 <b>Example usage</b> 2866 @code 2867 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr; 2868 2869 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL); 2870 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64); 2871 @endcode 2872 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM. 2873**/ 2874#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D 2875 2876/** 2877 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL 2878**/ 2879typedef union { 2880 /// 2881 /// Individual bit fields 2882 /// 2883 struct { 2884 /// 2885 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0. 2886 /// 2887 UINT32 EN0_OS:1; 2888 /// 2889 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0. 2890 /// 2891 UINT32 EN0_Usr:1; 2892 /// 2893 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated 2894 /// event conditions occurring across all logical processors sharing a 2895 /// processor core. When set to 0, the counter only increments the 2896 /// associated event conditions occurring in the logical processor which 2897 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. 2898 /// 2899 UINT32 AnyThread0:1; 2900 /// 2901 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows. 2902 /// 2903 UINT32 EN0_PMI:1; 2904 /// 2905 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0. 2906 /// 2907 UINT32 EN1_OS:1; 2908 /// 2909 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0. 2910 /// 2911 UINT32 EN1_Usr:1; 2912 /// 2913 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated 2914 /// event conditions occurring across all logical processors sharing a 2915 /// processor core. When set to 0, the counter only increments the 2916 /// associated event conditions occurring in the logical processor which 2917 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. 2918 /// 2919 UINT32 AnyThread1:1; 2920 /// 2921 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows. 2922 /// 2923 UINT32 EN1_PMI:1; 2924 /// 2925 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0. 2926 /// 2927 UINT32 EN2_OS:1; 2928 /// 2929 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0. 2930 /// 2931 UINT32 EN2_Usr:1; 2932 /// 2933 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated 2934 /// event conditions occurring across all logical processors sharing a 2935 /// processor core. When set to 0, the counter only increments the 2936 /// associated event conditions occurring in the logical processor which 2937 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. 2938 /// 2939 UINT32 AnyThread2:1; 2940 /// 2941 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows. 2942 /// 2943 UINT32 EN2_PMI:1; 2944 UINT32 Reserved1:20; 2945 UINT32 Reserved2:32; 2946 } Bits; 2947 /// 2948 /// All bit fields as a 32-bit value 2949 /// 2950 UINT32 Uint32; 2951 /// 2952 /// All bit fields as a 64-bit value 2953 /// 2954 UINT64 Uint64; 2955} MSR_IA32_FIXED_CTR_CTRL_REGISTER; 2956 2957 2958/** 2959 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0. 2960 2961 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E) 2962 @param EAX Lower 32-bits of MSR value. 2963 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. 2964 @param EDX Upper 32-bits of MSR value. 2965 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. 2966 2967 <b>Example usage</b> 2968 @code 2969 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; 2970 2971 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS); 2972 @endcode 2973 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. 2974**/ 2975#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E 2976 2977/** 2978 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS 2979**/ 2980typedef union { 2981 /// 2982 /// Individual bit fields 2983 /// 2984 struct { 2985 /// 2986 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH: 2987 /// EAX[15:8] > 0. 2988 /// 2989 UINT32 Ovf_PMC0:1; 2990 /// 2991 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH: 2992 /// EAX[15:8] > 1. 2993 /// 2994 UINT32 Ovf_PMC1:1; 2995 /// 2996 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH: 2997 /// EAX[15:8] > 2. 2998 /// 2999 UINT32 Ovf_PMC2:1; 3000 /// 3001 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH: 3002 /// EAX[15:8] > 3. 3003 /// 3004 UINT32 Ovf_PMC3:1; 3005 UINT32 Reserved1:28; 3006 /// 3007 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If 3008 /// CPUID.0AH: EAX[7:0] > 1. 3009 /// 3010 UINT32 Ovf_FixedCtr0:1; 3011 /// 3012 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If 3013 /// CPUID.0AH: EAX[7:0] > 1. 3014 /// 3015 UINT32 Ovf_FixedCtr1:1; 3016 /// 3017 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If 3018 /// CPUID.0AH: EAX[7:0] > 1. 3019 /// 3020 UINT32 Ovf_FixedCtr2:1; 3021 UINT32 Reserved2:20; 3022 /// 3023 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory 3024 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) 3025 /// && IA32_RTIT_CTL.ToPA = 1. 3026 /// 3027 UINT32 Trace_ToPA_PMI:1; 3028 UINT32 Reserved3:2; 3029 /// 3030 /// [Bit 58] LBR_Frz: LBRs are frozen due to - 3031 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If 3032 /// CPUID.0AH: EAX[7:0] > 3. 3033 /// 3034 UINT32 LBR_Frz:1; 3035 /// 3036 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due 3037 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU 3038 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3. 3039 /// 3040 UINT32 CTR_Frz:1; 3041 /// 3042 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may 3043 /// include contributions from the direct or indirect operation intel SGX 3044 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1. 3045 /// 3046 UINT32 ASCI:1; 3047 /// 3048 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH: 3049 /// EAX[7:0] > 2. 3050 /// 3051 UINT32 Ovf_Uncore:1; 3052 /// 3053 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH: 3054 /// EAX[7:0] > 0. 3055 /// 3056 UINT32 OvfBuf:1; 3057 /// 3058 /// [Bit 63] CondChgd: status bits of this register has changed. If 3059 /// CPUID.0AH: EAX[7:0] > 0. 3060 /// 3061 UINT32 CondChgd:1; 3062 } Bits; 3063 /// 3064 /// All bit fields as a 64-bit value 3065 /// 3066 UINT64 Uint64; 3067} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER; 3068 3069 3070/** 3071 Global Performance Counter Control (R/W) Counter increments while the result 3072 of ANDing respective enable bit in this MSR with the corresponding OS or USR 3073 bits in the general-purpose or fixed counter control MSR is true. If 3074 CPUID.0AH: EAX[7:0] > 0. 3075 3076 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F) 3077 @param EAX Lower 32-bits of MSR value. 3078 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. 3079 @param EDX Upper 32-bits of MSR value. 3080 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. 3081 3082 <b>Example usage</b> 3083 @code 3084 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr; 3085 3086 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL); 3087 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64); 3088 @endcode 3089 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM. 3090**/ 3091#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F 3092 3093/** 3094 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL 3095**/ 3096typedef union { 3097 /// 3098 /// Individual bit fields 3099/// 3100 struct { 3101 /// 3102 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n. 3103 /// Enable bitmask. Only the first n-1 bits are valid. 3104 /// Bits n..31 are reserved. 3105 /// 3106 UINT32 EN_PMCn:32; 3107 /// 3108 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n. 3109 /// Enable bitmask. Only the first n-1 bits are valid. 3110 /// Bits 31:n are reserved. 3111 /// 3112 UINT32 EN_FIXED_CTRn:32; 3113 } Bits; 3114 /// 3115 /// All bit fields as a 64-bit value 3116 /// 3117 UINT64 Uint64; 3118} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER; 3119 3120 3121/** 3122 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] > 3123 0 && CPUID.0AH: EAX[7:0] <= 3. 3124 3125 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390) 3126 @param EAX Lower 32-bits of MSR value. 3127 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. 3128 @param EDX Upper 32-bits of MSR value. 3129 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. 3130 3131 <b>Example usage</b> 3132 @code 3133 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; 3134 3135 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL); 3136 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); 3137 @endcode 3138 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM. 3139**/ 3140#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 3141 3142/** 3143 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL 3144**/ 3145typedef union { 3146 /// 3147 /// Individual bit fields 3148 /// 3149 struct { 3150 /// 3151 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. 3152 /// Clear bitmask. Only the first n-1 bits are valid. 3153 /// Bits 31:n are reserved. 3154 /// 3155 UINT32 Ovf_PMCn:32; 3156 /// 3157 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. 3158 /// If CPUID.0AH: EDX[4:0] > n. 3159 /// Clear bitmask. Only the first n-1 bits are valid. 3160 /// Bits 22:n are reserved. 3161 /// 3162 UINT32 Ovf_FIXED_CTRn:23; 3163 /// 3164 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, 3165 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1. 3166 /// 3167 UINT32 Trace_ToPA_PMI:1; 3168 UINT32 Reserved2:5; 3169 /// 3170 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / 3171 /// Display Model 06_2EH. 3172 /// 3173 UINT32 Ovf_Uncore:1; 3174 /// 3175 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. 3176 /// 3177 UINT32 OvfBuf:1; 3178 /// 3179 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. 3180 /// 3181 UINT32 CondChgd:1; 3182 } Bits; 3183 /// 3184 /// All bit fields as a 64-bit value 3185 /// 3186 UINT64 Uint64; 3187} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER; 3188 3189 3190/** 3191 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH: 3192 EAX[7:0] > 3. 3193 3194 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) 3195 @param EAX Lower 32-bits of MSR value. 3196 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 3197 @param EDX Upper 32-bits of MSR value. 3198 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 3199 3200 <b>Example usage</b> 3201 @code 3202 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; 3203 3204 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET); 3205 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); 3206 @endcode 3207 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. 3208**/ 3209#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 3210 3211/** 3212 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET 3213**/ 3214typedef union { 3215 /// 3216 /// Individual bit fields 3217 /// 3218 struct { 3219 /// 3220 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. 3221 /// Clear bitmask. Only the first n-1 bits are valid. 3222 /// Bits 31:n are reserved. 3223 /// 3224 UINT32 Ovf_PMCn:32; 3225 /// 3226 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. 3227 /// If CPUID.0AH: EDX[4:0] > n. 3228 /// Clear bitmask. Only the first n-1 bits are valid. 3229 /// Bits 22:n are reserved. 3230 /// 3231 UINT32 Ovf_FIXED_CTRn:23; 3232 /// 3233 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, 3234 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1. 3235 /// 3236 UINT32 Trace_ToPA_PMI:1; 3237 UINT32 Reserved2:2; 3238 /// 3239 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. 3240 /// 3241 UINT32 LBR_Frz:1; 3242 /// 3243 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. 3244 /// 3245 UINT32 CTR_Frz:1; 3246 /// 3247 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3. 3248 /// 3249 UINT32 ASCI:1; 3250 /// 3251 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / 3252 /// Display Model 06_2EH. 3253 /// 3254 UINT32 Ovf_Uncore:1; 3255 /// 3256 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. 3257 /// 3258 UINT32 OvfBuf:1; 3259 /// 3260 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. 3261 /// 3262 UINT32 CondChgd:1; 3263 } Bits; 3264 /// 3265 /// All bit fields as a 64-bit value 3266 /// 3267 UINT64 Uint64; 3268} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; 3269 3270 3271/** 3272 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH: 3273 EAX[7:0] > 3. 3274 3275 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) 3276 @param EAX Lower 32-bits of MSR value. 3277 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 3278 @param EDX Upper 32-bits of MSR value. 3279 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 3280 3281 <b>Example usage</b> 3282 @code 3283 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; 3284 3285 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET); 3286 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); 3287 @endcode 3288 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. 3289**/ 3290#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 3291 3292/** 3293 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET 3294**/ 3295typedef union { 3296 /// 3297 /// Individual bit fields 3298 /// 3299 struct { 3300 /// 3301 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n. 3302 /// Set bitmask. Only the first n-1 bits are valid. 3303 /// Bits 31:n are reserved. 3304 /// 3305 UINT32 Ovf_PMCn:32; 3306 /// 3307 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1. 3308 /// If CPUID.0AH: EAX[7:0] > n. 3309 /// Set bitmask. Only the first n-1 bits are valid. 3310 /// Bits 22:n are reserved. 3311 /// 3312 UINT32 Ovf_FIXED_CTRn:23; 3313 /// 3314 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3. 3315 /// 3316 UINT32 Trace_ToPA_PMI:1; 3317 UINT32 Reserved2:2; 3318 /// 3319 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. 3320 /// 3321 UINT32 LBR_Frz:1; 3322 /// 3323 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. 3324 /// 3325 UINT32 CTR_Frz:1; 3326 /// 3327 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3. 3328 /// 3329 UINT32 ASCI:1; 3330 /// 3331 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3. 3332 /// 3333 UINT32 Ovf_Uncore:1; 3334 /// 3335 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3. 3336 /// 3337 UINT32 OvfBuf:1; 3338 UINT32 Reserved3:1; 3339 } Bits; 3340 /// 3341 /// All bit fields as a 64-bit value 3342 /// 3343 UINT64 Uint64; 3344} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; 3345 3346 3347/** 3348 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] > 3349 3. 3350 3351 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392) 3352 @param EAX Lower 32-bits of MSR value. 3353 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. 3354 @param EDX Upper 32-bits of MSR value. 3355 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. 3356 3357 <b>Example usage</b> 3358 @code 3359 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr; 3360 3361 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE); 3362 @endcode 3363 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM. 3364**/ 3365#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392 3366 3367/** 3368 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE 3369**/ 3370typedef union { 3371 /// 3372 /// Individual bit fields 3373 /// 3374 struct { 3375 /// 3376 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n. 3377 /// Status bitmask. Only the first n-1 bits are valid. 3378 /// Bits 31:n are reserved. 3379 /// 3380 UINT32 IA32_PERFEVTSELn:32; 3381 /// 3382 /// [Bits 62:32] IA32_FIXED_CTRn in use. 3383 /// If CPUID.0AH: EAX[7:0] > n. 3384 /// Status bitmask. Only the first n-1 bits are valid. 3385 /// Bits 30:n are reserved. 3386 /// 3387 UINT32 IA32_FIXED_CTRn:31; 3388 /// 3389 /// [Bit 63] PMI in use. 3390 /// 3391 UINT32 PMI:1; 3392 } Bits; 3393 /// 3394 /// All bit fields as a 64-bit value 3395 /// 3396 UINT64 Uint64; 3397} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER; 3398 3399 3400/** 3401 PEBS Control (R/W). 3402 3403 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1) 3404 @param EAX Lower 32-bits of MSR value. 3405 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. 3406 @param EDX Upper 32-bits of MSR value. 3407 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. 3408 3409 <b>Example usage</b> 3410 @code 3411 MSR_IA32_PEBS_ENABLE_REGISTER Msr; 3412 3413 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE); 3414 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64); 3415 @endcode 3416 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM. 3417**/ 3418#define MSR_IA32_PEBS_ENABLE 0x000003F1 3419 3420/** 3421 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE 3422**/ 3423typedef union { 3424 /// 3425 /// Individual bit fields 3426 /// 3427 struct { 3428 /// 3429 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family / 3430 /// Display Model 06_0FH. 3431 /// 3432 UINT32 Enable:1; 3433 /// 3434 /// [Bits 3:1] Reserved or Model specific. 3435 /// 3436 UINT32 Reserved1:3; 3437 UINT32 Reserved2:28; 3438 /// 3439 /// [Bits 35:32] Reserved or Model specific. 3440 /// 3441 UINT32 Reserved3:4; 3442 UINT32 Reserved4:28; 3443 } Bits; 3444 /// 3445 /// All bit fields as a 64-bit value 3446 /// 3447 UINT64 Uint64; 3448} MSR_IA32_PEBS_ENABLE_REGISTER; 3449 3450 3451/** 3452 MCn_CTL. If IA32_MCG_CAP.CNT > n. 3453 3454 @param ECX MSR_IA32_MCn_CTL 3455 @param EAX Lower 32-bits of MSR value. 3456 @param EDX Upper 32-bits of MSR value. 3457 3458 <b>Example usage</b> 3459 @code 3460 UINT64 Msr; 3461 3462 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL); 3463 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr); 3464 @endcode 3465 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. 3466 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. 3467 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. 3468 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. 3469 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. 3470 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. 3471 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. 3472 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. 3473 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. 3474 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. 3475 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. 3476 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. 3477 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. 3478 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. 3479 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. 3480 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. 3481 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. 3482 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. 3483 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. 3484 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. 3485 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. 3486 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. 3487 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. 3488 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. 3489 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. 3490 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. 3491 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. 3492 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. 3493 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM. 3494 @{ 3495**/ 3496#define MSR_IA32_MC0_CTL 0x00000400 3497#define MSR_IA32_MC1_CTL 0x00000404 3498#define MSR_IA32_MC2_CTL 0x00000408 3499#define MSR_IA32_MC3_CTL 0x0000040C 3500#define MSR_IA32_MC4_CTL 0x00000410 3501#define MSR_IA32_MC5_CTL 0x00000414 3502#define MSR_IA32_MC6_CTL 0x00000418 3503#define MSR_IA32_MC7_CTL 0x0000041C 3504#define MSR_IA32_MC8_CTL 0x00000420 3505#define MSR_IA32_MC9_CTL 0x00000424 3506#define MSR_IA32_MC10_CTL 0x00000428 3507#define MSR_IA32_MC11_CTL 0x0000042C 3508#define MSR_IA32_MC12_CTL 0x00000430 3509#define MSR_IA32_MC13_CTL 0x00000434 3510#define MSR_IA32_MC14_CTL 0x00000438 3511#define MSR_IA32_MC15_CTL 0x0000043C 3512#define MSR_IA32_MC16_CTL 0x00000440 3513#define MSR_IA32_MC17_CTL 0x00000444 3514#define MSR_IA32_MC18_CTL 0x00000448 3515#define MSR_IA32_MC19_CTL 0x0000044C 3516#define MSR_IA32_MC20_CTL 0x00000450 3517#define MSR_IA32_MC21_CTL 0x00000454 3518#define MSR_IA32_MC22_CTL 0x00000458 3519#define MSR_IA32_MC23_CTL 0x0000045C 3520#define MSR_IA32_MC24_CTL 0x00000460 3521#define MSR_IA32_MC25_CTL 0x00000464 3522#define MSR_IA32_MC26_CTL 0x00000468 3523#define MSR_IA32_MC27_CTL 0x0000046C 3524#define MSR_IA32_MC28_CTL 0x00000470 3525/// @} 3526 3527 3528/** 3529 MCn_STATUS. If IA32_MCG_CAP.CNT > n. 3530 3531 @param ECX MSR_IA32_MCn_STATUS 3532 @param EAX Lower 32-bits of MSR value. 3533 @param EDX Upper 32-bits of MSR value. 3534 3535 <b>Example usage</b> 3536 @code 3537 UINT64 Msr; 3538 3539 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS); 3540 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr); 3541 @endcode 3542 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. 3543 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. 3544 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. 3545 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. 3546 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. 3547 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. 3548 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. 3549 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. 3550 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. 3551 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. 3552 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. 3553 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. 3554 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. 3555 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. 3556 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. 3557 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. 3558 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. 3559 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. 3560 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. 3561 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. 3562 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. 3563 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. 3564 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. 3565 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. 3566 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. 3567 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. 3568 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. 3569 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. 3570 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM. 3571 @{ 3572**/ 3573#define MSR_IA32_MC0_STATUS 0x00000401 3574#define MSR_IA32_MC1_STATUS 0x00000405 3575#define MSR_IA32_MC2_STATUS 0x00000409 3576#define MSR_IA32_MC3_STATUS 0x0000040D 3577#define MSR_IA32_MC4_STATUS 0x00000411 3578#define MSR_IA32_MC5_STATUS 0x00000415 3579#define MSR_IA32_MC6_STATUS 0x00000419 3580#define MSR_IA32_MC7_STATUS 0x0000041D 3581#define MSR_IA32_MC8_STATUS 0x00000421 3582#define MSR_IA32_MC9_STATUS 0x00000425 3583#define MSR_IA32_MC10_STATUS 0x00000429 3584#define MSR_IA32_MC11_STATUS 0x0000042D 3585#define MSR_IA32_MC12_STATUS 0x00000431 3586#define MSR_IA32_MC13_STATUS 0x00000435 3587#define MSR_IA32_MC14_STATUS 0x00000439 3588#define MSR_IA32_MC15_STATUS 0x0000043D 3589#define MSR_IA32_MC16_STATUS 0x00000441 3590#define MSR_IA32_MC17_STATUS 0x00000445 3591#define MSR_IA32_MC18_STATUS 0x00000449 3592#define MSR_IA32_MC19_STATUS 0x0000044D 3593#define MSR_IA32_MC20_STATUS 0x00000451 3594#define MSR_IA32_MC21_STATUS 0x00000455 3595#define MSR_IA32_MC22_STATUS 0x00000459 3596#define MSR_IA32_MC23_STATUS 0x0000045D 3597#define MSR_IA32_MC24_STATUS 0x00000461 3598#define MSR_IA32_MC25_STATUS 0x00000465 3599#define MSR_IA32_MC26_STATUS 0x00000469 3600#define MSR_IA32_MC27_STATUS 0x0000046D 3601#define MSR_IA32_MC28_STATUS 0x00000471 3602/// @} 3603 3604 3605/** 3606 MCn_ADDR. If IA32_MCG_CAP.CNT > n. 3607 3608 @param ECX MSR_IA32_MCn_ADDR 3609 @param EAX Lower 32-bits of MSR value. 3610 @param EDX Upper 32-bits of MSR value. 3611 3612 <b>Example usage</b> 3613 @code 3614 UINT64 Msr; 3615 3616 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR); 3617 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr); 3618 @endcode 3619 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. 3620 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. 3621 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. 3622 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. 3623 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. 3624 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. 3625 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. 3626 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. 3627 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. 3628 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. 3629 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. 3630 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. 3631 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. 3632 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. 3633 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. 3634 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. 3635 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. 3636 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. 3637 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. 3638 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. 3639 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. 3640 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. 3641 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. 3642 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. 3643 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. 3644 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. 3645 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. 3646 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. 3647 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM. 3648 @{ 3649**/ 3650#define MSR_IA32_MC0_ADDR 0x00000402 3651#define MSR_IA32_MC1_ADDR 0x00000406 3652#define MSR_IA32_MC2_ADDR 0x0000040A 3653#define MSR_IA32_MC3_ADDR 0x0000040E 3654#define MSR_IA32_MC4_ADDR 0x00000412 3655#define MSR_IA32_MC5_ADDR 0x00000416 3656#define MSR_IA32_MC6_ADDR 0x0000041A 3657#define MSR_IA32_MC7_ADDR 0x0000041E 3658#define MSR_IA32_MC8_ADDR 0x00000422 3659#define MSR_IA32_MC9_ADDR 0x00000426 3660#define MSR_IA32_MC10_ADDR 0x0000042A 3661#define MSR_IA32_MC11_ADDR 0x0000042E 3662#define MSR_IA32_MC12_ADDR 0x00000432 3663#define MSR_IA32_MC13_ADDR 0x00000436 3664#define MSR_IA32_MC14_ADDR 0x0000043A 3665#define MSR_IA32_MC15_ADDR 0x0000043E 3666#define MSR_IA32_MC16_ADDR 0x00000442 3667#define MSR_IA32_MC17_ADDR 0x00000446 3668#define MSR_IA32_MC18_ADDR 0x0000044A 3669#define MSR_IA32_MC19_ADDR 0x0000044E 3670#define MSR_IA32_MC20_ADDR 0x00000452 3671#define MSR_IA32_MC21_ADDR 0x00000456 3672#define MSR_IA32_MC22_ADDR 0x0000045A 3673#define MSR_IA32_MC23_ADDR 0x0000045E 3674#define MSR_IA32_MC24_ADDR 0x00000462 3675#define MSR_IA32_MC25_ADDR 0x00000466 3676#define MSR_IA32_MC26_ADDR 0x0000046A 3677#define MSR_IA32_MC27_ADDR 0x0000046E 3678#define MSR_IA32_MC28_ADDR 0x00000472 3679/// @} 3680 3681 3682/** 3683 MCn_MISC. If IA32_MCG_CAP.CNT > n. 3684 3685 @param ECX MSR_IA32_MCn_MISC 3686 @param EAX Lower 32-bits of MSR value. 3687 @param EDX Upper 32-bits of MSR value. 3688 3689 <b>Example usage</b> 3690 @code 3691 UINT64 Msr; 3692 3693 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC); 3694 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr); 3695 @endcode 3696 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. 3697 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. 3698 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. 3699 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. 3700 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. 3701 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. 3702 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. 3703 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. 3704 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. 3705 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. 3706 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. 3707 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. 3708 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. 3709 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. 3710 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. 3711 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. 3712 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. 3713 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. 3714 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. 3715 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. 3716 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. 3717 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. 3718 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. 3719 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. 3720 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. 3721 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. 3722 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. 3723 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. 3724 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM. 3725 @{ 3726**/ 3727#define MSR_IA32_MC0_MISC 0x00000403 3728#define MSR_IA32_MC1_MISC 0x00000407 3729#define MSR_IA32_MC2_MISC 0x0000040B 3730#define MSR_IA32_MC3_MISC 0x0000040F 3731#define MSR_IA32_MC4_MISC 0x00000413 3732#define MSR_IA32_MC5_MISC 0x00000417 3733#define MSR_IA32_MC6_MISC 0x0000041B 3734#define MSR_IA32_MC7_MISC 0x0000041F 3735#define MSR_IA32_MC8_MISC 0x00000423 3736#define MSR_IA32_MC9_MISC 0x00000427 3737#define MSR_IA32_MC10_MISC 0x0000042B 3738#define MSR_IA32_MC11_MISC 0x0000042F 3739#define MSR_IA32_MC12_MISC 0x00000433 3740#define MSR_IA32_MC13_MISC 0x00000437 3741#define MSR_IA32_MC14_MISC 0x0000043B 3742#define MSR_IA32_MC15_MISC 0x0000043F 3743#define MSR_IA32_MC16_MISC 0x00000443 3744#define MSR_IA32_MC17_MISC 0x00000447 3745#define MSR_IA32_MC18_MISC 0x0000044B 3746#define MSR_IA32_MC19_MISC 0x0000044F 3747#define MSR_IA32_MC20_MISC 0x00000453 3748#define MSR_IA32_MC21_MISC 0x00000457 3749#define MSR_IA32_MC22_MISC 0x0000045B 3750#define MSR_IA32_MC23_MISC 0x0000045F 3751#define MSR_IA32_MC24_MISC 0x00000463 3752#define MSR_IA32_MC25_MISC 0x00000467 3753#define MSR_IA32_MC26_MISC 0x0000046B 3754#define MSR_IA32_MC27_MISC 0x0000046F 3755#define MSR_IA32_MC28_MISC 0x00000473 3756/// @} 3757 3758 3759/** 3760 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic 3761 VMX Information.". If CPUID.01H:ECX.[5] = 1. 3762 3763 @param ECX MSR_IA32_VMX_BASIC (0x00000480) 3764 @param EAX Lower 32-bits of MSR value. 3765 @param EDX Upper 32-bits of MSR value. 3766 3767 <b>Example usage</b> 3768 @code 3769 MSR_IA32_VMX_BASIC_REGISTER Msr; 3770 3771 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC); 3772 @endcode 3773 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM. 3774**/ 3775#define MSR_IA32_VMX_BASIC 0x00000480 3776 3777/** 3778 MSR information returned for MSR index #MSR_IA32_VMX_BASIC 3779**/ 3780typedef union { 3781 /// 3782 /// Individual bit fields 3783 /// 3784 struct { 3785 /// 3786 /// [Bits 30:0] VMCS revision identifier used by the processor. Processors 3787 /// that use the same VMCS revision identifier use the same size for VMCS 3788 /// regions (see subsequent item on bits 44:32). 3789 /// 3790 /// @note Earlier versions of this manual specified that the VMCS revision 3791 /// identifier was a 32-bit field in bits 31:0 of this MSR. For all 3792 /// processors produced prior to this change, bit 31 of this MSR was read 3793 /// as 0. 3794 /// 3795 UINT32 VmcsRevisonId:31; 3796 UINT32 MustBeZero:1; 3797 /// 3798 /// [Bit 44:32] Reports the number of bytes that software should allocate 3799 /// for the VMXON region and any VMCS region. It is a value greater than 3800 /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear). 3801 /// 3802 UINT32 VmcsSize:13; 3803 UINT32 Reserved1:3; 3804 /// 3805 /// [Bit 48] Indicates the width of the physical addresses that may be used 3806 /// for the VMXON region, each VMCS, and data structures referenced by 3807 /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX 3808 /// transitions). If the bit is 0, these addresses are limited to the 3809 /// processor's physical-address width. If the bit is 1, these addresses 3810 /// are limited to 32 bits. This bit is always 0 for processors that 3811 /// support Intel 64 architecture. 3812 /// 3813 /// @note On processors that support Intel 64 architecture, the pointer 3814 /// must not set bits beyond the processor's physical address width. 3815 /// 3816 UINT32 VmcsAddressWidth:1; 3817 /// 3818 /// [Bit 49] If bit 49 is read as 1, the logical processor supports the 3819 /// dual-monitor treatment of system-management interrupts and 3820 /// system-management mode. See Section 34.15 for details of this treatment. 3821 /// 3822 UINT32 DualMonitor:1; 3823 /// 3824 /// [Bit 53:50] report the memory type that should be used for the VMCS, 3825 /// for data structures referenced by pointers in the VMCS (I/O bitmaps, 3826 /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG 3827 /// header. If software needs to access these data structures (e.g., to 3828 /// modify the contents of the MSR bitmaps), it can configure the paging 3829 /// structures to map them into the linear-address space. If it does so, 3830 /// it should establish mappings that use the memory type reported bits 3831 /// 53:50 in this MSR. 3832 /// 3833 /// As of this writing, all processors that support VMX operation indicate 3834 /// the write-back type. 3835 /// 3836 /// If software needs to access these data structures (e.g., to modify 3837 /// the contents of the MSR bitmaps), it can configure the paging 3838 /// structures to map them into the linear-address space. If it does so, 3839 /// it should establish mappings that use the memory type reported in this 3840 /// MSR. 3841 /// 3842 /// @note Alternatively, software may map any of these regions or 3843 /// structures with the UC memory type. (This may be necessary for the MSEG 3844 /// header.) Doing so is discouraged unless necessary as it will cause the 3845 /// performance of software accesses to those structures to suffer. 3846 /// 3847 /// 3848 UINT32 MemoryType:4; 3849 /// 3850 /// [Bit 54] If bit 54 is read as 1, the processor reports information in 3851 /// the VM-exit instruction-information field on VM exitsdue to execution 3852 /// of the INS and OUTS instructions (see Section 27.2.4). This reporting 3853 /// is done only if this bit is read as 1. 3854 /// 3855 UINT32 InsOutsReporting:1; 3856 /// 3857 /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may 3858 /// be cleared to 0. See Appendix A.2 for details. It also reports support 3859 /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, 3860 /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and 3861 /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2, 3862 /// Appendix A.4, and Appendix A.5 for details. 3863 /// 3864 UINT32 VmxControls:1; 3865 UINT32 Reserved2:8; 3866 } Bits; 3867 /// 3868 /// All bit fields as a 64-bit value 3869 /// 3870 UINT64 Uint64; 3871} MSR_IA32_VMX_BASIC_REGISTER; 3872 3873/// 3874/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType 3875/// 3876#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00 3877#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06 3878/// 3879/// @} 3880/// 3881 3882 3883/** 3884 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See 3885 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1. 3886 3887 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481) 3888 @param EAX Lower 32-bits of MSR value. 3889 @param EDX Upper 32-bits of MSR value. 3890 3891 <b>Example usage</b> 3892 @code 3893 UINT64 Msr; 3894 3895 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS); 3896 @endcode 3897 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM. 3898**/ 3899#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 3900 3901 3902/** 3903 Capability Reporting Register of Primary Processor-based VM-execution 3904 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution 3905 Controls.". If CPUID.01H:ECX.[5] = 1. 3906 3907 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482) 3908 @param EAX Lower 32-bits of MSR value. 3909 @param EDX Upper 32-bits of MSR value. 3910 3911 <b>Example usage</b> 3912 @code 3913 UINT64 Msr; 3914 3915 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS); 3916 @endcode 3917 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM. 3918**/ 3919#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 3920 3921 3922/** 3923 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, 3924 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1. 3925 3926 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483) 3927 @param EAX Lower 32-bits of MSR value. 3928 @param EDX Upper 32-bits of MSR value. 3929 3930 <b>Example usage</b> 3931 @code 3932 UINT64 Msr; 3933 3934 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS); 3935 @endcode 3936 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM. 3937**/ 3938#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 3939 3940 3941/** 3942 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5, 3943 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1. 3944 3945 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484) 3946 @param EAX Lower 32-bits of MSR value. 3947 @param EDX Upper 32-bits of MSR value. 3948 3949 <b>Example usage</b> 3950 @code 3951 UINT64 Msr; 3952 3953 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS); 3954 @endcode 3955 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM. 3956**/ 3957#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 3958 3959 3960/** 3961 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, 3962 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1. 3963 3964 @param ECX MSR_IA32_VMX_MISC (0x00000485) 3965 @param EAX Lower 32-bits of MSR value. 3966 @param EDX Upper 32-bits of MSR value. 3967 3968 <b>Example usage</b> 3969 @code 3970 IA32_VMX_MISC_REGISTER Msr; 3971 3972 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC); 3973 @endcode 3974 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM. 3975**/ 3976#define MSR_IA32_VMX_MISC 0x00000485 3977 3978/** 3979 MSR information returned for MSR index #IA32_VMX_MISC 3980**/ 3981typedef union { 3982 /// 3983 /// Individual bit fields 3984 /// 3985 struct { 3986 /// 3987 /// [Bits 4:0] Reports a value X that specifies the relationship between the 3988 /// rate of the VMX-preemption timer and that of the timestamp counter (TSC). 3989 /// Specifically, the VMX-preemption timer (if it is active) counts down by 3990 /// 1 every time bit X in the TSC changes due to a TSC increment. 3991 /// 3992 UINT32 VmxTimerRatio:5; 3993 /// 3994 /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA 3995 /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more 3996 /// details. This bit is read as 1 on any logical processor that supports 3997 /// the 1-setting of the "unrestricted guest" VM-execution control. 3998 /// 3999 UINT32 VmExitEferLma:1; 4000 /// 4001 /// [Bit 6] reports (if set) the support for activity state 1 (HLT). 4002 /// 4003 UINT32 HltActivityStateSupported:1; 4004 /// 4005 /// [Bit 7] reports (if set) the support for activity state 2 (shutdown). 4006 /// 4007 UINT32 ShutdownActivityStateSupported:1; 4008 /// 4009 /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI). 4010 /// 4011 UINT32 WaitForSipiActivityStateSupported:1; 4012 UINT32 Reserved1:5; 4013 /// 4014 /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used 4015 /// in VMX operation. If the processor supports Intel PT but does not allow 4016 /// it to be used in VMX operation, execution of VMXON clears 4017 /// IA32_RTIT_CTL.TraceEn (see �VMXON�Enter VMX Operation� in Chapter 30); 4018 /// any attempt to set that bit while in VMX operation (including VMX root 4019 /// operation) using the WRMSR instruction causes a general-protection 4020 /// exception. 4021 /// 4022 UINT32 ProcessorTraceSupported:1; 4023 /// 4024 /// [Bit 15] If read as 1, the RDMSR instruction can be used in system- 4025 /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH). 4026 /// See Section 34.15.6.3. 4027 /// 4028 UINT32 SmBaseMsrSupported:1; 4029 /// 4030 /// [Bits 24:16] Indicate the number of CR3-target values supported by the 4031 /// processor. This number is a value between 0 and 256, inclusive (bit 24 4032 /// is set if and only if bits 23:16 are clear). 4033 /// 4034 UINT32 NumberOfCr3TargetValues:9; 4035 /// 4036 /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum 4037 /// number of MSRs that should appear in the VM-exit MSR-store list, the 4038 /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if 4039 /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the 4040 /// recommended maximum number of MSRs to be included in each list. If the 4041 /// limit is exceeded, undefined processor behavior may result (including a 4042 /// machine check during the VMX transition). 4043 /// 4044 UINT32 MsrStoreListMaximum:3; 4045 /// 4046 /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set 4047 /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 4048 /// (see Section 34.14.4). 4049 /// 4050 UINT32 BlockSmiSupported:1; 4051 /// 4052 /// [Bit 29] read as 1, software can use VMWRITE to write to any supported 4053 /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit 4054 /// information fields. 4055 /// 4056 UINT32 VmWriteSupported:1; 4057 /// 4058 /// [Bit 30] If read as 1, VM entry allows injection of a software 4059 /// interrupt, software exception, or privileged software exception with an 4060 /// instruction length of 0. 4061 /// 4062 UINT32 VmInjectSupported:1; 4063 UINT32 Reserved2:1; 4064 /// 4065 /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the 4066 /// processor. 4067 /// 4068 UINT32 MsegRevisionIdentifier:32; 4069 } Bits; 4070 /// 4071 /// All bit fields as a 64-bit value 4072 /// 4073 UINT64 Uint64; 4074} IA32_VMX_MISC_REGISTER; 4075 4076 4077/** 4078 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, 4079 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. 4080 4081 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486) 4082 @param EAX Lower 32-bits of MSR value. 4083 @param EDX Upper 32-bits of MSR value. 4084 4085 <b>Example usage</b> 4086 @code 4087 UINT64 Msr; 4088 4089 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0); 4090 @endcode 4091 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM. 4092**/ 4093#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 4094 4095 4096/** 4097 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, 4098 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. 4099 4100 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487) 4101 @param EAX Lower 32-bits of MSR value. 4102 @param EDX Upper 32-bits of MSR value. 4103 4104 <b>Example usage</b> 4105 @code 4106 UINT64 Msr; 4107 4108 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1); 4109 @endcode 4110 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM. 4111**/ 4112#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 4113 4114 4115/** 4116 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, 4117 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1. 4118 4119 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488) 4120 @param EAX Lower 32-bits of MSR value. 4121 @param EDX Upper 32-bits of MSR value. 4122 4123 <b>Example usage</b> 4124 @code 4125 UINT64 Msr; 4126 4127 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0); 4128 @endcode 4129 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM. 4130**/ 4131#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 4132 4133 4134/** 4135 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, 4136 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1. 4137 4138 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489) 4139 @param EAX Lower 32-bits of MSR value. 4140 @param EDX Upper 32-bits of MSR value. 4141 4142 <b>Example usage</b> 4143 @code 4144 UINT64 Msr; 4145 4146 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1); 4147 @endcode 4148 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM. 4149**/ 4150#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 4151 4152 4153/** 4154 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix 4155 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1. 4156 4157 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A) 4158 @param EAX Lower 32-bits of MSR value. 4159 @param EDX Upper 32-bits of MSR value. 4160 4161 <b>Example usage</b> 4162 @code 4163 UINT64 Msr; 4164 4165 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM); 4166 @endcode 4167 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM. 4168**/ 4169#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A 4170 4171 4172/** 4173 Capability Reporting Register of Secondary Processor-based VM-execution 4174 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution 4175 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]). 4176 4177 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B) 4178 @param EAX Lower 32-bits of MSR value. 4179 @param EDX Upper 32-bits of MSR value. 4180 4181 <b>Example usage</b> 4182 @code 4183 UINT64 Msr; 4184 4185 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2); 4186 @endcode 4187 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM. 4188**/ 4189#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B 4190 4191 4192/** 4193 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10, 4194 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C 4195 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ). 4196 4197 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C) 4198 @param EAX Lower 32-bits of MSR value. 4199 @param EDX Upper 32-bits of MSR value. 4200 4201 <b>Example usage</b> 4202 @code 4203 UINT64 Msr; 4204 4205 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP); 4206 @endcode 4207 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM. 4208**/ 4209#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C 4210 4211 4212/** 4213 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O) 4214 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If ( 4215 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4216 4217 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D) 4218 @param EAX Lower 32-bits of MSR value. 4219 @param EDX Upper 32-bits of MSR value. 4220 4221 <b>Example usage</b> 4222 @code 4223 UINT64 Msr; 4224 4225 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS); 4226 @endcode 4227 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM. 4228**/ 4229#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D 4230 4231 4232/** 4233 Capability Reporting Register of Primary Processor-based VM-execution Flex 4234 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution 4235 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4236 4237 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E) 4238 @param EAX Lower 32-bits of MSR value. 4239 @param EDX Upper 32-bits of MSR value. 4240 4241 <b>Example usage</b> 4242 @code 4243 UINT64 Msr; 4244 4245 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS); 4246 @endcode 4247 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM. 4248**/ 4249#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E 4250 4251 4252/** 4253 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix 4254 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4255 4256 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F) 4257 @param EAX Lower 32-bits of MSR value. 4258 @param EDX Upper 32-bits of MSR value. 4259 4260 <b>Example usage</b> 4261 @code 4262 UINT64 Msr; 4263 4264 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS); 4265 @endcode 4266 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM. 4267**/ 4268#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F 4269 4270 4271/** 4272 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix 4273 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4274 4275 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490) 4276 @param EAX Lower 32-bits of MSR value. 4277 @param EDX Upper 32-bits of MSR value. 4278 4279 <b>Example usage</b> 4280 @code 4281 UINT64 Msr; 4282 4283 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS); 4284 @endcode 4285 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM. 4286**/ 4287#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 4288 4289 4290/** 4291 Capability Reporting Register of VMfunction Controls (R/O). If( 4292 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). 4293 4294 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491) 4295 @param EAX Lower 32-bits of MSR value. 4296 @param EDX Upper 32-bits of MSR value. 4297 4298 <b>Example usage</b> 4299 @code 4300 UINT64 Msr; 4301 4302 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC); 4303 @endcode 4304 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM. 4305**/ 4306#define MSR_IA32_VMX_VMFUNC 0x00000491 4307 4308 4309/** 4310 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && 4311 IA32_PERF_CAPABILITIES[ 13] = 1. 4312 4313 @param ECX MSR_IA32_A_PMCn 4314 @param EAX Lower 32-bits of MSR value. 4315 @param EDX Upper 32-bits of MSR value. 4316 4317 <b>Example usage</b> 4318 @code 4319 UINT64 Msr; 4320 4321 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0); 4322 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr); 4323 @endcode 4324 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. 4325 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. 4326 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. 4327 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. 4328 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. 4329 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. 4330 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. 4331 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM. 4332 @{ 4333**/ 4334#define MSR_IA32_A_PMC0 0x000004C1 4335#define MSR_IA32_A_PMC1 0x000004C2 4336#define MSR_IA32_A_PMC2 0x000004C3 4337#define MSR_IA32_A_PMC3 0x000004C4 4338#define MSR_IA32_A_PMC4 0x000004C5 4339#define MSR_IA32_A_PMC5 0x000004C6 4340#define MSR_IA32_A_PMC6 0x000004C7 4341#define MSR_IA32_A_PMC7 0x000004C8 4342/// @} 4343 4344 4345/** 4346 (R/W). If IA32_MCG_CAP.LMCE_P =1. 4347 4348 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0) 4349 @param EAX Lower 32-bits of MSR value. 4350 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER. 4351 @param EDX Upper 32-bits of MSR value. 4352 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER. 4353 4354 <b>Example usage</b> 4355 @code 4356 MSR_IA32_MCG_EXT_CTL_REGISTER Msr; 4357 4358 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL); 4359 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64); 4360 @endcode 4361 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM. 4362**/ 4363#define MSR_IA32_MCG_EXT_CTL 0x000004D0 4364 4365/** 4366 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL 4367**/ 4368typedef union { 4369 /// 4370 /// Individual bit fields 4371 /// 4372 struct { 4373 /// 4374 /// [Bit 0] LMCE_EN. 4375 /// 4376 UINT32 LMCE_EN:1; 4377 UINT32 Reserved1:31; 4378 UINT32 Reserved2:32; 4379 } Bits; 4380 /// 4381 /// All bit fields as a 32-bit value 4382 /// 4383 UINT32 Uint32; 4384 /// 4385 /// All bit fields as a 64-bit value 4386 /// 4387 UINT64 Uint64; 4388} MSR_IA32_MCG_EXT_CTL_REGISTER; 4389 4390 4391/** 4392 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H, 4393 ECX=0H): EBX[2] = 1. 4394 4395 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500) 4396 @param EAX Lower 32-bits of MSR value. 4397 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER. 4398 @param EDX Upper 32-bits of MSR value. 4399 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER. 4400 4401 <b>Example usage</b> 4402 @code 4403 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr; 4404 4405 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS); 4406 @endcode 4407 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM. 4408**/ 4409#define MSR_IA32_SGX_SVN_STATUS 0x00000500 4410 4411/** 4412 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS 4413**/ 4414typedef union { 4415 /// 4416 /// Individual bit fields 4417 /// 4418 struct { 4419 /// 4420 /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated 4421 /// Code Modules (ACMs)". 4422 /// 4423 UINT32 Lock:1; 4424 UINT32 Reserved1:15; 4425 /// 4426 /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with 4427 /// Authenticated Code Modules (ACMs)". 4428 /// 4429 UINT32 SGX_SVN_SINIT:8; 4430 UINT32 Reserved2:8; 4431 UINT32 Reserved3:32; 4432 } Bits; 4433 /// 4434 /// All bit fields as a 32-bit value 4435 /// 4436 UINT32 Uint32; 4437 /// 4438 /// All bit fields as a 64-bit value 4439 /// 4440 UINT64 Uint64; 4441} MSR_IA32_SGX_SVN_STATUS_REGISTER; 4442 4443 4444/** 4445 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1) 4446 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) 4447 ) ). 4448 4449 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560) 4450 @param EAX Lower 32-bits of MSR value. 4451 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER. 4452 @param EDX Upper 32-bits of MSR value. 4453 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER. 4454 4455 <b>Example usage</b> 4456 @code 4457 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr; 4458 4459 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE); 4460 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64); 4461 @endcode 4462 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM. 4463**/ 4464#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 4465 4466/** 4467 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE 4468**/ 4469typedef union { 4470 /// 4471 /// Individual bit fields 4472 /// 4473 struct { 4474 UINT32 Reserved:7; 4475 /// 4476 /// [Bits 31:7] Base physical address. 4477 /// 4478 UINT32 Base:25; 4479 /// 4480 /// [Bits 63:32] Base physical address. 4481 /// 4482 UINT32 BaseHi:32; 4483 } Bits; 4484 /// 4485 /// All bit fields as a 64-bit value 4486 /// 4487 UINT64 Uint64; 4488} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER; 4489 4490 4491/** 4492 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H, 4493 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) 4494 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ). 4495 4496 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561) 4497 @param EAX Lower 32-bits of MSR value. 4498 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER. 4499 @param EDX Upper 32-bits of MSR value. 4500 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER. 4501 4502 <b>Example usage</b> 4503 @code 4504 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr; 4505 4506 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS); 4507 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64); 4508 @endcode 4509 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM. 4510**/ 4511#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561 4512 4513/** 4514 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS 4515**/ 4516typedef union { 4517 /// 4518 /// Individual bit fields 4519 /// 4520 struct { 4521 UINT32 Reserved:7; 4522 /// 4523 /// [Bits 31:7] MaskOrTableOffset. 4524 /// 4525 UINT32 MaskOrTableOffset:25; 4526 /// 4527 /// [Bits 63:32] Output Offset. 4528 /// 4529 UINT32 OutputOffset:32; 4530 } Bits; 4531 /// 4532 /// All bit fields as a 64-bit value 4533 /// 4534 UINT64 Uint64; 4535} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER; 4536 4537 4538/** 4539 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). 4540 4541 @param ECX MSR_IA32_RTIT_CTL (0x00000570) 4542 @param EAX Lower 32-bits of MSR value. 4543 Described by the type MSR_IA32_RTIT_CTL_REGISTER. 4544 @param EDX Upper 32-bits of MSR value. 4545 Described by the type MSR_IA32_RTIT_CTL_REGISTER. 4546 4547 <b>Example usage</b> 4548 @code 4549 MSR_IA32_RTIT_CTL_REGISTER Msr; 4550 4551 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL); 4552 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64); 4553 @endcode 4554 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM. 4555**/ 4556#define MSR_IA32_RTIT_CTL 0x00000570 4557 4558/** 4559 MSR information returned for MSR index #MSR_IA32_RTIT_CTL 4560**/ 4561typedef union { 4562 /// 4563 /// Individual bit fields 4564 /// 4565 struct { 4566 /// 4567 /// [Bit 0] TraceEn. 4568 /// 4569 UINT32 TraceEn:1; 4570 /// 4571 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). 4572 /// 4573 UINT32 CYCEn:1; 4574 /// 4575 /// [Bit 2] OS. 4576 /// 4577 UINT32 OS:1; 4578 /// 4579 /// [Bit 3] User. 4580 /// 4581 UINT32 User:1; 4582 UINT32 Reserved1:2; 4583 /// 4584 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1). 4585 /// 4586 UINT32 FabricEn:1; 4587 /// 4588 /// [Bit 7] CR3 filter. 4589 /// 4590 UINT32 CR3:1; 4591 /// 4592 /// [Bit 8] ToPA. 4593 /// 4594 UINT32 ToPA:1; 4595 /// 4596 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1). 4597 /// 4598 UINT32 MTCEn:1; 4599 /// 4600 /// [Bit 10] TSCEn. 4601 /// 4602 UINT32 TSCEn:1; 4603 /// 4604 /// [Bit 11] DisRETC. 4605 /// 4606 UINT32 DisRETC:1; 4607 UINT32 Reserved2:1; 4608 /// 4609 /// [Bit 13] BranchEn. 4610 /// 4611 UINT32 BranchEn:1; 4612 /// 4613 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1). 4614 /// 4615 UINT32 MTCFreq:4; 4616 UINT32 Reserved3:1; 4617 /// 4618 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). 4619 /// 4620 UINT32 CYCThresh:4; 4621 UINT32 Reserved4:1; 4622 /// 4623 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). 4624 /// 4625 UINT32 PSBFreq:4; 4626 UINT32 Reserved5:4; 4627 /// 4628 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0). 4629 /// 4630 UINT32 ADDR0_CFG:4; 4631 /// 4632 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1). 4633 /// 4634 UINT32 ADDR1_CFG:4; 4635 /// 4636 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2). 4637 /// 4638 UINT32 ADDR2_CFG:4; 4639 /// 4640 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3). 4641 /// 4642 UINT32 ADDR3_CFG:4; 4643 UINT32 Reserved6:16; 4644 } Bits; 4645 /// 4646 /// All bit fields as a 64-bit value 4647 /// 4648 UINT64 Uint64; 4649} MSR_IA32_RTIT_CTL_REGISTER; 4650 4651 4652/** 4653 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). 4654 4655 @param ECX MSR_IA32_RTIT_STATUS (0x00000571) 4656 @param EAX Lower 32-bits of MSR value. 4657 Described by the type MSR_IA32_RTIT_STATUS_REGISTER. 4658 @param EDX Upper 32-bits of MSR value. 4659 Described by the type MSR_IA32_RTIT_STATUS_REGISTER. 4660 4661 <b>Example usage</b> 4662 @code 4663 MSR_IA32_RTIT_STATUS_REGISTER Msr; 4664 4665 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS); 4666 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64); 4667 @endcode 4668 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM. 4669**/ 4670#define MSR_IA32_RTIT_STATUS 0x00000571 4671 4672/** 4673 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS 4674**/ 4675typedef union { 4676 /// 4677 /// Individual bit fields 4678 /// 4679 struct { 4680 /// 4681 /// [Bit 0] FilterEn, (writes ignored). 4682 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1). 4683 /// 4684 UINT32 FilterEn:1; 4685 /// 4686 /// [Bit 1] ContexEn, (writes ignored). 4687 /// 4688 UINT32 ContexEn:1; 4689 /// 4690 /// [Bit 2] TriggerEn, (writes ignored). 4691 /// 4692 UINT32 TriggerEn:1; 4693 UINT32 Reserved1:1; 4694 /// 4695 /// [Bit 4] Error. 4696 /// 4697 UINT32 Error:1; 4698 /// 4699 /// [Bit 5] Stopped. 4700 /// 4701 UINT32 Stopped:1; 4702 UINT32 Reserved2:26; 4703 /// 4704 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3). 4705 /// 4706 UINT32 PacketByteCnt:17; 4707 UINT32 Reserved3:15; 4708 } Bits; 4709 /// 4710 /// All bit fields as a 64-bit value 4711 /// 4712 UINT64 Uint64; 4713} MSR_IA32_RTIT_STATUS_REGISTER; 4714 4715 4716/** 4717 Trace Filter CR3 Match Register (R/W). 4718 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). 4719 4720 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572) 4721 @param EAX Lower 32-bits of MSR value. 4722 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER. 4723 @param EDX Upper 32-bits of MSR value. 4724 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER. 4725 4726 <b>Example usage</b> 4727 @code 4728 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr; 4729 4730 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH); 4731 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64); 4732 @endcode 4733 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM. 4734**/ 4735#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 4736 4737/** 4738 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH 4739**/ 4740typedef union { 4741 /// 4742 /// Individual bit fields 4743 /// 4744 struct { 4745 UINT32 Reserved:5; 4746 /// 4747 /// [Bits 31:5] CR3[63:5] value to match. 4748 /// 4749 UINT32 Cr3:27; 4750 /// 4751 /// [Bits 63:32] CR3[63:5] value to match. 4752 /// 4753 UINT32 Cr3Hi:32; 4754 } Bits; 4755 /// 4756 /// All bit fields as a 64-bit value 4757 /// 4758 UINT64 Uint64; 4759} MSR_IA32_RTIT_CR3_MATCH_REGISTER; 4760 4761 4762/** 4763 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n). 4764 4765 @param ECX MSR_IA32_RTIT_ADDRn_A 4766 @param EAX Lower 32-bits of MSR value. 4767 Described by the type MSR_IA32_RTIT_ADDR_REGISTER. 4768 @param EDX Upper 32-bits of MSR value. 4769 Described by the type MSR_IA32_RTIT_ADDR_REGISTER. 4770 4771 <b>Example usage</b> 4772 @code 4773 MSR_IA32_RTIT_ADDR_REGISTER Msr; 4774 4775 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A); 4776 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64); 4777 @endcode 4778 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM. 4779 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM. 4780 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM. 4781 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM. 4782 @{ 4783**/ 4784#define MSR_IA32_RTIT_ADDR0_A 0x00000580 4785#define MSR_IA32_RTIT_ADDR1_A 0x00000582 4786#define MSR_IA32_RTIT_ADDR2_A 0x00000584 4787#define MSR_IA32_RTIT_ADDR3_A 0x00000586 4788/// @} 4789 4790 4791/** 4792 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n). 4793 4794 @param ECX MSR_IA32_RTIT_ADDRn_B 4795 @param EAX Lower 32-bits of MSR value. 4796 Described by the type MSR_IA32_RTIT_ADDR_REGISTER. 4797 @param EDX Upper 32-bits of MSR value. 4798 Described by the type MSR_IA32_RTIT_ADDR_REGISTER. 4799 4800 <b>Example usage</b> 4801 @code 4802 MSR_IA32_RTIT_ADDR_REGISTER Msr; 4803 4804 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B); 4805 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64); 4806 @endcode 4807 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM. 4808 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM. 4809 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM. 4810 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM. 4811 @{ 4812**/ 4813#define MSR_IA32_RTIT_ADDR0_B 0x00000581 4814#define MSR_IA32_RTIT_ADDR1_B 0x00000583 4815#define MSR_IA32_RTIT_ADDR2_B 0x00000585 4816#define MSR_IA32_RTIT_ADDR3_B 0x00000587 4817/// @} 4818 4819 4820/** 4821 MSR information returned for MSR indexes 4822 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and 4823 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B 4824**/ 4825typedef union { 4826 /// 4827 /// Individual bit fields 4828 /// 4829 struct { 4830 /// 4831 /// [Bits 31:0] Virtual Address. 4832 /// 4833 UINT32 VirtualAddress:32; 4834 /// 4835 /// [Bits 47:32] Virtual Address. 4836 /// 4837 UINT32 VirtualAddressHi:16; 4838 /// 4839 /// [Bits 63:48] SignExt_VA. 4840 /// 4841 UINT32 SignExt_VA:16; 4842 } Bits; 4843 /// 4844 /// All bit fields as a 64-bit value 4845 /// 4846 UINT64 Uint64; 4847} MSR_IA32_RTIT_ADDR_REGISTER; 4848 4849 4850/** 4851 DS Save Area (R/W) Points to the linear address of the first byte of the DS 4852 buffer management area, which is used to manage the BTS and PEBS buffers. 4853 See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21] 4854 = 1. 4855 4856 [Bits 31..0] The linear address of the first byte of the DS buffer 4857 management area, if not in IA-32e mode. 4858 4859 [Bits 63..0] The linear address of the first byte of the DS buffer 4860 management area, if IA-32e mode is active. 4861 4862 @param ECX MSR_IA32_DS_AREA (0x00000600) 4863 @param EAX Lower 32-bits of MSR value. 4864 Described by the type MSR_IA32_DS_AREA_REGISTER. 4865 @param EDX Upper 32-bits of MSR value. 4866 Described by the type MSR_IA32_DS_AREA_REGISTER. 4867 4868 <b>Example usage</b> 4869 @code 4870 UINT64 Msr; 4871 4872 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA); 4873 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr); 4874 @endcode 4875 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM. 4876**/ 4877#define MSR_IA32_DS_AREA 0x00000600 4878 4879 4880/** 4881 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] = 4882 1. 4883 4884 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0) 4885 @param EAX Lower 32-bits of MSR value. 4886 @param EDX Upper 32-bits of MSR value. 4887 4888 <b>Example usage</b> 4889 @code 4890 UINT64 Msr; 4891 4892 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE); 4893 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr); 4894 @endcode 4895 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM. 4896**/ 4897#define MSR_IA32_TSC_DEADLINE 0x000006E0 4898 4899 4900/** 4901 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1. 4902 4903 @param ECX MSR_IA32_PM_ENABLE (0x00000770) 4904 @param EAX Lower 32-bits of MSR value. 4905 Described by the type MSR_IA32_PM_ENABLE_REGISTER. 4906 @param EDX Upper 32-bits of MSR value. 4907 Described by the type MSR_IA32_PM_ENABLE_REGISTER. 4908 4909 <b>Example usage</b> 4910 @code 4911 MSR_IA32_PM_ENABLE_REGISTER Msr; 4912 4913 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE); 4914 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64); 4915 @endcode 4916 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM. 4917**/ 4918#define MSR_IA32_PM_ENABLE 0x00000770 4919 4920/** 4921 MSR information returned for MSR index #MSR_IA32_PM_ENABLE 4922**/ 4923typedef union { 4924 /// 4925 /// Individual bit fields 4926 /// 4927 struct { 4928 /// 4929 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If 4930 /// CPUID.06H:EAX.[7] = 1. 4931 /// 4932 UINT32 HWP_ENABLE:1; 4933 UINT32 Reserved1:31; 4934 UINT32 Reserved2:32; 4935 } Bits; 4936 /// 4937 /// All bit fields as a 32-bit value 4938 /// 4939 UINT32 Uint32; 4940 /// 4941 /// All bit fields as a 64-bit value 4942 /// 4943 UINT64 Uint64; 4944} MSR_IA32_PM_ENABLE_REGISTER; 4945 4946 4947/** 4948 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1. 4949 4950 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771) 4951 @param EAX Lower 32-bits of MSR value. 4952 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER. 4953 @param EDX Upper 32-bits of MSR value. 4954 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER. 4955 4956 <b>Example usage</b> 4957 @code 4958 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr; 4959 4960 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES); 4961 @endcode 4962 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM. 4963**/ 4964#define MSR_IA32_HWP_CAPABILITIES 0x00000771 4965 4966/** 4967 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES 4968**/ 4969typedef union { 4970 /// 4971 /// Individual bit fields 4972 /// 4973 struct { 4974 /// 4975 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance 4976 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. 4977 /// 4978 UINT32 Highest_Performance:8; 4979 /// 4980 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP 4981 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. 4982 /// 4983 UINT32 Guaranteed_Performance:8; 4984 /// 4985 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP 4986 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. 4987 /// 4988 UINT32 Most_Efficient_Performance:8; 4989 /// 4990 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance 4991 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. 4992 /// 4993 UINT32 Lowest_Performance:8; 4994 UINT32 Reserved:32; 4995 } Bits; 4996 /// 4997 /// All bit fields as a 32-bit value 4998 /// 4999 UINT32 Uint32; 5000 /// 5001 /// All bit fields as a 64-bit value 5002 /// 5003 UINT64 Uint64; 5004} MSR_IA32_HWP_CAPABILITIES_REGISTER; 5005 5006 5007/** 5008 Power Management Control Hints for All Logical Processors in a Package 5009 (R/W). If CPUID.06H:EAX.[11] = 1. 5010 5011 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772) 5012 @param EAX Lower 32-bits of MSR value. 5013 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER. 5014 @param EDX Upper 32-bits of MSR value. 5015 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER. 5016 5017 <b>Example usage</b> 5018 @code 5019 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr; 5020 5021 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG); 5022 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64); 5023 @endcode 5024 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM. 5025**/ 5026#define MSR_IA32_HWP_REQUEST_PKG 0x00000772 5027 5028/** 5029 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG 5030**/ 5031typedef union { 5032 /// 5033 /// Individual bit fields 5034 /// 5035 struct { 5036 /// 5037 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If 5038 /// CPUID.06H:EAX.[11] = 1. 5039 /// 5040 UINT32 Minimum_Performance:8; 5041 /// 5042 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If 5043 /// CPUID.06H:EAX.[11] = 1. 5044 /// 5045 UINT32 Maximum_Performance:8; 5046 /// 5047 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". 5048 /// If CPUID.06H:EAX.[11] = 1. 5049 /// 5050 UINT32 Desired_Performance:8; 5051 /// 5052 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4, 5053 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1. 5054 /// 5055 UINT32 Energy_Performance_Preference:8; 5056 /// 5057 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If 5058 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1. 5059 /// 5060 UINT32 Activity_Window:10; 5061 UINT32 Reserved:22; 5062 } Bits; 5063 /// 5064 /// All bit fields as a 64-bit value 5065 /// 5066 UINT64 Uint64; 5067} MSR_IA32_HWP_REQUEST_PKG_REGISTER; 5068 5069 5070/** 5071 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1. 5072 5073 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773) 5074 @param EAX Lower 32-bits of MSR value. 5075 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER. 5076 @param EDX Upper 32-bits of MSR value. 5077 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER. 5078 5079 <b>Example usage</b> 5080 @code 5081 MSR_IA32_HWP_INTERRUPT_REGISTER Msr; 5082 5083 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT); 5084 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64); 5085 @endcode 5086 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM. 5087**/ 5088#define MSR_IA32_HWP_INTERRUPT 0x00000773 5089 5090/** 5091 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT 5092**/ 5093typedef union { 5094 /// 5095 /// Individual bit fields 5096 /// 5097 struct { 5098 /// 5099 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP 5100 /// Notifications". If CPUID.06H:EAX.[8] = 1. 5101 /// 5102 UINT32 EN_Guaranteed_Performance_Change:1; 5103 /// 5104 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications". 5105 /// If CPUID.06H:EAX.[8] = 1. 5106 /// 5107 UINT32 EN_Excursion_Minimum:1; 5108 UINT32 Reserved1:30; 5109 UINT32 Reserved2:32; 5110 } Bits; 5111 /// 5112 /// All bit fields as a 32-bit value 5113 /// 5114 UINT32 Uint32; 5115 /// 5116 /// All bit fields as a 64-bit value 5117 /// 5118 UINT64 Uint64; 5119} MSR_IA32_HWP_INTERRUPT_REGISTER; 5120 5121 5122/** 5123 Power Management Control Hints to a Logical Processor (R/W). If 5124 CPUID.06H:EAX.[7] = 1. 5125 5126 @param ECX MSR_IA32_HWP_REQUEST (0x00000774) 5127 @param EAX Lower 32-bits of MSR value. 5128 Described by the type MSR_IA32_HWP_REQUEST_REGISTER. 5129 @param EDX Upper 32-bits of MSR value. 5130 Described by the type MSR_IA32_HWP_REQUEST_REGISTER. 5131 5132 <b>Example usage</b> 5133 @code 5134 MSR_IA32_HWP_REQUEST_REGISTER Msr; 5135 5136 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST); 5137 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64); 5138 @endcode 5139 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM. 5140**/ 5141#define MSR_IA32_HWP_REQUEST 0x00000774 5142 5143/** 5144 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST 5145**/ 5146typedef union { 5147 /// 5148 /// Individual bit fields 5149 /// 5150 struct { 5151 /// 5152 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If 5153 /// CPUID.06H:EAX.[7] = 1. 5154 /// 5155 UINT32 Minimum_Performance:8; 5156 /// 5157 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If 5158 /// CPUID.06H:EAX.[7] = 1. 5159 /// 5160 UINT32 Maximum_Performance:8; 5161 /// 5162 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". 5163 /// If CPUID.06H:EAX.[7] = 1. 5164 /// 5165 UINT32 Desired_Performance:8; 5166 /// 5167 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4, 5168 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1. 5169 /// 5170 UINT32 Energy_Performance_Preference:8; 5171 /// 5172 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If 5173 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1. 5174 /// 5175 UINT32 Activity_Window:10; 5176 /// 5177 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If 5178 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1. 5179 /// 5180 UINT32 Package_Control:1; 5181 UINT32 Reserved:21; 5182 } Bits; 5183 /// 5184 /// All bit fields as a 64-bit value 5185 /// 5186 UINT64 Uint64; 5187} MSR_IA32_HWP_REQUEST_REGISTER; 5188 5189 5190/** 5191 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If 5192 CPUID.06H:EAX.[7] = 1. 5193 5194 @param ECX MSR_IA32_HWP_STATUS (0x00000777) 5195 @param EAX Lower 32-bits of MSR value. 5196 Described by the type MSR_IA32_HWP_STATUS_REGISTER. 5197 @param EDX Upper 32-bits of MSR value. 5198 Described by the type MSR_IA32_HWP_STATUS_REGISTER. 5199 5200 <b>Example usage</b> 5201 @code 5202 MSR_IA32_HWP_STATUS_REGISTER Msr; 5203 5204 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS); 5205 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64); 5206 @endcode 5207 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM. 5208**/ 5209#define MSR_IA32_HWP_STATUS 0x00000777 5210 5211/** 5212 MSR information returned for MSR index #MSR_IA32_HWP_STATUS 5213**/ 5214typedef union { 5215 /// 5216 /// Individual bit fields 5217 /// 5218 struct { 5219 /// 5220 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5, 5221 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1. 5222 /// 5223 UINT32 Guaranteed_Performance_Change:1; 5224 UINT32 Reserved1:1; 5225 /// 5226 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP 5227 /// Feedback". If CPUID.06H:EAX.[7] = 1. 5228 /// 5229 UINT32 Excursion_To_Minimum:1; 5230 UINT32 Reserved2:29; 5231 UINT32 Reserved3:32; 5232 } Bits; 5233 /// 5234 /// All bit fields as a 32-bit value 5235 /// 5236 UINT32 Uint32; 5237 /// 5238 /// All bit fields as a 64-bit value 5239 /// 5240 UINT64 Uint64; 5241} MSR_IA32_HWP_STATUS_REGISTER; 5242 5243 5244/** 5245 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1 5246 && IA32_APIC_BASE.[10] = 1. 5247 5248 @param ECX MSR_IA32_X2APIC_APICID (0x00000802) 5249 @param EAX Lower 32-bits of MSR value. 5250 @param EDX Upper 32-bits of MSR value. 5251 5252 <b>Example usage</b> 5253 @code 5254 UINT64 Msr; 5255 5256 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID); 5257 @endcode 5258 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM. 5259**/ 5260#define MSR_IA32_X2APIC_APICID 0x00000802 5261 5262 5263/** 5264 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 && 5265 IA32_APIC_BASE.[10] = 1. 5266 5267 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803) 5268 @param EAX Lower 32-bits of MSR value. 5269 @param EDX Upper 32-bits of MSR value. 5270 5271 <b>Example usage</b> 5272 @code 5273 UINT64 Msr; 5274 5275 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION); 5276 @endcode 5277 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM. 5278**/ 5279#define MSR_IA32_X2APIC_VERSION 0x00000803 5280 5281 5282/** 5283 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5284 IA32_APIC_BASE.[10] = 1. 5285 5286 @param ECX MSR_IA32_X2APIC_TPR (0x00000808) 5287 @param EAX Lower 32-bits of MSR value. 5288 @param EDX Upper 32-bits of MSR value. 5289 5290 <b>Example usage</b> 5291 @code 5292 UINT64 Msr; 5293 5294 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR); 5295 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr); 5296 @endcode 5297 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM. 5298**/ 5299#define MSR_IA32_X2APIC_TPR 0x00000808 5300 5301 5302/** 5303 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 && 5304 IA32_APIC_BASE.[10] = 1. 5305 5306 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A) 5307 @param EAX Lower 32-bits of MSR value. 5308 @param EDX Upper 32-bits of MSR value. 5309 5310 <b>Example usage</b> 5311 @code 5312 UINT64 Msr; 5313 5314 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR); 5315 @endcode 5316 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM. 5317**/ 5318#define MSR_IA32_X2APIC_PPR 0x0000080A 5319 5320 5321/** 5322 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] 5323 = 1. 5324 5325 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B) 5326 @param EAX Lower 32-bits of MSR value. 5327 @param EDX Upper 32-bits of MSR value. 5328 5329 <b>Example usage</b> 5330 @code 5331 UINT64 Msr; 5332 5333 Msr = 0; 5334 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr); 5335 @endcode 5336 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM. 5337**/ 5338#define MSR_IA32_X2APIC_EOI 0x0000080B 5339 5340 5341/** 5342 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 && 5343 IA32_APIC_BASE.[10] = 1. 5344 5345 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D) 5346 @param EAX Lower 32-bits of MSR value. 5347 @param EDX Upper 32-bits of MSR value. 5348 5349 <b>Example usage</b> 5350 @code 5351 UINT64 Msr; 5352 5353 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR); 5354 @endcode 5355 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM. 5356**/ 5357#define MSR_IA32_X2APIC_LDR 0x0000080D 5358 5359 5360/** 5361 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1 5362 && IA32_APIC_BASE.[10] = 1. 5363 5364 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F) 5365 @param EAX Lower 32-bits of MSR value. 5366 @param EDX Upper 32-bits of MSR value. 5367 5368 <b>Example usage</b> 5369 @code 5370 UINT64 Msr; 5371 5372 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR); 5373 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr); 5374 @endcode 5375 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM. 5376**/ 5377#define MSR_IA32_X2APIC_SIVR 0x0000080F 5378 5379 5380/** 5381 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). 5382 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5383 5384 @param ECX MSR_IA32_X2APIC_ISRn 5385 @param EAX Lower 32-bits of MSR value. 5386 @param EDX Upper 32-bits of MSR value. 5387 5388 <b>Example usage</b> 5389 @code 5390 UINT64 Msr; 5391 5392 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0); 5393 @endcode 5394 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. 5395 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. 5396 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. 5397 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. 5398 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. 5399 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. 5400 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. 5401 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM. 5402 @{ 5403**/ 5404#define MSR_IA32_X2APIC_ISR0 0x00000810 5405#define MSR_IA32_X2APIC_ISR1 0x00000811 5406#define MSR_IA32_X2APIC_ISR2 0x00000812 5407#define MSR_IA32_X2APIC_ISR3 0x00000813 5408#define MSR_IA32_X2APIC_ISR4 0x00000814 5409#define MSR_IA32_X2APIC_ISR5 0x00000815 5410#define MSR_IA32_X2APIC_ISR6 0x00000816 5411#define MSR_IA32_X2APIC_ISR7 0x00000817 5412/// @} 5413 5414 5415/** 5416 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). 5417 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5418 5419 @param ECX MSR_IA32_X2APIC_TMRn 5420 @param EAX Lower 32-bits of MSR value. 5421 @param EDX Upper 32-bits of MSR value. 5422 5423 <b>Example usage</b> 5424 @code 5425 UINT64 Msr; 5426 5427 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0); 5428 @endcode 5429 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. 5430 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. 5431 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. 5432 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. 5433 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. 5434 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. 5435 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. 5436 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM. 5437 @{ 5438**/ 5439#define MSR_IA32_X2APIC_TMR0 0x00000818 5440#define MSR_IA32_X2APIC_TMR1 0x00000819 5441#define MSR_IA32_X2APIC_TMR2 0x0000081A 5442#define MSR_IA32_X2APIC_TMR3 0x0000081B 5443#define MSR_IA32_X2APIC_TMR4 0x0000081C 5444#define MSR_IA32_X2APIC_TMR5 0x0000081D 5445#define MSR_IA32_X2APIC_TMR6 0x0000081E 5446#define MSR_IA32_X2APIC_TMR7 0x0000081F 5447/// @} 5448 5449 5450/** 5451 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). 5452 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5453 5454 @param ECX MSR_IA32_X2APIC_IRRn 5455 @param EAX Lower 32-bits of MSR value. 5456 @param EDX Upper 32-bits of MSR value. 5457 5458 <b>Example usage</b> 5459 @code 5460 UINT64 Msr; 5461 5462 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0); 5463 @endcode 5464 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. 5465 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. 5466 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. 5467 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. 5468 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. 5469 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. 5470 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. 5471 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM. 5472 @{ 5473**/ 5474#define MSR_IA32_X2APIC_IRR0 0x00000820 5475#define MSR_IA32_X2APIC_IRR1 0x00000821 5476#define MSR_IA32_X2APIC_IRR2 0x00000822 5477#define MSR_IA32_X2APIC_IRR3 0x00000823 5478#define MSR_IA32_X2APIC_IRR4 0x00000824 5479#define MSR_IA32_X2APIC_IRR5 0x00000825 5480#define MSR_IA32_X2APIC_IRR6 0x00000826 5481#define MSR_IA32_X2APIC_IRR7 0x00000827 5482/// @} 5483 5484 5485/** 5486 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5487 IA32_APIC_BASE.[10] = 1. 5488 5489 @param ECX MSR_IA32_X2APIC_ESR (0x00000828) 5490 @param EAX Lower 32-bits of MSR value. 5491 @param EDX Upper 32-bits of MSR value. 5492 5493 <b>Example usage</b> 5494 @code 5495 UINT64 Msr; 5496 5497 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR); 5498 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr); 5499 @endcode 5500 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM. 5501**/ 5502#define MSR_IA32_X2APIC_ESR 0x00000828 5503 5504 5505/** 5506 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If 5507 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5508 5509 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F) 5510 @param EAX Lower 32-bits of MSR value. 5511 @param EDX Upper 32-bits of MSR value. 5512 5513 <b>Example usage</b> 5514 @code 5515 UINT64 Msr; 5516 5517 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI); 5518 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr); 5519 @endcode 5520 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM. 5521**/ 5522#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F 5523 5524 5525/** 5526 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5527 IA32_APIC_BASE.[10] = 1. 5528 5529 @param ECX MSR_IA32_X2APIC_ICR (0x00000830) 5530 @param EAX Lower 32-bits of MSR value. 5531 @param EDX Upper 32-bits of MSR value. 5532 5533 <b>Example usage</b> 5534 @code 5535 UINT64 Msr; 5536 5537 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR); 5538 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr); 5539 @endcode 5540 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM. 5541**/ 5542#define MSR_IA32_X2APIC_ICR 0x00000830 5543 5544 5545/** 5546 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5547 IA32_APIC_BASE.[10] = 1. 5548 5549 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832) 5550 @param EAX Lower 32-bits of MSR value. 5551 @param EDX Upper 32-bits of MSR value. 5552 5553 <b>Example usage</b> 5554 @code 5555 UINT64 Msr; 5556 5557 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER); 5558 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr); 5559 @endcode 5560 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM. 5561**/ 5562#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832 5563 5564 5565/** 5566 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 5567 1 && IA32_APIC_BASE.[10] = 1. 5568 5569 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833) 5570 @param EAX Lower 32-bits of MSR value. 5571 @param EDX Upper 32-bits of MSR value. 5572 5573 <b>Example usage</b> 5574 @code 5575 UINT64 Msr; 5576 5577 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL); 5578 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr); 5579 @endcode 5580 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM. 5581**/ 5582#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833 5583 5584 5585/** 5586 x2APIC LVT Performance Monitor Interrupt Register (R/W). If 5587 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. 5588 5589 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834) 5590 @param EAX Lower 32-bits of MSR value. 5591 @param EDX Upper 32-bits of MSR value. 5592 5593 <b>Example usage</b> 5594 @code 5595 UINT64 Msr; 5596 5597 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI); 5598 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr); 5599 @endcode 5600 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM. 5601**/ 5602#define MSR_IA32_X2APIC_LVT_PMI 0x00000834 5603 5604 5605/** 5606 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5607 IA32_APIC_BASE.[10] = 1. 5608 5609 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835) 5610 @param EAX Lower 32-bits of MSR value. 5611 @param EDX Upper 32-bits of MSR value. 5612 5613 <b>Example usage</b> 5614 @code 5615 UINT64 Msr; 5616 5617 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0); 5618 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr); 5619 @endcode 5620 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM. 5621**/ 5622#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835 5623 5624 5625/** 5626 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5627 IA32_APIC_BASE.[10] = 1. 5628 5629 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836) 5630 @param EAX Lower 32-bits of MSR value. 5631 @param EDX Upper 32-bits of MSR value. 5632 5633 <b>Example usage</b> 5634 @code 5635 UINT64 Msr; 5636 5637 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1); 5638 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr); 5639 @endcode 5640 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM. 5641**/ 5642#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836 5643 5644 5645/** 5646 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5647 IA32_APIC_BASE.[10] = 1. 5648 5649 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837) 5650 @param EAX Lower 32-bits of MSR value. 5651 @param EDX Upper 32-bits of MSR value. 5652 5653 <b>Example usage</b> 5654 @code 5655 UINT64 Msr; 5656 5657 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR); 5658 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr); 5659 @endcode 5660 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM. 5661**/ 5662#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837 5663 5664 5665/** 5666 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5667 IA32_APIC_BASE.[10] = 1. 5668 5669 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838) 5670 @param EAX Lower 32-bits of MSR value. 5671 @param EDX Upper 32-bits of MSR value. 5672 5673 <b>Example usage</b> 5674 @code 5675 UINT64 Msr; 5676 5677 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT); 5678 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr); 5679 @endcode 5680 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM. 5681**/ 5682#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838 5683 5684 5685/** 5686 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 && 5687 IA32_APIC_BASE.[10] = 1. 5688 5689 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839) 5690 @param EAX Lower 32-bits of MSR value. 5691 @param EDX Upper 32-bits of MSR value. 5692 5693 <b>Example usage</b> 5694 @code 5695 UINT64 Msr; 5696 5697 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT); 5698 @endcode 5699 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM. 5700**/ 5701#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839 5702 5703 5704/** 5705 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 && 5706 IA32_APIC_BASE.[10] = 1. 5707 5708 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E) 5709 @param EAX Lower 32-bits of MSR value. 5710 @param EDX Upper 32-bits of MSR value. 5711 5712 <b>Example usage</b> 5713 @code 5714 UINT64 Msr; 5715 5716 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF); 5717 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr); 5718 @endcode 5719 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM. 5720**/ 5721#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E 5722 5723 5724/** 5725 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 && 5726 IA32_APIC_BASE.[10] = 1. 5727 5728 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F) 5729 @param EAX Lower 32-bits of MSR value. 5730 @param EDX Upper 32-bits of MSR value. 5731 5732 <b>Example usage</b> 5733 @code 5734 UINT64 Msr; 5735 5736 Msr = 0; 5737 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr); 5738 @endcode 5739 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM. 5740**/ 5741#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F 5742 5743 5744/** 5745 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1. 5746 5747 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80) 5748 @param EAX Lower 32-bits of MSR value. 5749 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER. 5750 @param EDX Upper 32-bits of MSR value. 5751 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER. 5752 5753 <b>Example usage</b> 5754 @code 5755 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr; 5756 5757 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE); 5758 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64); 5759 @endcode 5760 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM. 5761**/ 5762#define MSR_IA32_DEBUG_INTERFACE 0x00000C80 5763 5764/** 5765 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE 5766**/ 5767typedef union { 5768 /// 5769 /// Individual bit fields 5770 /// 5771 struct { 5772 /// 5773 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features. 5774 /// Default is 0. If CPUID.01H:ECX.[11] = 1. 5775 /// 5776 UINT32 Enable:1; 5777 UINT32 Reserved1:29; 5778 /// 5779 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The 5780 /// lock bit is set automatically on the first SMI assertion even if not 5781 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1. 5782 /// 5783 UINT32 Lock:1; 5784 /// 5785 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to 5786 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1. 5787 /// 5788 UINT32 DebugOccurred:1; 5789 UINT32 Reserved2:32; 5790 } Bits; 5791 /// 5792 /// All bit fields as a 32-bit value 5793 /// 5794 UINT32 Uint32; 5795 /// 5796 /// All bit fields as a 64-bit value 5797 /// 5798 UINT64 Uint64; 5799} MSR_IA32_DEBUG_INTERFACE_REGISTER; 5800 5801 5802/** 5803 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ). 5804 5805 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81) 5806 @param EAX Lower 32-bits of MSR value. 5807 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER. 5808 @param EDX Upper 32-bits of MSR value. 5809 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER. 5810 5811 <b>Example usage</b> 5812 @code 5813 MSR_IA32_L3_QOS_CFG_REGISTER Msr; 5814 5815 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG); 5816 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64); 5817 @endcode 5818 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM. 5819**/ 5820#define MSR_IA32_L3_QOS_CFG 0x00000C81 5821 5822/** 5823 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG 5824**/ 5825typedef union { 5826 /// 5827 /// Individual bit fields 5828 /// 5829 struct { 5830 /// 5831 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate 5832 /// in Code and Data Prioritization (CDP) mode. 5833 /// 5834 UINT32 Enable:1; 5835 UINT32 Reserved1:31; 5836 UINT32 Reserved2:32; 5837 } Bits; 5838 /// 5839 /// All bit fields as a 32-bit value 5840 /// 5841 UINT32 Uint32; 5842 /// 5843 /// All bit fields as a 64-bit value 5844 /// 5845 UINT64 Uint64; 5846} MSR_IA32_L3_QOS_CFG_REGISTER; 5847 5848 5849/** 5850 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] 5851 = 1 ). 5852 5853 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D) 5854 @param EAX Lower 32-bits of MSR value. 5855 Described by the type MSR_IA32_QM_EVTSEL_REGISTER. 5856 @param EDX Upper 32-bits of MSR value. 5857 Described by the type MSR_IA32_QM_EVTSEL_REGISTER. 5858 5859 <b>Example usage</b> 5860 @code 5861 MSR_IA32_QM_EVTSEL_REGISTER Msr; 5862 5863 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL); 5864 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64); 5865 @endcode 5866 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM. 5867**/ 5868#define MSR_IA32_QM_EVTSEL 0x00000C8D 5869 5870/** 5871 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL 5872**/ 5873typedef union { 5874 /// 5875 /// Individual bit fields 5876 /// 5877 struct { 5878 /// 5879 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via 5880 /// IA32_QM_CTR. 5881 /// 5882 UINT32 EventID:8; 5883 UINT32 Reserved:24; 5884 /// 5885 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to 5886 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` ( 5887 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)). 5888 /// 5889 UINT32 ResourceMonitoringID:32; 5890 } Bits; 5891 /// 5892 /// All bit fields as a 64-bit value 5893 /// 5894 UINT64 Uint64; 5895} MSR_IA32_QM_EVTSEL_REGISTER; 5896 5897 5898/** 5899 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1 5900 ). 5901 5902 @param ECX MSR_IA32_QM_CTR (0x00000C8E) 5903 @param EAX Lower 32-bits of MSR value. 5904 Described by the type MSR_IA32_QM_CTR_REGISTER. 5905 @param EDX Upper 32-bits of MSR value. 5906 Described by the type MSR_IA32_QM_CTR_REGISTER. 5907 5908 <b>Example usage</b> 5909 @code 5910 MSR_IA32_QM_CTR_REGISTER Msr; 5911 5912 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR); 5913 @endcode 5914 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM. 5915**/ 5916#define MSR_IA32_QM_CTR 0x00000C8E 5917 5918/** 5919 MSR information returned for MSR index #MSR_IA32_QM_CTR 5920**/ 5921typedef union { 5922 /// 5923 /// Individual bit fields 5924 /// 5925 struct { 5926 /// 5927 /// [Bits 31:0] Resource Monitored Data. 5928 /// 5929 UINT32 ResourceMonitoredData:32; 5930 /// 5931 /// [Bits 61:32] Resource Monitored Data. 5932 /// 5933 UINT32 ResourceMonitoredDataHi:30; 5934 /// 5935 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not 5936 /// available or not monitored for this resource or RMID. 5937 /// 5938 UINT32 Unavailable:1; 5939 /// 5940 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was 5941 /// written to IA32_PQR_QM_EVTSEL. 5942 /// 5943 UINT32 Error:1; 5944 } Bits; 5945 /// 5946 /// All bit fields as a 64-bit value 5947 /// 5948 UINT64 Uint64; 5949} MSR_IA32_QM_CTR_REGISTER; 5950 5951 5952/** 5953 Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12] 5954 =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ). 5955 5956 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F) 5957 @param EAX Lower 32-bits of MSR value. 5958 Described by the type MSR_IA32_PQR_ASSOC_REGISTER. 5959 @param EDX Upper 32-bits of MSR value. 5960 Described by the type MSR_IA32_PQR_ASSOC_REGISTER. 5961 5962 <b>Example usage</b> 5963 @code 5964 MSR_IA32_PQR_ASSOC_REGISTER Msr; 5965 5966 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC); 5967 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64); 5968 @endcode 5969 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. 5970**/ 5971#define MSR_IA32_PQR_ASSOC 0x00000C8F 5972 5973/** 5974 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC 5975**/ 5976typedef union { 5977 /// 5978 /// Individual bit fields 5979 /// 5980 struct { 5981 /// 5982 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware 5983 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2` 5984 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)). 5985 /// 5986 UINT32 ResourceMonitoringID:32; 5987 /// 5988 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on 5989 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H, 5990 /// ECX=0):EBX.[15] = 1 ). 5991 /// 5992 UINT32 COS:32; 5993 } Bits; 5994 /// 5995 /// All bit fields as a 64-bit value 5996 /// 5997 UINT64 Uint64; 5998} MSR_IA32_PQR_ASSOC_REGISTER; 5999 6000 6001/** 6002 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H, 6003 ECX=0H):EBX[14] = 1). 6004 6005 @param ECX MSR_IA32_BNDCFGS (0x00000D90) 6006 @param EAX Lower 32-bits of MSR value. 6007 Described by the type MSR_IA32_BNDCFGS_REGISTER. 6008 @param EDX Upper 32-bits of MSR value. 6009 Described by the type MSR_IA32_BNDCFGS_REGISTER. 6010 6011 <b>Example usage</b> 6012 @code 6013 MSR_IA32_BNDCFGS_REGISTER Msr; 6014 6015 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS); 6016 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64); 6017 @endcode 6018 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM. 6019**/ 6020#define MSR_IA32_BNDCFGS 0x00000D90 6021 6022/** 6023 MSR information returned for MSR index #MSR_IA32_BNDCFGS 6024**/ 6025typedef union { 6026 /// 6027 /// Individual bit fields 6028 /// 6029 struct { 6030 /// 6031 /// [Bit 0] EN: Enable Intel MPX in supervisor mode. 6032 /// 6033 UINT32 EN:1; 6034 /// 6035 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch 6036 /// instructions in the absence of the BND prefix. 6037 /// 6038 UINT32 BNDPRESERVE:1; 6039 UINT32 Reserved:10; 6040 /// 6041 /// [Bits 31:12] Base Address of Bound Directory. 6042 /// 6043 UINT32 Base:20; 6044 /// 6045 /// [Bits 63:32] Base Address of Bound Directory. 6046 /// 6047 UINT32 BaseHi:32; 6048 } Bits; 6049 /// 6050 /// All bit fields as a 64-bit value 6051 /// 6052 UINT64 Uint64; 6053} MSR_IA32_BNDCFGS_REGISTER; 6054 6055 6056/** 6057 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1. 6058 6059 @param ECX MSR_IA32_XSS (0x00000DA0) 6060 @param EAX Lower 32-bits of MSR value. 6061 Described by the type MSR_IA32_XSS_REGISTER. 6062 @param EDX Upper 32-bits of MSR value. 6063 Described by the type MSR_IA32_XSS_REGISTER. 6064 6065 <b>Example usage</b> 6066 @code 6067 MSR_IA32_XSS_REGISTER Msr; 6068 6069 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS); 6070 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64); 6071 @endcode 6072 @note MSR_IA32_XSS is defined as IA32_XSS in SDM. 6073**/ 6074#define MSR_IA32_XSS 0x00000DA0 6075 6076/** 6077 MSR information returned for MSR index #MSR_IA32_XSS 6078**/ 6079typedef union { 6080 /// 6081 /// Individual bit fields 6082 /// 6083 struct { 6084 UINT32 Reserved1:8; 6085 /// 6086 /// [Bit 8] Trace Packet Configuration State (R/W). 6087 /// 6088 UINT32 TracePacketConfigurationState:1; 6089 UINT32 Reserved2:23; 6090 UINT32 Reserved3:32; 6091 } Bits; 6092 /// 6093 /// All bit fields as a 32-bit value 6094 /// 6095 UINT32 Uint32; 6096 /// 6097 /// All bit fields as a 64-bit value 6098 /// 6099 UINT64 Uint64; 6100} MSR_IA32_XSS_REGISTER; 6101 6102 6103/** 6104 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1. 6105 6106 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0) 6107 @param EAX Lower 32-bits of MSR value. 6108 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER. 6109 @param EDX Upper 32-bits of MSR value. 6110 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER. 6111 6112 <b>Example usage</b> 6113 @code 6114 MSR_IA32_PKG_HDC_CTL_REGISTER Msr; 6115 6116 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL); 6117 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64); 6118 @endcode 6119 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM. 6120**/ 6121#define MSR_IA32_PKG_HDC_CTL 0x00000DB0 6122 6123/** 6124 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL 6125**/ 6126typedef union { 6127 /// 6128 /// Individual bit fields 6129 /// 6130 struct { 6131 /// 6132 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled 6133 /// logical processors in the package. See Section 14.5.2, "Package level 6134 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1. 6135 /// 6136 UINT32 HDC_Pkg_Enable:1; 6137 UINT32 Reserved1:31; 6138 UINT32 Reserved2:32; 6139 } Bits; 6140 /// 6141 /// All bit fields as a 32-bit value 6142 /// 6143 UINT32 Uint32; 6144 /// 6145 /// All bit fields as a 64-bit value 6146 /// 6147 UINT64 Uint64; 6148} MSR_IA32_PKG_HDC_CTL_REGISTER; 6149 6150 6151/** 6152 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1. 6153 6154 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1) 6155 @param EAX Lower 32-bits of MSR value. 6156 Described by the type MSR_IA32_PM_CTL1_REGISTER. 6157 @param EDX Upper 32-bits of MSR value. 6158 Described by the type MSR_IA32_PM_CTL1_REGISTER. 6159 6160 <b>Example usage</b> 6161 @code 6162 MSR_IA32_PM_CTL1_REGISTER Msr; 6163 6164 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1); 6165 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64); 6166 @endcode 6167 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM. 6168**/ 6169#define MSR_IA32_PM_CTL1 0x00000DB1 6170 6171/** 6172 MSR information returned for MSR index #MSR_IA32_PM_CTL1 6173**/ 6174typedef union { 6175 /// 6176 /// Individual bit fields 6177 /// 6178 struct { 6179 /// 6180 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for 6181 /// package level HDC control. See Section 14.5.3. 6182 /// If CPUID.06H:EAX.[13] = 1. 6183 /// 6184 UINT32 HDC_Allow_Block:1; 6185 UINT32 Reserved1:31; 6186 UINT32 Reserved2:32; 6187 } Bits; 6188 /// 6189 /// All bit fields as a 32-bit value 6190 /// 6191 UINT32 Uint32; 6192 /// 6193 /// All bit fields as a 64-bit value 6194 /// 6195 UINT64 Uint64; 6196} MSR_IA32_PM_CTL1_REGISTER; 6197 6198 6199/** 6200 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1. 6201 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical 6202 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1. 6203 6204 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2) 6205 @param EAX Lower 32-bits of MSR value. 6206 @param EDX Upper 32-bits of MSR value. 6207 6208 <b>Example usage</b> 6209 @code 6210 UINT64 Msr; 6211 6212 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL); 6213 @endcode 6214 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM. 6215**/ 6216#define MSR_IA32_THREAD_STALL 0x00000DB2 6217 6218 6219/** 6220 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0] 6221 CPUID.80000001H:EDX.[2 9]). 6222 6223 @param ECX MSR_IA32_EFER (0xC0000080) 6224 @param EAX Lower 32-bits of MSR value. 6225 Described by the type MSR_IA32_EFER_REGISTER. 6226 @param EDX Upper 32-bits of MSR value. 6227 Described by the type MSR_IA32_EFER_REGISTER. 6228 6229 <b>Example usage</b> 6230 @code 6231 MSR_IA32_EFER_REGISTER Msr; 6232 6233 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER); 6234 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64); 6235 @endcode 6236 @note MSR_IA32_EFER is defined as IA32_EFER in SDM. 6237**/ 6238#define MSR_IA32_EFER 0xC0000080 6239 6240/** 6241 MSR information returned for MSR index #MSR_IA32_EFER 6242**/ 6243typedef union { 6244 /// 6245 /// Individual bit fields 6246 /// 6247 struct { 6248 /// 6249 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET 6250 /// instructions in 64-bit mode. 6251 /// 6252 UINT32 SCE:1; 6253 UINT32 Reserved1:7; 6254 /// 6255 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode 6256 /// operation. 6257 /// 6258 UINT32 LME:1; 6259 UINT32 Reserved2:1; 6260 /// 6261 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode 6262 /// is active when set. 6263 /// 6264 UINT32 LMA:1; 6265 /// 6266 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W). 6267 /// 6268 UINT32 NXE:1; 6269 UINT32 Reserved3:20; 6270 UINT32 Reserved4:32; 6271 } Bits; 6272 /// 6273 /// All bit fields as a 32-bit value 6274 /// 6275 UINT32 Uint32; 6276 /// 6277 /// All bit fields as a 64-bit value 6278 /// 6279 UINT64 Uint64; 6280} MSR_IA32_EFER_REGISTER; 6281 6282 6283/** 6284 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1. 6285 6286 @param ECX MSR_IA32_STAR (0xC0000081) 6287 @param EAX Lower 32-bits of MSR value. 6288 @param EDX Upper 32-bits of MSR value. 6289 6290 <b>Example usage</b> 6291 @code 6292 UINT64 Msr; 6293 6294 Msr = AsmReadMsr64 (MSR_IA32_STAR); 6295 AsmWriteMsr64 (MSR_IA32_STAR, Msr); 6296 @endcode 6297 @note MSR_IA32_STAR is defined as IA32_STAR in SDM. 6298**/ 6299#define MSR_IA32_STAR 0xC0000081 6300 6301 6302/** 6303 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1. 6304 6305 @param ECX MSR_IA32_LSTAR (0xC0000082) 6306 @param EAX Lower 32-bits of MSR value. 6307 @param EDX Upper 32-bits of MSR value. 6308 6309 <b>Example usage</b> 6310 @code 6311 UINT64 Msr; 6312 6313 Msr = AsmReadMsr64 (MSR_IA32_LSTAR); 6314 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr); 6315 @endcode 6316 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM. 6317**/ 6318#define MSR_IA32_LSTAR 0xC0000082 6319 6320 6321/** 6322 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1. 6323 6324 @param ECX MSR_IA32_FMASK (0xC0000084) 6325 @param EAX Lower 32-bits of MSR value. 6326 @param EDX Upper 32-bits of MSR value. 6327 6328 <b>Example usage</b> 6329 @code 6330 UINT64 Msr; 6331 6332 Msr = AsmReadMsr64 (MSR_IA32_FMASK); 6333 AsmWriteMsr64 (MSR_IA32_FMASK, Msr); 6334 @endcode 6335 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM. 6336**/ 6337#define MSR_IA32_FMASK 0xC0000084 6338 6339 6340/** 6341 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1. 6342 6343 @param ECX MSR_IA32_FS_BASE (0xC0000100) 6344 @param EAX Lower 32-bits of MSR value. 6345 @param EDX Upper 32-bits of MSR value. 6346 6347 <b>Example usage</b> 6348 @code 6349 UINT64 Msr; 6350 6351 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE); 6352 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr); 6353 @endcode 6354 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM. 6355**/ 6356#define MSR_IA32_FS_BASE 0xC0000100 6357 6358 6359/** 6360 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1. 6361 6362 @param ECX MSR_IA32_GS_BASE (0xC0000101) 6363 @param EAX Lower 32-bits of MSR value. 6364 @param EDX Upper 32-bits of MSR value. 6365 6366 <b>Example usage</b> 6367 @code 6368 UINT64 Msr; 6369 6370 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE); 6371 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr); 6372 @endcode 6373 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM. 6374**/ 6375#define MSR_IA32_GS_BASE 0xC0000101 6376 6377 6378/** 6379 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1. 6380 6381 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102) 6382 @param EAX Lower 32-bits of MSR value. 6383 @param EDX Upper 32-bits of MSR value. 6384 6385 <b>Example usage</b> 6386 @code 6387 UINT64 Msr; 6388 6389 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE); 6390 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr); 6391 @endcode 6392 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM. 6393**/ 6394#define MSR_IA32_KERNEL_GS_BASE 0xC0000102 6395 6396 6397/** 6398 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1. 6399 6400 @param ECX MSR_IA32_TSC_AUX (0xC0000103) 6401 @param EAX Lower 32-bits of MSR value. 6402 Described by the type MSR_IA32_TSC_AUX_REGISTER. 6403 @param EDX Upper 32-bits of MSR value. 6404 Described by the type MSR_IA32_TSC_AUX_REGISTER. 6405 6406 <b>Example usage</b> 6407 @code 6408 MSR_IA32_TSC_AUX_REGISTER Msr; 6409 6410 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX); 6411 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64); 6412 @endcode 6413 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM. 6414**/ 6415#define MSR_IA32_TSC_AUX 0xC0000103 6416 6417/** 6418 MSR information returned for MSR index #MSR_IA32_TSC_AUX 6419**/ 6420typedef union { 6421 /// 6422 /// Individual bit fields 6423 /// 6424 struct { 6425 /// 6426 /// [Bits 31:0] AUX: Auxiliary signature of TSC. 6427 /// 6428 UINT32 AUX:32; 6429 UINT32 Reserved:32; 6430 } Bits; 6431 /// 6432 /// All bit fields as a 32-bit value 6433 /// 6434 UINT32 Uint32; 6435 /// 6436 /// All bit fields as a 64-bit value 6437 /// 6438 UINT64 Uint64; 6439} MSR_IA32_TSC_AUX_REGISTER; 6440 6441#endif 6442