| 3b4640ee56e06eea83db296d98210f99ff68310c |
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20-Dec-2016 |
Hao Wu <hao.a.wu@intel.com> |
UefiCpuPkg/ArchitecturalMsr.h: Remove non-Ascii characters
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
/device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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| a03bb3d2a9f7486f3bd9539cd35561661c5b38a2 |
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07-Dec-2016 |
Michael Kinney <michael.d.kinney@intel.com> |
UefiCpuPkg/Include: Update MSEG structure comments
Add comments to describe fields of MSEG_HEADER and
add define values for the MonitorFeatures field.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
/device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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| 0f16be6d9eef371d6ed1e45422748ae0fb49652f |
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25-Oct-2016 |
Hao Wu <hao.a.wu@intel.com> |
UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update MSR header files of processors (excluding Goldmont and Skylake
processors) according to Intel(R) 64 and IA-32 Architectures Software
Developer's Manual, Volume 3, September 2016, Chapter 35
Model-Specific-Registers (MSR).
Summary of incompatible changes:
General:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header
files has been removed or renamed to IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS)
in processor-specific header files have been removed or renamed to
IA32_MC{X}_{XXX} (like IA32_MC4_STATUS)
Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in
SDM are still kept in processor-specific header files.
HaswellMsr.h:
1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed
Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE'
in SDM.
Since the MSR definition is the same with architectural MSR, we remove it.
SandyBridgeMsr.h:
1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields
0:3
Bit description change from 'Core {X} select' to 'Slice {X} select' for
bit 0:3 in SDM.
SilvermontMsr.h:
1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed
Bit description for this MSR is totally changed in SDM, we modify the
structure definition to align with it.
XeonDMsr.h:
1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY
and MSR_PKG_C10_RESIDENCY have been removed
Those 3 MSRs are not defined for this processor in SDM, we remove them.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
/device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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| 831d287a99873643f94f3e06f5bb1b16a32d268b |
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10-Nov-2016 |
Michael Kinney <michael.d.kinney@intel.com> |
UefiCpuPkg/Include: Add VMX MSR register structures
https://bugzilla.tianocore.org/show_bug.cgi?id=279
Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER
structures with the bit fields for these two MSRs. Also
add MSEG_HEADER structure whose base address is in the
MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
/device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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| 7de98828b7d716bde9517a1e5262079442ffb257 |
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06-Sep-2016 |
Jeff Fan <jeff.fan@intel.com> |
UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
/device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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| 490b048b5afec06b1c78e6723530dcebd8b21612 |
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15-Aug-2016 |
Ruiyu Ni <ruiyu.ni@intel.com> |
UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
/device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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| 04c980a6305c7ae61fc4649ffbf8333e5cb7f188 |
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08-Mar-2016 |
Michael Kinney <michael.d.kinney@intel.com> |
UefiCpuPkg/Include: Add Architectural MSR include file
Add Architectural MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-1.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
/device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
|