1/** @file
2
3  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
4
5
6  This program and the accompanying materials are licensed and made available under
7
8  the terms and conditions of the BSD License that accompanies this distribution.
9
10  The full text of the license may be found at
11
12  http://opensource.org/licenses/bsd-license.php.
13
14
15
16  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17
18  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20
21
22
23Module Name:
24
25
26  IchRegTable.c
27
28Abstract:
29
30  Register initialization table for Ich.
31
32
33
34--*/
35
36#include <Library/EfiRegTableLib.h>
37#include "PlatformDxe.h"
38extern EFI_PLATFORM_INFO_HOB      mPlatformInfo;
39
40#define R_EFI_PCI_SVID 0x2C
41
42EFI_REG_TABLE mSubsystemIdRegs [] = {
43
44  //
45  // Program SVID and SID for PCI devices.
46  // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance
47  //
48  PCI_WRITE (
49      MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,
50      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
51    ),
52
53  PCI_WRITE (
54      IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,
55      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
56    ),
57
58  PCI_WRITE(
59      DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID, EfiPciWidthUint32,
60      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
61    ),
62  PCI_WRITE (
63      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,
64      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
65    ),
66  PCI_WRITE (
67      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,
68      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
69    ),
70  PCI_WRITE (
71      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID, EfiPciWidthUint32,
72      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
73    ),
74  PCI_WRITE (
75      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,
76      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
77    ),
78  PCI_WRITE (
79      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID, EfiPciWidthUint32,
80      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
81    ),
82  PCI_WRITE (
83      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID, EfiPciWidthUint32,
84      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
85    ),
86  PCI_WRITE (
87      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID, EfiPciWidthUint32,
88      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
89    ),
90  PCI_WRITE (
91      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID, EfiPciWidthUint32,
92      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
93    ),
94  TERMINATE_TABLE
95};
96
97/**
98  Updates the mSubsystemIdRegs table, and processes it.  This should program
99  the Subsystem Vendor and Device IDs.
100
101  @retval Returns  VOID
102
103**/
104VOID
105InitializeSubsystemIds (
106  )
107{
108
109  EFI_REG_TABLE *RegTablePtr;
110  UINT32 SubsystemVidDid;
111
112  SubsystemVidDid = mPlatformInfo.SsidSvid;
113
114  RegTablePtr = mSubsystemIdRegs;
115
116  //
117  // While we are not at the end of the table
118  //
119  while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {
120  	//
121    // If the data to write is the original SSID
122    //
123    if (RegTablePtr->PciWrite.Data ==
124          ((V_PCH_DEFAULT_SID << 16) |
125           V_PCH_INTEL_VENDOR_ID)
126       ) {
127
128    	//
129      // Then overwrite it to use the alternate SSID
130      //
131      RegTablePtr->PciWrite.Data = SubsystemVidDid;
132    }
133
134    //
135    // Go to next table entry
136    //
137    RegTablePtr++;
138    }
139
140  RegTablePtr = mSubsystemIdRegs;
141
142
143  //
144  // Program the SSVID/SSDID
145  //
146  ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo, NULL);
147
148}
149