1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/uapi/asm/kvm.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#ifndef __ARM_KVM_H__ 24#define __ARM_KVM_H__ 25 26#define KVM_SPSR_EL1 0 27#define KVM_SPSR_SVC KVM_SPSR_EL1 28#define KVM_SPSR_ABT 1 29#define KVM_SPSR_UND 2 30#define KVM_SPSR_IRQ 3 31#define KVM_SPSR_FIQ 4 32#define KVM_NR_SPSR 5 33 34#ifndef __ASSEMBLY__ 35#include <linux/psci.h> 36#include <linux/types.h> 37#include <asm/ptrace.h> 38 39#define __KVM_HAVE_GUEST_DEBUG 40#define __KVM_HAVE_IRQ_LINE 41#define __KVM_HAVE_READONLY_MEM 42 43#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 44 45#define KVM_REG_SIZE(id) \ 46 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 47 48struct kvm_regs { 49 struct user_pt_regs regs; /* sp = sp_el0 */ 50 51 __u64 sp_el1; 52 __u64 elr_el1; 53 54 __u64 spsr[KVM_NR_SPSR]; 55 56 struct user_fpsimd_state fp_regs; 57}; 58 59/* 60 * Supported CPU Targets - Adding a new target type is not recommended, 61 * unless there are some special registers not supported by the 62 * genericv8 syreg table. 63 */ 64#define KVM_ARM_TARGET_AEM_V8 0 65#define KVM_ARM_TARGET_FOUNDATION_V8 1 66#define KVM_ARM_TARGET_CORTEX_A57 2 67#define KVM_ARM_TARGET_XGENE_POTENZA 3 68#define KVM_ARM_TARGET_CORTEX_A53 4 69/* Generic ARM v8 target */ 70#define KVM_ARM_TARGET_GENERIC_V8 5 71 72#define KVM_ARM_NUM_TARGETS 6 73 74/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 75#define KVM_ARM_DEVICE_TYPE_SHIFT 0 76#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 77#define KVM_ARM_DEVICE_ID_SHIFT 16 78#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 79 80/* Supported device IDs */ 81#define KVM_ARM_DEVICE_VGIC_V2 0 82 83/* Supported VGIC address types */ 84#define KVM_VGIC_V2_ADDR_TYPE_DIST 0 85#define KVM_VGIC_V2_ADDR_TYPE_CPU 1 86 87#define KVM_VGIC_V2_DIST_SIZE 0x1000 88#define KVM_VGIC_V2_CPU_SIZE 0x2000 89 90/* Supported VGICv3 address types */ 91#define KVM_VGIC_V3_ADDR_TYPE_DIST 2 92#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 93#define KVM_VGIC_ITS_ADDR_TYPE 4 94 95#define KVM_VGIC_V3_DIST_SIZE SZ_64K 96#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 97#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 98 99#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 100#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 101#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 102#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 103 104struct kvm_vcpu_init { 105 __u32 target; 106 __u32 features[7]; 107}; 108 109struct kvm_sregs { 110}; 111 112struct kvm_fpu { 113}; 114 115/* 116 * See v8 ARM ARM D7.3: Debug Registers 117 * 118 * The architectural limit is 16 debug registers of each type although 119 * in practice there are usually less (see ID_AA64DFR0_EL1). 120 * 121 * Although the control registers are architecturally defined as 32 122 * bits wide we use a 64 bit structure here to keep parity with 123 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 124 * 64 bit values. It also allows for the possibility of the 125 * architecture expanding the control registers without having to 126 * change the userspace ABI. 127 */ 128#define KVM_ARM_MAX_DBG_REGS 16 129struct kvm_guest_debug_arch { 130 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 131 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 132 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 133 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 134}; 135 136struct kvm_debug_exit_arch { 137 __u32 hsr; 138 __u64 far; /* used for watchpoints */ 139}; 140 141/* 142 * Architecture specific defines for kvm_guest_debug->control 143 */ 144 145#define KVM_GUESTDBG_USE_SW_BP (1 << 16) 146#define KVM_GUESTDBG_USE_HW (1 << 17) 147 148struct kvm_sync_regs { 149 /* Used with KVM_CAP_ARM_USER_IRQ */ 150 __u64 device_irq_level; 151}; 152 153struct kvm_arch_memory_slot { 154}; 155 156/* If you need to interpret the index values, here is the key: */ 157#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 158#define KVM_REG_ARM_COPROC_SHIFT 16 159 160/* Normal registers are mapped as coprocessor 16. */ 161#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 162#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 163 164/* Some registers need more space to represent values. */ 165#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 166#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 167#define KVM_REG_ARM_DEMUX_ID_SHIFT 8 168#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 169#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 170#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 171 172/* AArch64 system registers */ 173#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 174#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 175#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 176#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 177#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 178#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 179#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 180#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 181#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 182#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 183#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 184 185#define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 186 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 187 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 188 189#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 190 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 191 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 192 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 193 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 194 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 195 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 196 197#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 198 199/* Physical Timer EL0 Registers */ 200#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 201#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 202#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 203 204/* EL0 Virtual Timer Registers */ 205#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 206#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 207#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 208 209/* Device Control API: ARM VGIC */ 210#define KVM_DEV_ARM_VGIC_GRP_ADDR 0 211#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 212#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 213#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 214#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 215#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 216#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 217 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 218#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 219#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 220#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 221#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 222#define KVM_DEV_ARM_VGIC_GRP_CTRL 4 223#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 224#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 225#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 226#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 227#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 228#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 229 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 230#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 231#define VGIC_LEVEL_INFO_LINE_LEVEL 0 232 233#define KVM_DEV_ARM_VGIC_CTRL_INIT 0 234#define KVM_DEV_ARM_ITS_SAVE_TABLES 1 235#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 236#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 237#define KVM_DEV_ARM_ITS_CTRL_RESET 4 238 239/* Device Control API on vcpu fd */ 240#define KVM_ARM_VCPU_PMU_V3_CTRL 0 241#define KVM_ARM_VCPU_PMU_V3_IRQ 0 242#define KVM_ARM_VCPU_PMU_V3_INIT 1 243#define KVM_ARM_VCPU_TIMER_CTRL 1 244#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 245#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 246 247/* KVM_IRQ_LINE irq field index values */ 248#define KVM_ARM_IRQ_TYPE_SHIFT 24 249#define KVM_ARM_IRQ_TYPE_MASK 0xff 250#define KVM_ARM_IRQ_VCPU_SHIFT 16 251#define KVM_ARM_IRQ_VCPU_MASK 0xff 252#define KVM_ARM_IRQ_NUM_SHIFT 0 253#define KVM_ARM_IRQ_NUM_MASK 0xffff 254 255/* irq_type field */ 256#define KVM_ARM_IRQ_TYPE_CPU 0 257#define KVM_ARM_IRQ_TYPE_SPI 1 258#define KVM_ARM_IRQ_TYPE_PPI 2 259 260/* out-of-kernel GIC cpu interrupt injection irq_number field */ 261#define KVM_ARM_IRQ_CPU_IRQ 0 262#define KVM_ARM_IRQ_CPU_FIQ 1 263 264/* 265 * This used to hold the highest supported SPI, but it is now obsolete 266 * and only here to provide source code level compatibility with older 267 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 268 */ 269#ifndef __KERNEL__ 270#define KVM_ARM_IRQ_GIC_MAX 127 271#endif 272 273/* One single KVM irqchip, ie. the VGIC */ 274#define KVM_NR_IRQCHIPS 1 275 276/* PSCI interface */ 277#define KVM_PSCI_FN_BASE 0x95c1ba5e 278#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 279 280#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 281#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 282#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 283#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 284 285#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 286#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 287#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 288#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 289 290#endif 291 292#endif /* __ARM_KVM_H__ */ 293