TargetInstrInfo.h revision 096f58b09adb03b5b060e12b327cff57329909f7
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32 33//--------------------------------------------------------------------------- 34// Data types used to define information about a single machine instruction 35//--------------------------------------------------------------------------- 36 37typedef short MachineOpCode; 38typedef unsigned InstrSchedClass; 39 40//--------------------------------------------------------------------------- 41// struct TargetInstrDescriptor: 42// Predefined information about each machine instruction. 43// Designed to initialized statically. 44// 45 46const unsigned M_NOP_FLAG = 1 << 0; 47const unsigned M_BRANCH_FLAG = 1 << 1; 48const unsigned M_CALL_FLAG = 1 << 2; 49const unsigned M_RET_FLAG = 1 << 3; 50const unsigned M_BARRIER_FLAG = 1 << 4; 51const unsigned M_CC_FLAG = 1 << 6; 52const unsigned M_LOAD_FLAG = 1 << 10; 53const unsigned M_STORE_FLAG = 1 << 12; 54const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 55const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction 56// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub 57const unsigned M_2_ADDR_FLAG = 1 << 15; 58 59// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 60// block? Typically this is things like return and branch instructions. 61// Various passes use this to insert code into the bottom of a basic block, but 62// before control flow occurs. 63const unsigned M_TERMINATOR_FLAG = 1 << 16; 64 65struct TargetInstrDescriptor { 66 const char * Name; // Assembly language mnemonic for the opcode. 67 int numOperands; // Number of args; -1 if variable #args 68 int resultPos; // Position of the result; -1 if no result 69 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 70 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 71 // smallest -ve value is -(maxImmedConst+1). 72 unsigned numDelaySlots; // Number of delay slots after instruction 73 unsigned latency; // Latency in machine cycles 74 InstrSchedClass schedClass; // enum identifying instr sched class 75 unsigned Flags; // flags identifying machine instr class 76 unsigned TSFlags; // Target Specific Flag values 77 const unsigned *ImplicitUses; // Registers implicitly read by this instr 78 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 79}; 80 81 82//--------------------------------------------------------------------------- 83/// 84/// TargetInstrInfo - Interface to description of machine instructions 85/// 86class TargetInstrInfo { 87 const TargetInstrDescriptor* desc; // raw array to allow static init'n 88 unsigned NumOpcodes; // number of entries in the desc array 89 unsigned numRealOpCodes; // number of non-dummy op codes 90 91 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 92 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 93public: 94 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 95 virtual ~TargetInstrInfo(); 96 97 // Invariant: All instruction sets use opcode #0 as the PHI instruction 98 enum { PHI = 0 }; 99 100 unsigned getNumOpcodes() const { return NumOpcodes; } 101 102 /// get - Return the machine instruction descriptor that corresponds to the 103 /// specified instruction opcode. 104 /// 105 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 106 assert((unsigned)Opcode < NumOpcodes); 107 return desc[Opcode]; 108 } 109 110 const char *getName(MachineOpCode Opcode) const { 111 return get(Opcode).Name; 112 } 113 114 int getNumOperands(MachineOpCode Opcode) const { 115 return get(Opcode).numOperands; 116 } 117 118 119 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 120 return get(Opcode).schedClass; 121 } 122 123 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 124 return get(Opcode).ImplicitUses; 125 } 126 127 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 128 return get(Opcode).ImplicitDefs; 129 } 130 131 132 // 133 // Query instruction class flags according to the machine-independent 134 // flags listed above. 135 // 136 bool isReturn(MachineOpCode Opcode) const { 137 return get(Opcode).Flags & M_RET_FLAG; 138 } 139 140 bool isPseudoInstr(MachineOpCode Opcode) const { 141 return get(Opcode).Flags & M_PSEUDO_FLAG; 142 } 143 bool isTwoAddrInstr(MachineOpCode Opcode) const { 144 return get(Opcode).Flags & M_2_ADDR_FLAG; 145 } 146 bool isTerminatorInstr(unsigned Opcode) const { 147 return get(Opcode).Flags & M_TERMINATOR_FLAG; 148 } 149 150 // 151 // Return true if the instruction is a register to register move and 152 // leave the source and dest operands in the passed parameters. 153 // 154 virtual bool isMoveInstr(const MachineInstr& MI, 155 unsigned& sourceReg, 156 unsigned& destReg) const { 157 return false; 158 } 159 160 // 161 // Insert a goto (unconditional branch) sequence to MBB, right 162 // before MBBI 163 virtual void insertGoto(const MachineBasicBlock& MBB, 164 MachineBasicBlock::iterator MBBI) const { 165 assert(0 && "Target didn't implement insertGoto!"); 166 } 167 168 // 169 // Reverses the branch condition of the MachineInstr pointed by 170 // MI. The instruction is replaced and the new MI is returned. 171 virtual MachineBasicBlock::iterator 172 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 173 assert(0 && "Target didn't implement reverseBranchCondition!"); 174 } 175 176 //------------------------------------------------------------------------- 177 // Code generation support for creating individual machine instructions 178 // 179 // WARNING: These methods are Sparc specific 180 // 181 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 182 // 183 //------------------------------------------------------------------------- 184 185 int getResultPos(MachineOpCode Opcode) const { 186 return get(Opcode).resultPos; 187 } 188 unsigned getNumDelaySlots(MachineOpCode Opcode) const { 189 return get(Opcode).numDelaySlots; 190 } 191 bool isCCInstr(MachineOpCode Opcode) const { 192 return get(Opcode).Flags & M_CC_FLAG; 193 } 194 bool isNop(MachineOpCode Opcode) const { 195 return get(Opcode).Flags & M_NOP_FLAG; 196 } 197 bool isBranch(MachineOpCode Opcode) const { 198 return get(Opcode).Flags & M_BRANCH_FLAG; 199 } 200 /// isBarrier - Returns true if the specified instruction stops control flow 201 /// from executing the instruction immediately following it. Examples include 202 /// unconditional branches and return instructions. 203 bool isBarrier(MachineOpCode Opcode) const { 204 return get(Opcode).Flags & M_BARRIER_FLAG; 205 } 206 bool isCall(MachineOpCode Opcode) const { 207 return get(Opcode).Flags & M_CALL_FLAG; 208 } 209 bool isLoad(MachineOpCode Opcode) const { 210 return get(Opcode).Flags & M_LOAD_FLAG; 211 } 212 bool isStore(MachineOpCode Opcode) const { 213 return get(Opcode).Flags & M_STORE_FLAG; 214 } 215 bool isDummyPhiInstr(MachineOpCode Opcode) const { 216 return get(Opcode).Flags & M_DUMMY_PHI_FLAG; 217 } 218 219 virtual bool hasResultInterlock(MachineOpCode Opcode) const { 220 return true; 221 } 222 223 // 224 // Latencies for individual instructions and instruction pairs 225 // 226 virtual int minLatency(MachineOpCode Opcode) const { 227 return get(Opcode).latency; 228 } 229 230 virtual int maxLatency(MachineOpCode Opcode) const { 231 return get(Opcode).latency; 232 } 233 234 // 235 // Which operand holds an immediate constant? Returns -1 if none 236 // 237 virtual int getImmedConstantPos(MachineOpCode Opcode) const { 238 return -1; // immediate position is machine specific, so say -1 == "none" 239 } 240 241 // Check if the specified constant fits in the immediate field 242 // of this machine instruction 243 // 244 virtual bool constantFitsInImmedField(MachineOpCode Opcode, 245 int64_t intValue) const; 246 247 // Return the largest positive constant that can be held in the IMMED field 248 // of this machine instruction. 249 // isSignExtended is set to true if the value is sign-extended before use 250 // (this is true for all immediate fields in SPARC instructions). 251 // Return 0 if the instruction has no IMMED field. 252 // 253 virtual uint64_t maxImmedConstant(MachineOpCode Opcode, 254 bool &isSignExtended) const { 255 isSignExtended = get(Opcode).immedIsSignExtended; 256 return get(Opcode).maxImmedConst; 257 } 258}; 259 260} // End llvm namespace 261 262#endif 263