TargetInstrInfo.h revision 0d3ea0268f44f8fd4ddf7a15f3624b384b0691db
1//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===---------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "llvm/Target/TargetMachine.h" 11#include "llvm/Support/DataTypes.h" 12#include <vector> 13 14class MachineInstrDescriptor; 15class TmpInstruction; 16class MachineInstr; 17class Value; 18class Instruction; 19 20 21typedef int InstrSchedClass; 22 23// Global variable holding an array of descriptors for machine instructions. 24// The actual object needs to be created separately for each target machine. 25// This variable is initialized and reset by class MachineInstrInfo. 26// 27// FIXME: This should be a property of the target so that more than one target 28// at a time can be active... 29// 30extern const MachineInstrDescriptor *TargetInstrDescriptors; 31 32 33//--------------------------------------------------------------------------- 34// struct MachineInstrDescriptor: 35// Predefined information about each machine instruction. 36// Designed to initialized statically. 37// 38// class MachineInstructionInfo 39// Interface to description of machine instructions 40// 41//--------------------------------------------------------------------------- 42 43 44const unsigned int M_NOP_FLAG = 1; 45const unsigned int M_BRANCH_FLAG = 1 << 1; 46const unsigned int M_CALL_FLAG = 1 << 2; 47const unsigned int M_RET_FLAG = 1 << 3; 48const unsigned int M_ARITH_FLAG = 1 << 4; 49const unsigned int M_CC_FLAG = 1 << 6; 50const unsigned int M_LOGICAL_FLAG = 1 << 6; 51const unsigned int M_INT_FLAG = 1 << 7; 52const unsigned int M_FLOAT_FLAG = 1 << 8; 53const unsigned int M_CONDL_FLAG = 1 << 9; 54const unsigned int M_LOAD_FLAG = 1 << 10; 55const unsigned int M_PREFETCH_FLAG = 1 << 11; 56const unsigned int M_STORE_FLAG = 1 << 12; 57const unsigned int M_DUMMY_PHI_FLAG = 1 << 13; 58 59 60struct MachineInstrDescriptor { 61 string opCodeString; // Assembly language mnemonic for the opcode. 62 int numOperands; // Number of args; -1 if variable #args 63 int resultPos; // Position of the result; -1 if no result 64 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0. 65 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 66 // smallest -ve value is -(maxImmedConst+1). 67 unsigned int numDelaySlots; // Number of delay slots after instruction 68 unsigned int latency; // Latency in machine cycles 69 InstrSchedClass schedClass; // enum identifying instr sched class 70 unsigned int iclass; // flags identifying machine instr class 71}; 72 73 74class MachineInstrInfo : public NonCopyableV { 75protected: 76 const MachineInstrDescriptor* desc; // raw array to allow static init'n 77 unsigned int descSize; // number of entries in the desc array 78 unsigned int numRealOpCodes; // number of non-dummy op codes 79 80public: 81 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize, 82 unsigned numRealOpCodes); 83 virtual ~MachineInstrInfo(); 84 85 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 86 unsigned getNumTotalOpCodes() const { return descSize; } 87 88 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { 89 assert(opCode >= 0 && opCode < (int)descSize); 90 return desc[opCode]; 91 } 92 93 int getNumOperands(MachineOpCode opCode) const { 94 return getDescriptor(opCode).numOperands; 95 } 96 97 int getResultPos(MachineOpCode opCode) const { 98 return getDescriptor(opCode).resultPos; 99 } 100 101 unsigned getNumDelaySlots(MachineOpCode opCode) const { 102 return getDescriptor(opCode).numDelaySlots; 103 } 104 105 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 106 return getDescriptor(opCode).schedClass; 107 } 108 109 // 110 // Query instruction class flags according to the machine-independent 111 // flags listed above. 112 // 113 unsigned int getIClass(MachineOpCode opCode) const { 114 return getDescriptor(opCode).iclass; 115 } 116 bool isNop(MachineOpCode opCode) const { 117 return getDescriptor(opCode).iclass & M_NOP_FLAG; 118 } 119 bool isBranch(MachineOpCode opCode) const { 120 return getDescriptor(opCode).iclass & M_BRANCH_FLAG; 121 } 122 bool isCall(MachineOpCode opCode) const { 123 return getDescriptor(opCode).iclass & M_CALL_FLAG; 124 } 125 bool isReturn(MachineOpCode opCode) const { 126 return getDescriptor(opCode).iclass & M_RET_FLAG; 127 } 128 bool isControlFlow(MachineOpCode opCode) const { 129 return getDescriptor(opCode).iclass & M_BRANCH_FLAG 130 || getDescriptor(opCode).iclass & M_CALL_FLAG 131 || getDescriptor(opCode).iclass & M_RET_FLAG; 132 } 133 bool isArith(MachineOpCode opCode) const { 134 return getDescriptor(opCode).iclass & M_RET_FLAG; 135 } 136 bool isCCInstr(MachineOpCode opCode) const { 137 return getDescriptor(opCode).iclass & M_CC_FLAG; 138 } 139 bool isLogical(MachineOpCode opCode) const { 140 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; 141 } 142 bool isIntInstr(MachineOpCode opCode) const { 143 return getDescriptor(opCode).iclass & M_INT_FLAG; 144 } 145 bool isFloatInstr(MachineOpCode opCode) const { 146 return getDescriptor(opCode).iclass & M_FLOAT_FLAG; 147 } 148 bool isConditional(MachineOpCode opCode) const { 149 return getDescriptor(opCode).iclass & M_CONDL_FLAG; 150 } 151 bool isLoad(MachineOpCode opCode) const { 152 return getDescriptor(opCode).iclass & M_LOAD_FLAG; 153 } 154 bool isPrefetch(MachineOpCode opCode) const { 155 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 156 } 157 bool isLoadOrPrefetch(MachineOpCode opCode) const { 158 return getDescriptor(opCode).iclass & M_LOAD_FLAG 159 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 160 } 161 bool isStore(MachineOpCode opCode) const { 162 return getDescriptor(opCode).iclass & M_STORE_FLAG; 163 } 164 bool isMemoryAccess(MachineOpCode opCode) const { 165 return getDescriptor(opCode).iclass & M_LOAD_FLAG 166 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG 167 || getDescriptor(opCode).iclass & M_STORE_FLAG; 168 } 169 bool isDummyPhiInstr(const MachineOpCode opCode) const { 170 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; 171 } 172 173 174 // delete this later ******* 175 bool isPhi(const MachineOpCode opCode) { return isDummyPhiInstr(opCode); } 176 177 178 // Check if an instruction can be issued before its operands are ready, 179 // or if a subsequent instruction that uses its result can be issued 180 // before the results are ready. 181 // Default to true since most instructions on many architectures allow this. 182 // 183 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 184 return true; 185 } 186 187 virtual bool hasResultInterlock(MachineOpCode opCode) const { 188 return true; 189 } 190 191 // 192 // Latencies for individual instructions and instruction pairs 193 // 194 virtual int minLatency(MachineOpCode opCode) const { 195 return getDescriptor(opCode).latency; 196 } 197 198 virtual int maxLatency(MachineOpCode opCode) const { 199 return getDescriptor(opCode).latency; 200 } 201 202 // Check if the specified constant fits in the immediate field 203 // of this machine instruction 204 // 205 virtual bool constantFitsInImmedField(MachineOpCode opCode, 206 int64_t intValue) const; 207 208 // Return the largest +ve constant that can be held in the IMMMED field 209 // of this machine instruction. 210 // isSignExtended is set to true if the value is sign-extended before use 211 // (this is true for all immediate fields in SPARC instructions). 212 // Return 0 if the instruction has no IMMED field. 213 // 214 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 215 bool &isSignExtended) const { 216 isSignExtended = getDescriptor(opCode).immedIsSignExtended; 217 return getDescriptor(opCode).maxImmedConst; 218 } 219 220 //------------------------------------------------------------------------- 221 // Code generation support for creating individual machine instructions 222 //------------------------------------------------------------------------- 223 224 // Create an instruction sequence to put the constant `val' into 225 // the virtual register `dest'. `val' may be a ConstPoolVal or a 226 // GlobalValue, viz., the constant address of a global variable or function. 227 // The generated instructions are returned in `minstrVec'. 228 // Any temp. registers (TmpInstruction) created are returned in `tempVec'. 229 // 230 virtual void CreateCodeToLoadConst(Value* val, 231 Instruction* dest, 232 vector<MachineInstr*>& minstrVec, 233 vector<TmpInstruction*>& temps) const =0; 234}; 235 236#endif 237