TargetInstrInfo.h revision 0d9513c74f3e4c019406273cce49e43508dc4dcf
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/MC/MCInstrInfo.h" 18#include "llvm/CodeGen/DFAPacketizer.h" 19#include "llvm/CodeGen/MachineFunction.h" 20 21namespace llvm { 22 23class InstrItineraryData; 24class LiveVariables; 25class MCAsmInfo; 26class MachineMemOperand; 27class MachineRegisterInfo; 28class MDNode; 29class MCInst; 30class SDNode; 31class ScheduleHazardRecognizer; 32class SelectionDAG; 33class ScheduleDAG; 34class TargetRegisterClass; 35class TargetRegisterInfo; 36class BranchProbability; 37 38template<class T> class SmallVectorImpl; 39 40 41//--------------------------------------------------------------------------- 42/// 43/// TargetInstrInfo - Interface to description of machine instruction set 44/// 45class TargetInstrInfo : public MCInstrInfo { 46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 48public: 49 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) 50 : CallFrameSetupOpcode(CFSetupOpcode), 51 CallFrameDestroyOpcode(CFDestroyOpcode) { 52 } 53 54 virtual ~TargetInstrInfo(); 55 56 /// getRegClass - Givem a machine instruction descriptor, returns the register 57 /// class constraint for OpNum, or NULL. 58 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 59 unsigned OpNum, 60 const TargetRegisterInfo *TRI, 61 const MachineFunction &MF) const; 62 63 /// isTriviallyReMaterializable - Return true if the instruction is trivially 64 /// rematerializable, meaning it has no side effects and requires no operands 65 /// that aren't always available. 66 bool isTriviallyReMaterializable(const MachineInstr *MI, 67 AliasAnalysis *AA = 0) const { 68 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 69 (MI->getDesc().isRematerializable() && 70 (isReallyTriviallyReMaterializable(MI, AA) || 71 isReallyTriviallyReMaterializableGeneric(MI, AA))); 72 } 73 74protected: 75 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 76 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 77 /// specify whether the instruction is actually trivially rematerializable, 78 /// taking into consideration its operands. This predicate must return false 79 /// if the instruction has any side effects other than producing a value, or 80 /// if it requres any address registers that are not always available. 81 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 82 AliasAnalysis *AA) const { 83 return false; 84 } 85 86private: 87 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 88 /// for which the M_REMATERIALIZABLE flag is set and the target hook 89 /// isReallyTriviallyReMaterializable returns false, this function does 90 /// target-independent tests to determine if the instruction is really 91 /// trivially rematerializable. 92 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 93 AliasAnalysis *AA) const; 94 95public: 96 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 97 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 98 /// targets use pseudo instructions in order to abstract away the difference 99 /// between operating with a frame pointer and operating without, through the 100 /// use of these two instructions. 101 /// 102 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 103 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 104 105 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 106 /// extension instruction. That is, it's like a copy where it's legal for the 107 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 108 /// true, then it's expected the pre-extension value is available as a subreg 109 /// of the result register. This also returns the sub-register index in 110 /// SubIdx. 111 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 112 unsigned &SrcReg, unsigned &DstReg, 113 unsigned &SubIdx) const { 114 return false; 115 } 116 117 /// isLoadFromStackSlot - If the specified machine instruction is a direct 118 /// load from a stack slot, return the virtual or physical register number of 119 /// the destination along with the FrameIndex of the loaded stack slot. If 120 /// not, return 0. This predicate must return 0 if the instruction has 121 /// any side effects other than loading from the stack slot. 122 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 123 int &FrameIndex) const { 124 return 0; 125 } 126 127 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 128 /// stack locations as well. This uses a heuristic so it isn't 129 /// reliable for correctness. 130 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 131 int &FrameIndex) const { 132 return 0; 133 } 134 135 /// hasLoadFromStackSlot - If the specified machine instruction has 136 /// a load from a stack slot, return true along with the FrameIndex 137 /// of the loaded stack slot and the machine mem operand containing 138 /// the reference. If not, return false. Unlike 139 /// isLoadFromStackSlot, this returns true for any instructions that 140 /// loads from the stack. This is just a hint, as some cases may be 141 /// missed. 142 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 143 const MachineMemOperand *&MMO, 144 int &FrameIndex) const { 145 return 0; 146 } 147 148 /// isStoreToStackSlot - If the specified machine instruction is a direct 149 /// store to a stack slot, return the virtual or physical register number of 150 /// the source reg along with the FrameIndex of the loaded stack slot. If 151 /// not, return 0. This predicate must return 0 if the instruction has 152 /// any side effects other than storing to the stack slot. 153 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 154 int &FrameIndex) const { 155 return 0; 156 } 157 158 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 159 /// stack locations as well. This uses a heuristic so it isn't 160 /// reliable for correctness. 161 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 162 int &FrameIndex) const { 163 return 0; 164 } 165 166 /// hasStoreToStackSlot - If the specified machine instruction has a 167 /// store to a stack slot, return true along with the FrameIndex of 168 /// the loaded stack slot and the machine mem operand containing the 169 /// reference. If not, return false. Unlike isStoreToStackSlot, 170 /// this returns true for any instructions that stores to the 171 /// stack. This is just a hint, as some cases may be missed. 172 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 173 const MachineMemOperand *&MMO, 174 int &FrameIndex) const { 175 return 0; 176 } 177 178 /// reMaterialize - Re-issue the specified 'original' instruction at the 179 /// specific location targeting a new destination register. 180 /// The register in Orig->getOperand(0).getReg() will be substituted by 181 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 182 /// SubIdx. 183 virtual void reMaterialize(MachineBasicBlock &MBB, 184 MachineBasicBlock::iterator MI, 185 unsigned DestReg, unsigned SubIdx, 186 const MachineInstr *Orig, 187 const TargetRegisterInfo &TRI) const = 0; 188 189 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 190 /// two-addrss instruction inserted by two-address pass. 191 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 192 MachineInstr *UseMI, 193 const TargetRegisterInfo &TRI) const { 194 // Do nothing. 195 } 196 197 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 198 /// MachineFunction::CloneMachineInstr(), but the target may update operands 199 /// that are required to be unique. 200 /// 201 /// The instruction must be duplicable as indicated by isNotDuplicable(). 202 virtual MachineInstr *duplicate(MachineInstr *Orig, 203 MachineFunction &MF) const = 0; 204 205 /// convertToThreeAddress - This method must be implemented by targets that 206 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 207 /// may be able to convert a two-address instruction into one or more true 208 /// three-address instructions on demand. This allows the X86 target (for 209 /// example) to convert ADD and SHL instructions into LEA instructions if they 210 /// would require register copies due to two-addressness. 211 /// 212 /// This method returns a null pointer if the transformation cannot be 213 /// performed, otherwise it returns the last new instruction. 214 /// 215 virtual MachineInstr * 216 convertToThreeAddress(MachineFunction::iterator &MFI, 217 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 218 return 0; 219 } 220 221 /// commuteInstruction - If a target has any instructions that are 222 /// commutable but require converting to different instructions or making 223 /// non-trivial changes to commute them, this method can overloaded to do 224 /// that. The default implementation simply swaps the commutable operands. 225 /// If NewMI is false, MI is modified in place and returned; otherwise, a 226 /// new machine instruction is created and returned. Do not call this 227 /// method for a non-commutable instruction, but there may be some cases 228 /// where this method fails and returns null. 229 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 230 bool NewMI = false) const = 0; 231 232 /// findCommutedOpIndices - If specified MI is commutable, return the two 233 /// operand indices that would swap value. Return false if the instruction 234 /// is not in a form which this routine understands. 235 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 236 unsigned &SrcOpIdx2) const = 0; 237 238 /// produceSameValue - Return true if two machine instructions would produce 239 /// identical values. By default, this is only true when the two instructions 240 /// are deemed identical except for defs. If this function is called when the 241 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 242 /// aggressive checks. 243 virtual bool produceSameValue(const MachineInstr *MI0, 244 const MachineInstr *MI1, 245 const MachineRegisterInfo *MRI = 0) const = 0; 246 247 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 248 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 249 /// implemented for a target). Upon success, this returns false and returns 250 /// with the following information in various cases: 251 /// 252 /// 1. If this block ends with no branches (it just falls through to its succ) 253 /// just return false, leaving TBB/FBB null. 254 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 255 /// the destination block. 256 /// 3. If this block ends with a conditional branch and it falls through to a 257 /// successor block, it sets TBB to be the branch destination block and a 258 /// list of operands that evaluate the condition. These operands can be 259 /// passed to other TargetInstrInfo methods to create new branches. 260 /// 4. If this block ends with a conditional branch followed by an 261 /// unconditional branch, it returns the 'true' destination in TBB, the 262 /// 'false' destination in FBB, and a list of operands that evaluate the 263 /// condition. These operands can be passed to other TargetInstrInfo 264 /// methods to create new branches. 265 /// 266 /// Note that RemoveBranch and InsertBranch must be implemented to support 267 /// cases where this method returns success. 268 /// 269 /// If AllowModify is true, then this routine is allowed to modify the basic 270 /// block (e.g. delete instructions after the unconditional branch). 271 /// 272 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 273 MachineBasicBlock *&FBB, 274 SmallVectorImpl<MachineOperand> &Cond, 275 bool AllowModify = false) const { 276 return true; 277 } 278 279 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 280 /// This is only invoked in cases where AnalyzeBranch returns success. It 281 /// returns the number of instructions that were removed. 282 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 283 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); 284 } 285 286 /// InsertBranch - Insert branch code into the end of the specified 287 /// MachineBasicBlock. The operands to this method are the same as those 288 /// returned by AnalyzeBranch. This is only invoked in cases where 289 /// AnalyzeBranch returns success. It returns the number of instructions 290 /// inserted. 291 /// 292 /// It is also invoked by tail merging to add unconditional branches in 293 /// cases where AnalyzeBranch doesn't apply because there was no original 294 /// branch to analyze. At least this much must be implemented, else tail 295 /// merging needs to be disabled. 296 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 297 MachineBasicBlock *FBB, 298 const SmallVectorImpl<MachineOperand> &Cond, 299 DebugLoc DL) const { 300 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); 301 } 302 303 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 304 /// after it, replacing it with an unconditional branch to NewDest. This is 305 /// used by the tail merging pass. 306 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 307 MachineBasicBlock *NewDest) const = 0; 308 309 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 310 /// block at the specified instruction (i.e. instruction would be the start 311 /// of a new basic block). 312 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 313 MachineBasicBlock::iterator MBBI) const { 314 return true; 315 } 316 317 /// isProfitableToIfCvt - Return true if it's profitable to predicate 318 /// instructions with accumulated instruction latency of "NumCycles" 319 /// of the specified basic block, where the probability of the instructions 320 /// being executed is given by Probability, and Confidence is a measure 321 /// of our confidence that it will be properly predicted. 322 virtual 323 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 324 unsigned ExtraPredCycles, 325 const BranchProbability &Probability) const { 326 return false; 327 } 328 329 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 330 /// checks for the case where two basic blocks from true and false path 331 /// of a if-then-else (diamond) are predicated on mutally exclusive 332 /// predicates, where the probability of the true path being taken is given 333 /// by Probability, and Confidence is a measure of our confidence that it 334 /// will be properly predicted. 335 virtual bool 336 isProfitableToIfCvt(MachineBasicBlock &TMBB, 337 unsigned NumTCycles, unsigned ExtraTCycles, 338 MachineBasicBlock &FMBB, 339 unsigned NumFCycles, unsigned ExtraFCycles, 340 const BranchProbability &Probability) const { 341 return false; 342 } 343 344 /// isProfitableToDupForIfCvt - Return true if it's profitable for 345 /// if-converter to duplicate instructions of specified accumulated 346 /// instruction latencies in the specified MBB to enable if-conversion. 347 /// The probability of the instructions being executed is given by 348 /// Probability, and Confidence is a measure of our confidence that it 349 /// will be properly predicted. 350 virtual bool 351 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 352 const BranchProbability &Probability) const { 353 return false; 354 } 355 356 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate 357 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 358 /// exclusive predicates. 359 /// e.g. 360 /// subeq r0, r1, #1 361 /// addne r0, r1, #1 362 /// => 363 /// sub r0, r1, #1 364 /// addne r0, r1, #1 365 /// 366 /// This may be profitable is conditional instructions are always executed. 367 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 368 MachineBasicBlock &FMBB) const { 369 return false; 370 } 371 372 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 373 virtual void copyPhysReg(MachineBasicBlock &MBB, 374 MachineBasicBlock::iterator MI, DebugLoc DL, 375 unsigned DestReg, unsigned SrcReg, 376 bool KillSrc) const { 377 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 378 } 379 380 /// storeRegToStackSlot - Store the specified register of the given register 381 /// class to the specified stack frame index. The store instruction is to be 382 /// added to the given machine basic block before the specified machine 383 /// instruction. If isKill is true, the register operand is the last use and 384 /// must be marked kill. 385 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 386 MachineBasicBlock::iterator MI, 387 unsigned SrcReg, bool isKill, int FrameIndex, 388 const TargetRegisterClass *RC, 389 const TargetRegisterInfo *TRI) const { 390 llvm_unreachable("Target didn't implement " 391 "TargetInstrInfo::storeRegToStackSlot!"); 392 } 393 394 /// loadRegFromStackSlot - Load the specified register of the given register 395 /// class from the specified stack frame index. The load instruction is to be 396 /// added to the given machine basic block before the specified machine 397 /// instruction. 398 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 399 MachineBasicBlock::iterator MI, 400 unsigned DestReg, int FrameIndex, 401 const TargetRegisterClass *RC, 402 const TargetRegisterInfo *TRI) const { 403 llvm_unreachable("Target didn't implement " 404 "TargetInstrInfo::loadRegFromStackSlot!"); 405 } 406 407 /// expandPostRAPseudo - This function is called for all pseudo instructions 408 /// that remain after register allocation. Many pseudo instructions are 409 /// created to help register allocation. This is the place to convert them 410 /// into real instructions. The target can edit MI in place, or it can insert 411 /// new instructions and erase MI. The function should return true if 412 /// anything was changed. 413 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 414 return false; 415 } 416 417 /// emitFrameIndexDebugValue - Emit a target-dependent form of 418 /// DBG_VALUE encoding the address of a frame index. Addresses would 419 /// normally be lowered the same way as other addresses on the target, 420 /// e.g. in load instructions. For targets that do not support this 421 /// the debug info is simply lost. 422 /// If you add this for a target you should handle this DBG_VALUE in the 423 /// target-specific AsmPrinter code as well; you will probably get invalid 424 /// assembly output if you don't. 425 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 426 int FrameIx, 427 uint64_t Offset, 428 const MDNode *MDPtr, 429 DebugLoc dl) const { 430 return 0; 431 } 432 433 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 434 /// slot into the specified machine instruction for the specified operand(s). 435 /// If this is possible, a new instruction is returned with the specified 436 /// operand folded, otherwise NULL is returned. 437 /// The new instruction is inserted before MI, and the client is responsible 438 /// for removing the old instruction. 439 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 440 const SmallVectorImpl<unsigned> &Ops, 441 int FrameIndex) const; 442 443 /// foldMemoryOperand - Same as the previous version except it allows folding 444 /// of any load and store from / to any address, not just from a specific 445 /// stack slot. 446 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 447 const SmallVectorImpl<unsigned> &Ops, 448 MachineInstr* LoadMI) const; 449 450protected: 451 /// foldMemoryOperandImpl - Target-dependent implementation for 452 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 453 /// take care of adding a MachineMemOperand to the newly created instruction. 454 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 455 MachineInstr* MI, 456 const SmallVectorImpl<unsigned> &Ops, 457 int FrameIndex) const { 458 return 0; 459 } 460 461 /// foldMemoryOperandImpl - Target-dependent implementation for 462 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 463 /// take care of adding a MachineMemOperand to the newly created instruction. 464 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 465 MachineInstr* MI, 466 const SmallVectorImpl<unsigned> &Ops, 467 MachineInstr* LoadMI) const { 468 return 0; 469 } 470 471public: 472 /// canFoldMemoryOperand - Returns true for the specified load / store if 473 /// folding is possible. 474 virtual 475 bool canFoldMemoryOperand(const MachineInstr *MI, 476 const SmallVectorImpl<unsigned> &Ops) const =0; 477 478 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 479 /// a store or a load and a store into two or more instruction. If this is 480 /// possible, returns true as well as the new instructions by reference. 481 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 482 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 483 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 484 return false; 485 } 486 487 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 488 SmallVectorImpl<SDNode*> &NewNodes) const { 489 return false; 490 } 491 492 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 493 /// instruction after load / store are unfolded from an instruction of the 494 /// specified opcode. It returns zero if the specified unfolding is not 495 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 496 /// index of the operand which will hold the register holding the loaded 497 /// value. 498 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 499 bool UnfoldLoad, bool UnfoldStore, 500 unsigned *LoadRegIndex = 0) const { 501 return 0; 502 } 503 504 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 505 /// to determine if two loads are loading from the same base address. It 506 /// should only return true if the base pointers are the same and the 507 /// only differences between the two addresses are the offset. It also returns 508 /// the offsets by reference. 509 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 510 int64_t &Offset1, int64_t &Offset2) const { 511 return false; 512 } 513 514 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 515 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 516 /// be scheduled togther. On some targets if two loads are loading from 517 /// addresses in the same cache line, it's better if they are scheduled 518 /// together. This function takes two integers that represent the load offsets 519 /// from the common base address. It returns true if it decides it's desirable 520 /// to schedule the two loads together. "NumLoads" is the number of loads that 521 /// have already been scheduled after Load1. 522 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 523 int64_t Offset1, int64_t Offset2, 524 unsigned NumLoads) const { 525 return false; 526 } 527 528 /// ReverseBranchCondition - Reverses the branch condition of the specified 529 /// condition list, returning false on success and true if it cannot be 530 /// reversed. 531 virtual 532 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 533 return true; 534 } 535 536 /// insertNoop - Insert a noop into the instruction stream at the specified 537 /// point. 538 virtual void insertNoop(MachineBasicBlock &MBB, 539 MachineBasicBlock::iterator MI) const; 540 541 542 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 543 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 544 // Default to just using 'nop' string. 545 } 546 547 548 /// isPredicated - Returns true if the instruction is already predicated. 549 /// 550 virtual bool isPredicated(const MachineInstr *MI) const { 551 return false; 552 } 553 554 /// isUnpredicatedTerminator - Returns true if the instruction is a 555 /// terminator instruction that has not been predicated. 556 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const = 0; 557 558 /// PredicateInstruction - Convert the instruction into a predicated 559 /// instruction. It returns true if the operation was successful. 560 virtual 561 bool PredicateInstruction(MachineInstr *MI, 562 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 563 564 /// SubsumesPredicate - Returns true if the first specified predicate 565 /// subsumes the second, e.g. GE subsumes GT. 566 virtual 567 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 568 const SmallVectorImpl<MachineOperand> &Pred2) const { 569 return false; 570 } 571 572 /// DefinesPredicate - If the specified instruction defines any predicate 573 /// or condition code register(s) used for predication, returns true as well 574 /// as the definition predicate(s) by reference. 575 virtual bool DefinesPredicate(MachineInstr *MI, 576 std::vector<MachineOperand> &Pred) const { 577 return false; 578 } 579 580 /// isPredicable - Return true if the specified instruction can be predicated. 581 /// By default, this returns true for every instruction with a 582 /// PredicateOperand. 583 virtual bool isPredicable(MachineInstr *MI) const { 584 return MI->getDesc().isPredicable(); 585 } 586 587 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 588 /// instruction that defines the specified register class. 589 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 590 return true; 591 } 592 593 /// isSchedulingBoundary - Test if the given instruction should be 594 /// considered a scheduling boundary. This primarily includes labels and 595 /// terminators. 596 virtual bool isSchedulingBoundary(const MachineInstr *MI, 597 const MachineBasicBlock *MBB, 598 const MachineFunction &MF) const = 0; 599 600 /// Measure the specified inline asm to determine an approximation of its 601 /// length. 602 virtual unsigned getInlineAsmLength(const char *Str, 603 const MCAsmInfo &MAI) const; 604 605 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 606 /// use for this target when scheduling the machine instructions before 607 /// register allocation. 608 virtual ScheduleHazardRecognizer* 609 CreateTargetHazardRecognizer(const TargetMachine *TM, 610 const ScheduleDAG *DAG) const = 0; 611 612 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer 613 /// to use for this target when scheduling the machine instructions before 614 /// register allocation. 615 virtual ScheduleHazardRecognizer* 616 CreateTargetMIHazardRecognizer(const InstrItineraryData*, 617 const ScheduleDAG *DAG) const = 0; 618 619 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 620 /// recognizer to use for this target when scheduling the machine instructions 621 /// after register allocation. 622 virtual ScheduleHazardRecognizer* 623 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 624 const ScheduleDAG *DAG) const = 0; 625 626 /// AnalyzeCompare - For a comparison instruction, return the source register 627 /// in SrcReg and the value it compares against in CmpValue. Return true if 628 /// the comparison instruction can be analyzed. 629 virtual bool AnalyzeCompare(const MachineInstr *MI, 630 unsigned &SrcReg, int &Mask, int &Value) const { 631 return false; 632 } 633 634 /// OptimizeCompareInstr - See if the comparison instruction can be converted 635 /// into something more efficient. E.g., on ARM most instructions can set the 636 /// flags register, obviating the need for a separate CMP. 637 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, 638 unsigned SrcReg, int Mask, int Value, 639 const MachineRegisterInfo *MRI) const { 640 return false; 641 } 642 643 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 644 /// instruction, try to fold the immediate into the use instruction. 645 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 646 unsigned Reg, MachineRegisterInfo *MRI) const { 647 return false; 648 } 649 650 /// getNumMicroOps - Return the number of u-operations the given machine 651 /// instruction will be decoded to on the target cpu. The itinerary's 652 /// IssueWidth is the number of microops that can be dispatched each 653 /// cycle. An instruction with zero microops takes no dispatch resources. 654 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 655 const MachineInstr *MI) const = 0; 656 657 /// isZeroCost - Return true for pseudo instructions that don't consume any 658 /// machine resources in their current form. These are common cases that the 659 /// scheduler should consider free, rather than conservatively handling them 660 /// as instructions with no itinerary. 661 bool isZeroCost(unsigned Opcode) const { 662 return Opcode <= TargetOpcode::COPY; 663 } 664 665 virtual int getOperandLatency(const InstrItineraryData *ItinData, 666 SDNode *DefNode, unsigned DefIdx, 667 SDNode *UseNode, unsigned UseIdx) const = 0; 668 669 /// getOperandLatency - Compute and return the use operand latency of a given 670 /// pair of def and use. 671 /// In most cases, the static scheduling itinerary was enough to determine the 672 /// operand latency. But it may not be possible for instructions with variable 673 /// number of defs / uses. 674 /// 675 /// This is a raw interface to the itinerary that may be directly overriden by 676 /// a target. Use computeOperandLatency to get the best estimate of latency. 677 virtual int getOperandLatency(const InstrItineraryData *ItinData, 678 const MachineInstr *DefMI, unsigned DefIdx, 679 const MachineInstr *UseMI, 680 unsigned UseIdx) const = 0; 681 682 /// computeOperandLatency - Compute and return the latency of the given data 683 /// dependent def and use when the operand indices are already known. 684 /// 685 /// FindMin may be set to get the minimum vs. expected latency. 686 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 687 const MachineInstr *DefMI, unsigned DefIdx, 688 const MachineInstr *UseMI, unsigned UseIdx, 689 bool FindMin = false) const; 690 691 /// computeOperandLatency - Compute and return the latency of the given data 692 /// dependent def and use. DefMI must be a valid def. UseMI may be NULL for 693 /// an unknown use. If the subtarget allows, this may or may not need to call 694 /// getOperandLatency(). 695 /// 696 /// FindMin may be set to get the minimum vs. expected latency. Minimum 697 /// latency is used for scheduling groups, while expected latency is for 698 /// instruction cost and critical path. 699 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 700 const TargetRegisterInfo *TRI, 701 const MachineInstr *DefMI, 702 const MachineInstr *UseMI, 703 unsigned Reg, bool FindMin) const; 704 705 /// getOutputLatency - Compute and return the output dependency latency of a 706 /// a given pair of defs which both target the same register. This is usually 707 /// one. 708 virtual unsigned getOutputLatency(const InstrItineraryData *ItinData, 709 const MachineInstr *DefMI, unsigned DefIdx, 710 const MachineInstr *DepMI) const { 711 return 1; 712 } 713 714 /// getInstrLatency - Compute the instruction latency of a given instruction. 715 /// If the instruction has higher cost when predicated, it's returned via 716 /// PredCost. 717 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 718 const MachineInstr *MI, 719 unsigned *PredCost = 0) const = 0; 720 721 virtual int getInstrLatency(const InstrItineraryData *ItinData, 722 SDNode *Node) const = 0; 723 724 /// Return the default expected latency for a def based on it's opcode. 725 unsigned defaultDefLatency(const InstrItineraryData *ItinData, 726 const MachineInstr *DefMI) const; 727 728 /// isHighLatencyDef - Return true if this opcode has high latency to its 729 /// result. 730 virtual bool isHighLatencyDef(int opc) const { return false; } 731 732 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 733 /// and an use in the current loop, return true if the target considered 734 /// it 'high'. This is used by optimization passes such as machine LICM to 735 /// determine whether it makes sense to hoist an instruction out even in 736 /// high register pressure situation. 737 virtual 738 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 739 const MachineRegisterInfo *MRI, 740 const MachineInstr *DefMI, unsigned DefIdx, 741 const MachineInstr *UseMI, unsigned UseIdx) const { 742 return false; 743 } 744 745 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 746 /// if the target considered it 'low'. 747 virtual 748 bool hasLowDefLatency(const InstrItineraryData *ItinData, 749 const MachineInstr *DefMI, unsigned DefIdx) const = 0; 750 751 /// verifyInstruction - Perform target specific instruction verification. 752 virtual 753 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { 754 return true; 755 } 756 757 /// getExecutionDomain - Return the current execution domain and bit mask of 758 /// possible domains for instruction. 759 /// 760 /// Some micro-architectures have multiple execution domains, and multiple 761 /// opcodes that perform the same operation in different domains. For 762 /// example, the x86 architecture provides the por, orps, and orpd 763 /// instructions that all do the same thing. There is a latency penalty if a 764 /// register is written in one domain and read in another. 765 /// 766 /// This function returns a pair (domain, mask) containing the execution 767 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 768 /// function can be used to change the opcode to one of the domains in the 769 /// bit mask. Instructions whose execution domain can't be changed should 770 /// return a 0 mask. 771 /// 772 /// The execution domain numbers don't have any special meaning except domain 773 /// 0 is used for instructions that are not associated with any interesting 774 /// execution domain. 775 /// 776 virtual std::pair<uint16_t, uint16_t> 777 getExecutionDomain(const MachineInstr *MI) const { 778 return std::make_pair(0, 0); 779 } 780 781 /// setExecutionDomain - Change the opcode of MI to execute in Domain. 782 /// 783 /// The bit (1 << Domain) must be set in the mask returned from 784 /// getExecutionDomain(MI). 785 /// 786 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} 787 788 789 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance 790 /// before an instruction with an unwanted partial register update. 791 /// 792 /// Some instructions only write part of a register, and implicitly need to 793 /// read the other parts of the register. This may cause unwanted stalls 794 /// preventing otherwise unrelated instructions from executing in parallel in 795 /// an out-of-order CPU. 796 /// 797 /// For example, the x86 instruction cvtsi2ss writes its result to bits 798 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 799 /// the instruction needs to wait for the old value of the register to become 800 /// available: 801 /// 802 /// addps %xmm1, %xmm0 803 /// movaps %xmm0, (%rax) 804 /// cvtsi2ss %rbx, %xmm0 805 /// 806 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 807 /// instruction before it can issue, even though the high bits of %xmm0 808 /// probably aren't needed. 809 /// 810 /// This hook returns the preferred clearance before MI, measured in 811 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 812 /// instructions before MI. It should only return a positive value for 813 /// unwanted dependencies. If the old bits of the defined register have 814 /// useful values, or if MI is determined to otherwise read the dependency, 815 /// the hook should return 0. 816 /// 817 /// The unwanted dependency may be handled by: 818 /// 819 /// 1. Allocating the same register for an MI def and use. That makes the 820 /// unwanted dependency identical to a required dependency. 821 /// 822 /// 2. Allocating a register for the def that has no defs in the previous N 823 /// instructions. 824 /// 825 /// 3. Calling breakPartialRegDependency() with the same arguments. This 826 /// allows the target to insert a dependency breaking instruction. 827 /// 828 virtual unsigned 829 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 830 const TargetRegisterInfo *TRI) const { 831 // The default implementation returns 0 for no partial register dependency. 832 return 0; 833 } 834 835 /// breakPartialRegDependency - Insert a dependency-breaking instruction 836 /// before MI to eliminate an unwanted dependency on OpNum. 837 /// 838 /// If it wasn't possible to avoid a def in the last N instructions before MI 839 /// (see getPartialRegUpdateClearance), this hook will be called to break the 840 /// unwanted dependency. 841 /// 842 /// On x86, an xorps instruction can be used as a dependency breaker: 843 /// 844 /// addps %xmm1, %xmm0 845 /// movaps %xmm0, (%rax) 846 /// xorps %xmm0, %xmm0 847 /// cvtsi2ss %rbx, %xmm0 848 /// 849 /// An <imp-kill> operand should be added to MI if an instruction was 850 /// inserted. This ties the instructions together in the post-ra scheduler. 851 /// 852 virtual void 853 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 854 const TargetRegisterInfo *TRI) const {} 855 856 /// Create machine specific model for scheduling. 857 virtual DFAPacketizer* 858 CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const { 859 return NULL; 860 } 861 862private: 863 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 864}; 865 866/// TargetInstrInfoImpl - This is the default implementation of 867/// TargetInstrInfo, which just provides a couple of default implementations 868/// for various methods. This separated out because it is implemented in 869/// libcodegen, not in libtarget. 870class TargetInstrInfoImpl : public TargetInstrInfo { 871protected: 872 TargetInstrInfoImpl(int CallFrameSetupOpcode = -1, 873 int CallFrameDestroyOpcode = -1) 874 : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 875public: 876 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 877 MachineBasicBlock *NewDest) const; 878 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 879 bool NewMI = false) const; 880 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 881 unsigned &SrcOpIdx2) const; 882 virtual bool canFoldMemoryOperand(const MachineInstr *MI, 883 const SmallVectorImpl<unsigned> &Ops) const; 884 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 885 const MachineMemOperand *&MMO, 886 int &FrameIndex) const; 887 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 888 const MachineMemOperand *&MMO, 889 int &FrameIndex) const; 890 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 891 virtual bool PredicateInstruction(MachineInstr *MI, 892 const SmallVectorImpl<MachineOperand> &Pred) const; 893 virtual void reMaterialize(MachineBasicBlock &MBB, 894 MachineBasicBlock::iterator MI, 895 unsigned DestReg, unsigned SubReg, 896 const MachineInstr *Orig, 897 const TargetRegisterInfo &TRI) const; 898 virtual MachineInstr *duplicate(MachineInstr *Orig, 899 MachineFunction &MF) const; 900 virtual bool produceSameValue(const MachineInstr *MI0, 901 const MachineInstr *MI1, 902 const MachineRegisterInfo *MRI) const; 903 virtual bool isSchedulingBoundary(const MachineInstr *MI, 904 const MachineBasicBlock *MBB, 905 const MachineFunction &MF) const; 906 907 virtual int getOperandLatency(const InstrItineraryData *ItinData, 908 SDNode *DefNode, unsigned DefIdx, 909 SDNode *UseNode, unsigned UseIdx) const; 910 911 virtual int getInstrLatency(const InstrItineraryData *ItinData, 912 SDNode *Node) const; 913 914 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 915 const MachineInstr *MI) const; 916 917 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 918 const MachineInstr *MI, 919 unsigned *PredCost = 0) const; 920 921 virtual 922 bool hasLowDefLatency(const InstrItineraryData *ItinData, 923 const MachineInstr *DefMI, unsigned DefIdx) const; 924 925 virtual int getOperandLatency(const InstrItineraryData *ItinData, 926 const MachineInstr *DefMI, unsigned DefIdx, 927 const MachineInstr *UseMI, 928 unsigned UseIdx) const; 929 930 bool usePreRAHazardRecognizer() const; 931 932 virtual ScheduleHazardRecognizer * 933 CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const; 934 935 virtual ScheduleHazardRecognizer * 936 CreateTargetMIHazardRecognizer(const InstrItineraryData*, 937 const ScheduleDAG*) const; 938 939 virtual ScheduleHazardRecognizer * 940 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 941 const ScheduleDAG*) const; 942}; 943 944} // End llvm namespace 945 946#endif 947