TargetInstrInfo.h revision 11e8b74a7ae9ecd59b64180a59143e39bc3b9514
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class CalleeSavedInfo; 23class InstrItineraryData; 24class LiveVariables; 25class MCAsmInfo; 26class MachineMemOperand; 27class MachineRegisterInfo; 28class MDNode; 29class MCInst; 30class SDNode; 31class ScheduleHazardRecognizer; 32class SelectionDAG; 33class TargetRegisterClass; 34class TargetRegisterInfo; 35 36template<class T> class SmallVectorImpl; 37 38 39//--------------------------------------------------------------------------- 40/// 41/// TargetInstrInfo - Interface to description of machine instruction set 42/// 43class TargetInstrInfo { 44 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 45 unsigned NumOpcodes; // Number of entries in the desc array 46 47 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 48 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 49public: 50 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 51 virtual ~TargetInstrInfo(); 52 53 unsigned getNumOpcodes() const { return NumOpcodes; } 54 55 /// get - Return the machine instruction descriptor that corresponds to the 56 /// specified instruction opcode. 57 /// 58 const TargetInstrDesc &get(unsigned Opcode) const { 59 assert(Opcode < NumOpcodes && "Invalid opcode!"); 60 return Descriptors[Opcode]; 61 } 62 63 /// isTriviallyReMaterializable - Return true if the instruction is trivially 64 /// rematerializable, meaning it has no side effects and requires no operands 65 /// that aren't always available. 66 bool isTriviallyReMaterializable(const MachineInstr *MI, 67 AliasAnalysis *AA = 0) const { 68 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 69 (MI->getDesc().isRematerializable() && 70 (isReallyTriviallyReMaterializable(MI, AA) || 71 isReallyTriviallyReMaterializableGeneric(MI, AA))); 72 } 73 74protected: 75 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 76 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 77 /// specify whether the instruction is actually trivially rematerializable, 78 /// taking into consideration its operands. This predicate must return false 79 /// if the instruction has any side effects other than producing a value, or 80 /// if it requres any address registers that are not always available. 81 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 82 AliasAnalysis *AA) const { 83 return false; 84 } 85 86private: 87 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 88 /// for which the M_REMATERIALIZABLE flag is set and the target hook 89 /// isReallyTriviallyReMaterializable returns false, this function does 90 /// target-independent tests to determine if the instruction is really 91 /// trivially rematerializable. 92 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 93 AliasAnalysis *AA) const; 94 95public: 96 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 97 /// extension instruction. That is, it's like a copy where it's legal for the 98 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 99 /// true, then it's expected the pre-extension value is available as a subreg 100 /// of the result register. This also returns the sub-register index in 101 /// SubIdx. 102 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 103 unsigned &SrcReg, unsigned &DstReg, 104 unsigned &SubIdx) const { 105 return false; 106 } 107 108 /// isLoadFromStackSlot - If the specified machine instruction is a direct 109 /// load from a stack slot, return the virtual or physical register number of 110 /// the destination along with the FrameIndex of the loaded stack slot. If 111 /// not, return 0. This predicate must return 0 if the instruction has 112 /// any side effects other than loading from the stack slot. 113 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 114 int &FrameIndex) const { 115 return 0; 116 } 117 118 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 119 /// stack locations as well. This uses a heuristic so it isn't 120 /// reliable for correctness. 121 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 122 int &FrameIndex) const { 123 return 0; 124 } 125 126 /// hasLoadFromStackSlot - If the specified machine instruction has 127 /// a load from a stack slot, return true along with the FrameIndex 128 /// of the loaded stack slot and the machine mem operand containing 129 /// the reference. If not, return false. Unlike 130 /// isLoadFromStackSlot, this returns true for any instructions that 131 /// loads from the stack. This is just a hint, as some cases may be 132 /// missed. 133 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 134 const MachineMemOperand *&MMO, 135 int &FrameIndex) const { 136 return 0; 137 } 138 139 /// isStoreToStackSlot - If the specified machine instruction is a direct 140 /// store to a stack slot, return the virtual or physical register number of 141 /// the source reg along with the FrameIndex of the loaded stack slot. If 142 /// not, return 0. This predicate must return 0 if the instruction has 143 /// any side effects other than storing to the stack slot. 144 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 145 int &FrameIndex) const { 146 return 0; 147 } 148 149 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 150 /// stack locations as well. This uses a heuristic so it isn't 151 /// reliable for correctness. 152 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 153 int &FrameIndex) const { 154 return 0; 155 } 156 157 /// hasStoreToStackSlot - If the specified machine instruction has a 158 /// store to a stack slot, return true along with the FrameIndex of 159 /// the loaded stack slot and the machine mem operand containing the 160 /// reference. If not, return false. Unlike isStoreToStackSlot, 161 /// this returns true for any instructions that stores to the 162 /// stack. This is just a hint, as some cases may be missed. 163 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 164 const MachineMemOperand *&MMO, 165 int &FrameIndex) const { 166 return 0; 167 } 168 169 /// reMaterialize - Re-issue the specified 'original' instruction at the 170 /// specific location targeting a new destination register. 171 /// The register in Orig->getOperand(0).getReg() will be substituted by 172 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 173 /// SubIdx. 174 virtual void reMaterialize(MachineBasicBlock &MBB, 175 MachineBasicBlock::iterator MI, 176 unsigned DestReg, unsigned SubIdx, 177 const MachineInstr *Orig, 178 const TargetRegisterInfo &TRI) const = 0; 179 180 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 181 /// two-addrss instruction inserted by two-address pass. 182 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 183 MachineInstr *UseMI, 184 const TargetRegisterInfo &TRI) const { 185 // Do nothing. 186 } 187 188 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 189 /// MachineFunction::CloneMachineInstr(), but the target may update operands 190 /// that are required to be unique. 191 /// 192 /// The instruction must be duplicable as indicated by isNotDuplicable(). 193 virtual MachineInstr *duplicate(MachineInstr *Orig, 194 MachineFunction &MF) const = 0; 195 196 /// convertToThreeAddress - This method must be implemented by targets that 197 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 198 /// may be able to convert a two-address instruction into one or more true 199 /// three-address instructions on demand. This allows the X86 target (for 200 /// example) to convert ADD and SHL instructions into LEA instructions if they 201 /// would require register copies due to two-addressness. 202 /// 203 /// This method returns a null pointer if the transformation cannot be 204 /// performed, otherwise it returns the last new instruction. 205 /// 206 virtual MachineInstr * 207 convertToThreeAddress(MachineFunction::iterator &MFI, 208 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 209 return 0; 210 } 211 212 /// commuteInstruction - If a target has any instructions that are 213 /// commutable but require converting to different instructions or making 214 /// non-trivial changes to commute them, this method can overloaded to do 215 /// that. The default implementation simply swaps the commutable operands. 216 /// If NewMI is false, MI is modified in place and returned; otherwise, a 217 /// new machine instruction is created and returned. Do not call this 218 /// method for a non-commutable instruction, but there may be some cases 219 /// where this method fails and returns null. 220 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 221 bool NewMI = false) const = 0; 222 223 /// findCommutedOpIndices - If specified MI is commutable, return the two 224 /// operand indices that would swap value. Return false if the instruction 225 /// is not in a form which this routine understands. 226 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 227 unsigned &SrcOpIdx2) const = 0; 228 229 /// produceSameValue - Return true if two machine instructions would produce 230 /// identical values. By default, this is only true when the two instructions 231 /// are deemed identical except for defs. 232 virtual bool produceSameValue(const MachineInstr *MI0, 233 const MachineInstr *MI1) const = 0; 234 235 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 236 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 237 /// implemented for a target). Upon success, this returns false and returns 238 /// with the following information in various cases: 239 /// 240 /// 1. If this block ends with no branches (it just falls through to its succ) 241 /// just return false, leaving TBB/FBB null. 242 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 243 /// the destination block. 244 /// 3. If this block ends with a conditional branch and it falls through to a 245 /// successor block, it sets TBB to be the branch destination block and a 246 /// list of operands that evaluate the condition. These operands can be 247 /// passed to other TargetInstrInfo methods to create new branches. 248 /// 4. If this block ends with a conditional branch followed by an 249 /// unconditional branch, it returns the 'true' destination in TBB, the 250 /// 'false' destination in FBB, and a list of operands that evaluate the 251 /// condition. These operands can be passed to other TargetInstrInfo 252 /// methods to create new branches. 253 /// 254 /// Note that RemoveBranch and InsertBranch must be implemented to support 255 /// cases where this method returns success. 256 /// 257 /// If AllowModify is true, then this routine is allowed to modify the basic 258 /// block (e.g. delete instructions after the unconditional branch). 259 /// 260 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 261 MachineBasicBlock *&FBB, 262 SmallVectorImpl<MachineOperand> &Cond, 263 bool AllowModify = false) const { 264 return true; 265 } 266 267 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 268 /// This is only invoked in cases where AnalyzeBranch returns success. It 269 /// returns the number of instructions that were removed. 270 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 271 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 272 return 0; 273 } 274 275 /// InsertBranch - Insert branch code into the end of the specified 276 /// MachineBasicBlock. The operands to this method are the same as those 277 /// returned by AnalyzeBranch. This is only invoked in cases where 278 /// AnalyzeBranch returns success. It returns the number of instructions 279 /// inserted. 280 /// 281 /// It is also invoked by tail merging to add unconditional branches in 282 /// cases where AnalyzeBranch doesn't apply because there was no original 283 /// branch to analyze. At least this much must be implemented, else tail 284 /// merging needs to be disabled. 285 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 286 MachineBasicBlock *FBB, 287 const SmallVectorImpl<MachineOperand> &Cond, 288 DebugLoc DL) const { 289 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 290 return 0; 291 } 292 293 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 294 /// after it, replacing it with an unconditional branch to NewDest. This is 295 /// used by the tail merging pass. 296 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 297 MachineBasicBlock *NewDest) const = 0; 298 299 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 300 /// block at the specified instruction (i.e. instruction would be the start 301 /// of a new basic block). 302 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 303 MachineBasicBlock::iterator MBBI) const { 304 return true; 305 } 306 307 /// isProfitableToIfCvt - Return true if it's profitable to first "NumInstrs" 308 /// of the specified basic block, where the probability of the instructions 309 /// being executed is given by Probability, and Confidence is a measure 310 /// of our confidence that it will be properly predicted. 311 virtual 312 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs, 313 float Probability, float Confidence) const { 314 return false; 315 } 316 317 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 318 /// checks for the case where two basic blocks from true and false path 319 /// of a if-then-else (diamond) are predicated on mutally exclusive 320 /// predicates, where the probability of the true path being taken is given 321 /// by Probability, and Confidence is a measure of our confidence that it 322 /// will be properly predicted. 323 virtual bool 324 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs, 325 MachineBasicBlock &FMBB, unsigned NumFInstrs, 326 float Probability, float Confidence) const { 327 return false; 328 } 329 330 /// isProfitableToDupForIfCvt - Return true if it's profitable for 331 /// if-converter to duplicate a specific number of instructions in the 332 /// specified MBB to enable if-conversion, where the probability of the 333 /// instructions being executed is given by Probability, and Confidence is 334 /// a measure of our confidence that it will be properly predicted. 335 virtual bool 336 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs, 337 float Probability, float Confidence) const { 338 return false; 339 } 340 341 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 342 virtual void copyPhysReg(MachineBasicBlock &MBB, 343 MachineBasicBlock::iterator MI, DebugLoc DL, 344 unsigned DestReg, unsigned SrcReg, 345 bool KillSrc) const { 346 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!"); 347 } 348 349 /// storeRegToStackSlot - Store the specified register of the given register 350 /// class to the specified stack frame index. The store instruction is to be 351 /// added to the given machine basic block before the specified machine 352 /// instruction. If isKill is true, the register operand is the last use and 353 /// must be marked kill. 354 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 355 MachineBasicBlock::iterator MI, 356 unsigned SrcReg, bool isKill, int FrameIndex, 357 const TargetRegisterClass *RC, 358 const TargetRegisterInfo *TRI) const { 359 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 360 } 361 362 /// loadRegFromStackSlot - Load the specified register of the given register 363 /// class from the specified stack frame index. The load instruction is to be 364 /// added to the given machine basic block before the specified machine 365 /// instruction. 366 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 367 MachineBasicBlock::iterator MI, 368 unsigned DestReg, int FrameIndex, 369 const TargetRegisterClass *RC, 370 const TargetRegisterInfo *TRI) const { 371 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 372 } 373 374 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 375 /// saved registers and returns true if it isn't possible / profitable to do 376 /// so by issuing a series of store instructions via 377 /// storeRegToStackSlot(). Returns false otherwise. 378 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 379 MachineBasicBlock::iterator MI, 380 const std::vector<CalleeSavedInfo> &CSI, 381 const TargetRegisterInfo *TRI) const { 382 return false; 383 } 384 385 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 386 /// saved registers and returns true if it isn't possible / profitable to do 387 /// so by issuing a series of load instructions via loadRegToStackSlot(). 388 /// Returns false otherwise. 389 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 390 MachineBasicBlock::iterator MI, 391 const std::vector<CalleeSavedInfo> &CSI, 392 const TargetRegisterInfo *TRI) const { 393 return false; 394 } 395 396 /// emitFrameIndexDebugValue - Emit a target-dependent form of 397 /// DBG_VALUE encoding the address of a frame index. Addresses would 398 /// normally be lowered the same way as other addresses on the target, 399 /// e.g. in load instructions. For targets that do not support this 400 /// the debug info is simply lost. 401 /// If you add this for a target you should handle this DBG_VALUE in the 402 /// target-specific AsmPrinter code as well; you will probably get invalid 403 /// assembly output if you don't. 404 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 405 int FrameIx, 406 uint64_t Offset, 407 const MDNode *MDPtr, 408 DebugLoc dl) const { 409 return 0; 410 } 411 412 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 413 /// slot into the specified machine instruction for the specified operand(s). 414 /// If this is possible, a new instruction is returned with the specified 415 /// operand folded, otherwise NULL is returned. 416 /// The new instruction is inserted before MI, and the client is responsible 417 /// for removing the old instruction. 418 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 419 const SmallVectorImpl<unsigned> &Ops, 420 int FrameIndex) const; 421 422 /// foldMemoryOperand - Same as the previous version except it allows folding 423 /// of any load and store from / to any address, not just from a specific 424 /// stack slot. 425 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 426 const SmallVectorImpl<unsigned> &Ops, 427 MachineInstr* LoadMI) const; 428 429protected: 430 /// foldMemoryOperandImpl - Target-dependent implementation for 431 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 432 /// take care of adding a MachineMemOperand to the newly created instruction. 433 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 434 MachineInstr* MI, 435 const SmallVectorImpl<unsigned> &Ops, 436 int FrameIndex) const { 437 return 0; 438 } 439 440 /// foldMemoryOperandImpl - Target-dependent implementation for 441 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 442 /// take care of adding a MachineMemOperand to the newly created instruction. 443 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 444 MachineInstr* MI, 445 const SmallVectorImpl<unsigned> &Ops, 446 MachineInstr* LoadMI) const { 447 return 0; 448 } 449 450public: 451 /// canFoldMemoryOperand - Returns true for the specified load / store if 452 /// folding is possible. 453 virtual 454 bool canFoldMemoryOperand(const MachineInstr *MI, 455 const SmallVectorImpl<unsigned> &Ops) const =0; 456 457 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 458 /// a store or a load and a store into two or more instruction. If this is 459 /// possible, returns true as well as the new instructions by reference. 460 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 461 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 462 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 463 return false; 464 } 465 466 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 467 SmallVectorImpl<SDNode*> &NewNodes) const { 468 return false; 469 } 470 471 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 472 /// instruction after load / store are unfolded from an instruction of the 473 /// specified opcode. It returns zero if the specified unfolding is not 474 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 475 /// index of the operand which will hold the register holding the loaded 476 /// value. 477 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 478 bool UnfoldLoad, bool UnfoldStore, 479 unsigned *LoadRegIndex = 0) const { 480 return 0; 481 } 482 483 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 484 /// to determine if two loads are loading from the same base address. It 485 /// should only return true if the base pointers are the same and the 486 /// only differences between the two addresses are the offset. It also returns 487 /// the offsets by reference. 488 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 489 int64_t &Offset1, int64_t &Offset2) const { 490 return false; 491 } 492 493 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 494 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 495 /// be scheduled togther. On some targets if two loads are loading from 496 /// addresses in the same cache line, it's better if they are scheduled 497 /// together. This function takes two integers that represent the load offsets 498 /// from the common base address. It returns true if it decides it's desirable 499 /// to schedule the two loads together. "NumLoads" is the number of loads that 500 /// have already been scheduled after Load1. 501 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 502 int64_t Offset1, int64_t Offset2, 503 unsigned NumLoads) const { 504 return false; 505 } 506 507 /// ReverseBranchCondition - Reverses the branch condition of the specified 508 /// condition list, returning false on success and true if it cannot be 509 /// reversed. 510 virtual 511 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 512 return true; 513 } 514 515 /// insertNoop - Insert a noop into the instruction stream at the specified 516 /// point. 517 virtual void insertNoop(MachineBasicBlock &MBB, 518 MachineBasicBlock::iterator MI) const; 519 520 521 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 522 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 523 // Default to just using 'nop' string. 524 } 525 526 527 /// isPredicated - Returns true if the instruction is already predicated. 528 /// 529 virtual bool isPredicated(const MachineInstr *MI) const { 530 return false; 531 } 532 533 /// isUnpredicatedTerminator - Returns true if the instruction is a 534 /// terminator instruction that has not been predicated. 535 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 536 537 /// PredicateInstruction - Convert the instruction into a predicated 538 /// instruction. It returns true if the operation was successful. 539 virtual 540 bool PredicateInstruction(MachineInstr *MI, 541 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 542 543 /// SubsumesPredicate - Returns true if the first specified predicate 544 /// subsumes the second, e.g. GE subsumes GT. 545 virtual 546 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 547 const SmallVectorImpl<MachineOperand> &Pred2) const { 548 return false; 549 } 550 551 /// DefinesPredicate - If the specified instruction defines any predicate 552 /// or condition code register(s) used for predication, returns true as well 553 /// as the definition predicate(s) by reference. 554 virtual bool DefinesPredicate(MachineInstr *MI, 555 std::vector<MachineOperand> &Pred) const { 556 return false; 557 } 558 559 /// isPredicable - Return true if the specified instruction can be predicated. 560 /// By default, this returns true for every instruction with a 561 /// PredicateOperand. 562 virtual bool isPredicable(MachineInstr *MI) const { 563 return MI->getDesc().isPredicable(); 564 } 565 566 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 567 /// instruction that defines the specified register class. 568 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 569 return true; 570 } 571 572 /// isSchedulingBoundary - Test if the given instruction should be 573 /// considered a scheduling boundary. This primarily includes labels and 574 /// terminators. 575 virtual bool isSchedulingBoundary(const MachineInstr *MI, 576 const MachineBasicBlock *MBB, 577 const MachineFunction &MF) const = 0; 578 579 /// Measure the specified inline asm to determine an approximation of its 580 /// length. 581 virtual unsigned getInlineAsmLength(const char *Str, 582 const MCAsmInfo &MAI) const; 583 584 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer 585 /// to use for this target when scheduling the machine instructions after 586 /// register allocation. 587 virtual ScheduleHazardRecognizer* 588 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const = 0; 589 590 /// AnalyzeCompare - For a comparison instruction, return the source register 591 /// in SrcReg and the value it compares against in CmpValue. Return true if 592 /// the comparison instruction can be analyzed. 593 virtual bool AnalyzeCompare(const MachineInstr *MI, 594 unsigned &SrcReg, int &Mask, int &Value) const { 595 return false; 596 } 597 598 /// OptimizeCompareInstr - See if the comparison instruction can be converted 599 /// into something more efficient. E.g., on ARM most instructions can set the 600 /// flags register, obviating the need for a separate CMP. Update the iterator 601 /// *only* if a transformation took place. 602 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, 603 unsigned SrcReg, int Mask, int Value, 604 const MachineRegisterInfo *MRI, 605 MachineBasicBlock::iterator &) const { 606 return false; 607 } 608 609 /// getNumMicroOps - Return the number of u-operations the given machine 610 /// instruction will be decoded to on the target cpu. 611 virtual unsigned getNumMicroOps(const MachineInstr *MI, 612 const InstrItineraryData *ItinData) const; 613 614 /// getOperandLatency - Compute and return the use operand latency of a given 615 /// itinerary class and operand index if the value is produced by an 616 /// instruction of the specified itinerary class and def operand index. 617 /// In most cases, the static scheduling itinerary was enough to determine the 618 /// operand latency. But it may not be possible for instructions with variable 619 /// number of defs / uses. 620 virtual 621 int getOperandLatency(const InstrItineraryData *ItinData, 622 const MachineInstr *DefMI, unsigned DefIdx, 623 const MachineInstr *UseMI, unsigned UseIdx) const; 624 625 virtual 626 int getOperandLatency(const InstrItineraryData *ItinData, 627 SDNode *DefNode, unsigned DefIdx, 628 SDNode *UseNode, unsigned UseIdx) const; 629 630 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 631 /// and an use in the current loop, return true if the target considered 632 /// it 'high'. This is used by optimization passes such as machine LICM to 633 /// determine whether it makes sense to hoist an instruction out even in 634 /// high register pressure situation. 635 virtual 636 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 637 const MachineRegisterInfo *MRI, 638 const MachineInstr *DefMI, unsigned DefIdx, 639 const MachineInstr *UseMI, unsigned UseIdx) const { 640 return false; 641 } 642}; 643 644/// TargetInstrInfoImpl - This is the default implementation of 645/// TargetInstrInfo, which just provides a couple of default implementations 646/// for various methods. This separated out because it is implemented in 647/// libcodegen, not in libtarget. 648class TargetInstrInfoImpl : public TargetInstrInfo { 649protected: 650 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 651 : TargetInstrInfo(desc, NumOpcodes) {} 652public: 653 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 654 MachineBasicBlock *NewDest) const; 655 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 656 bool NewMI = false) const; 657 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 658 unsigned &SrcOpIdx2) const; 659 virtual bool canFoldMemoryOperand(const MachineInstr *MI, 660 const SmallVectorImpl<unsigned> &Ops) const; 661 virtual bool PredicateInstruction(MachineInstr *MI, 662 const SmallVectorImpl<MachineOperand> &Pred) const; 663 virtual void reMaterialize(MachineBasicBlock &MBB, 664 MachineBasicBlock::iterator MI, 665 unsigned DestReg, unsigned SubReg, 666 const MachineInstr *Orig, 667 const TargetRegisterInfo &TRI) const; 668 virtual MachineInstr *duplicate(MachineInstr *Orig, 669 MachineFunction &MF) const; 670 virtual bool produceSameValue(const MachineInstr *MI0, 671 const MachineInstr *MI1) const; 672 virtual bool isSchedulingBoundary(const MachineInstr *MI, 673 const MachineBasicBlock *MBB, 674 const MachineFunction &MF) const; 675 676 virtual ScheduleHazardRecognizer * 677 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const; 678}; 679 680} // End llvm namespace 681 682#endif 683