TargetInstrInfo.h revision 2864eee7a322610a8dc5f01e450a5e1ca477f7e7
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class MachineInstr; 26class TargetMachine; 27class MachineCodeForInstruction; 28class TargetRegisterClass; 29class LiveVariables; 30 31//--------------------------------------------------------------------------- 32// Data types used to define information about a single machine instruction 33//--------------------------------------------------------------------------- 34 35typedef short MachineOpCode; 36typedef unsigned InstrSchedClass; 37 38//--------------------------------------------------------------------------- 39// struct TargetInstrDescriptor: 40// Predefined information about each machine instruction. 41// Designed to initialized statically. 42// 43 44const unsigned M_BRANCH_FLAG = 1 << 0; 45const unsigned M_CALL_FLAG = 1 << 1; 46const unsigned M_RET_FLAG = 1 << 2; 47const unsigned M_BARRIER_FLAG = 1 << 3; 48const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 49const unsigned M_LOAD_FLAG = 1 << 5; 50const unsigned M_STORE_FLAG = 1 << 6; 51 52// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 53// changed into a 3-address instruction if the first two operands cannot be 54// assigned to the same register. The target must implement the 55// TargetInstrInfo::convertToThreeAddress method for this instruction. 56const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 57 58// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 59// Z), which produces the same result if Y and Z are exchanged. 60const unsigned M_COMMUTABLE = 1 << 8; 61 62// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 63// block? Typically this is things like return and branch instructions. 64// Various passes use this to insert code into the bottom of a basic block, but 65// before control flow occurs. 66const unsigned M_TERMINATOR_FLAG = 1 << 9; 67 68// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 69// insertion support when the DAG scheduler is inserting it into a machine basic 70// block. 71const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 72 73// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 74// operands in addition to the minimum number operands specified. 75const unsigned M_VARIABLE_OPS = 1 << 11; 76 77// M_PREDICATED - Set if this instruction has a predicate that controls its 78// execution. 79const unsigned M_PREDICATED = 1 << 12; 80 81 82// Machine operand flags 83// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 84// requires a callback to look up its register class. 85const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 86 87/// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate 88/// operand that controls an M_PREDICATED instruction. 89const unsigned M_PREDICATE_OPERAND = 1 << 1; 90 91namespace TOI { 92 // Operand constraints: only "tied_to" for now. 93 enum OperandConstraint { 94 TIED_TO = 0 // Must be allocated the same register as. 95 }; 96} 97 98/// TargetOperandInfo - This holds information about one operand of a machine 99/// instruction, indicating the register class for register operands, etc. 100/// 101class TargetOperandInfo { 102public: 103 /// RegClass - This specifies the register class enumeration of the operand 104 /// if the operand is a register. If not, this contains 0. 105 unsigned short RegClass; 106 unsigned short Flags; 107 /// Lower 16 bits are used to specify which constraints are set. The higher 16 108 /// bits are used to specify the value of constraints (4 bits each). 109 unsigned int Constraints; 110 /// Currently no other information. 111}; 112 113 114class TargetInstrDescriptor { 115public: 116 MachineOpCode Opcode; // The opcode. 117 unsigned short numOperands; // Num of args (may be more if variable_ops). 118 const char * Name; // Assembly language mnemonic for the opcode. 119 InstrSchedClass schedClass; // enum identifying instr sched class 120 unsigned Flags; // flags identifying machine instr class 121 unsigned TSFlags; // Target Specific Flag values 122 const unsigned *ImplicitUses; // Registers implicitly read by this instr 123 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 124 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 125 126 /// getOperandConstraint - Returns the value of the specific constraint if 127 /// it is set. Returns -1 if it is not set. 128 int getOperandConstraint(unsigned OpNum, 129 TOI::OperandConstraint Constraint) const { 130 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 131 "Invalid operand # of TargetInstrInfo"); 132 if (OpNum < numOperands && 133 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 134 unsigned Pos = 16 + Constraint * 4; 135 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 136 } 137 return -1; 138 } 139 140 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 141 /// dest operand. Returns -1 if there isn't one. 142 int findTiedToSrcOperand(unsigned OpNum) const; 143}; 144 145 146//--------------------------------------------------------------------------- 147/// 148/// TargetInstrInfo - Interface to description of machine instructions 149/// 150class TargetInstrInfo { 151 const TargetInstrDescriptor* desc; // raw array to allow static init'n 152 unsigned NumOpcodes; // number of entries in the desc array 153 unsigned numRealOpCodes; // number of non-dummy op codes 154 155 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 156 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 157public: 158 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 159 virtual ~TargetInstrInfo(); 160 161 // Invariant opcodes: All instruction sets have these as their low opcodes. 162 enum { 163 PHI = 0, 164 INLINEASM = 1, 165 LABEL = 2 166 }; 167 168 unsigned getNumOpcodes() const { return NumOpcodes; } 169 170 /// get - Return the machine instruction descriptor that corresponds to the 171 /// specified instruction opcode. 172 /// 173 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 174 assert((unsigned)Opcode < NumOpcodes); 175 return desc[Opcode]; 176 } 177 178 const char *getName(MachineOpCode Opcode) const { 179 return get(Opcode).Name; 180 } 181 182 int getNumOperands(MachineOpCode Opcode) const { 183 return get(Opcode).numOperands; 184 } 185 186 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 187 return get(Opcode).schedClass; 188 } 189 190 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 191 return get(Opcode).ImplicitUses; 192 } 193 194 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 195 return get(Opcode).ImplicitDefs; 196 } 197 198 199 // 200 // Query instruction class flags according to the machine-independent 201 // flags listed above. 202 // 203 bool isReturn(MachineOpCode Opcode) const { 204 return get(Opcode).Flags & M_RET_FLAG; 205 } 206 207 bool isPredicated(MachineOpCode Opcode) const { 208 return get(Opcode).Flags & M_PREDICATED; 209 } 210 bool isCommutableInstr(MachineOpCode Opcode) const { 211 return get(Opcode).Flags & M_COMMUTABLE; 212 } 213 bool isTerminatorInstr(unsigned Opcode) const { 214 return get(Opcode).Flags & M_TERMINATOR_FLAG; 215 } 216 217 bool isBranch(MachineOpCode Opcode) const { 218 return get(Opcode).Flags & M_BRANCH_FLAG; 219 } 220 221 /// isBarrier - Returns true if the specified instruction stops control flow 222 /// from executing the instruction immediately following it. Examples include 223 /// unconditional branches and return instructions. 224 bool isBarrier(MachineOpCode Opcode) const { 225 return get(Opcode).Flags & M_BARRIER_FLAG; 226 } 227 228 bool isCall(MachineOpCode Opcode) const { 229 return get(Opcode).Flags & M_CALL_FLAG; 230 } 231 bool isLoad(MachineOpCode Opcode) const { 232 return get(Opcode).Flags & M_LOAD_FLAG; 233 } 234 bool isStore(MachineOpCode Opcode) const { 235 return get(Opcode).Flags & M_STORE_FLAG; 236 } 237 238 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 239 /// which must be filled by the code generator. 240 bool hasDelaySlot(unsigned Opcode) const { 241 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 242 } 243 244 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 245 /// custom insertion support when the DAG scheduler is inserting it into a 246 /// machine basic block. 247 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 248 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 249 } 250 251 bool hasVariableOperands(MachineOpCode Opcode) const { 252 return get(Opcode).Flags & M_VARIABLE_OPS; 253 } 254 255 /// getOperandConstraint - Returns the value of the specific constraint if 256 /// it is set. Returns -1 if it is not set. 257 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 258 TOI::OperandConstraint Constraint) const { 259 return get(Opcode).getOperandConstraint(OpNum, Constraint); 260 } 261 262 /// Return true if the instruction is a register to register move 263 /// and leave the source and dest operands in the passed parameters. 264 virtual bool isMoveInstr(const MachineInstr& MI, 265 unsigned& sourceReg, 266 unsigned& destReg) const { 267 return false; 268 } 269 270 /// isLoadFromStackSlot - If the specified machine instruction is a direct 271 /// load from a stack slot, return the virtual or physical register number of 272 /// the destination along with the FrameIndex of the loaded stack slot. If 273 /// not, return 0. This predicate must return 0 if the instruction has 274 /// any side effects other than loading from the stack slot. 275 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 276 return 0; 277 } 278 279 /// isStoreToStackSlot - If the specified machine instruction is a direct 280 /// store to a stack slot, return the virtual or physical register number of 281 /// the source reg along with the FrameIndex of the loaded stack slot. If 282 /// not, return 0. This predicate must return 0 if the instruction has 283 /// any side effects other than storing to the stack slot. 284 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 285 return 0; 286 } 287 288 /// convertToThreeAddress - This method must be implemented by targets that 289 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 290 /// may be able to convert a two-address instruction into one or moretrue 291 /// three-address instructions on demand. This allows the X86 target (for 292 /// example) to convert ADD and SHL instructions into LEA instructions if they 293 /// would require register copies due to two-addressness. 294 /// 295 /// This method returns a null pointer if the transformation cannot be 296 /// performed, otherwise it returns the last new instruction. 297 /// 298 virtual MachineInstr * 299 convertToThreeAddress(MachineFunction::iterator &MFI, 300 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 301 return 0; 302 } 303 304 /// commuteInstruction - If a target has any instructions that are commutable, 305 /// but require converting to a different instruction or making non-trivial 306 /// changes to commute them, this method can overloaded to do this. The 307 /// default implementation of this method simply swaps the first two operands 308 /// of MI and returns it. 309 /// 310 /// If a target wants to make more aggressive changes, they can construct and 311 /// return a new machine instruction. If an instruction cannot commute, it 312 /// can also return null. 313 /// 314 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 315 316 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 317 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 318 /// implemented for a target). Upon success, this returns false and returns 319 /// with the following information in various cases: 320 /// 321 /// 1. If this block ends with no branches (it just falls through to its succ) 322 /// just return false, leaving TBB/FBB null. 323 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 324 /// the destination block. 325 /// 3. If this block ends with an conditional branch, it returns the 'true' 326 /// destination in TBB, the 'false' destination in FBB, and a list of 327 /// operands that evaluate the condition. These operands can be passed to 328 /// other TargetInstrInfo methods to create new branches. 329 /// 330 /// Note that RemoveBranch and InsertBranch must be implemented to support 331 /// cases where this method returns success. 332 /// 333 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 334 MachineBasicBlock *&FBB, 335 std::vector<MachineOperand> &Cond) const { 336 return true; 337 } 338 339 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 340 /// this is only invoked in cases where AnalyzeBranch returns success. 341 virtual void RemoveBranch(MachineBasicBlock &MBB) const { 342 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 343 } 344 345 /// InsertBranch - Insert a branch into the end of the specified 346 /// MachineBasicBlock. This operands to this method are the same as those 347 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 348 /// returns success and when an unconditional branch (TBB is non-null, FBB is 349 /// null, Cond is empty) needs to be inserted. 350 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 351 MachineBasicBlock *FBB, 352 const std::vector<MachineOperand> &Cond) const { 353 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 354 } 355 356 /// BlockHasNoFallThrough - Return true if the specified block does not 357 /// fall-through into its successor block. This is primarily used when a 358 /// branch is unanalyzable. It is useful for things like unconditional 359 /// indirect branches (jump tables). 360 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 361 return false; 362 } 363 364 /// ReverseBranchCondition - Reverses the branch condition of the specified 365 /// condition list, returning false on success and true if it cannot be 366 /// reversed. 367 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 368 return true; 369 } 370 371 /// insertNoop - Insert a noop into the instruction stream at the specified 372 /// point. 373 virtual void insertNoop(MachineBasicBlock &MBB, 374 MachineBasicBlock::iterator MI) const { 375 assert(0 && "Target didn't implement insertNoop!"); 376 abort(); 377 } 378 379 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 380 /// values. 381 virtual const TargetRegisterClass *getPointerRegClass() const { 382 assert(0 && "Target didn't implement getPointerRegClass!"); 383 abort(); 384 return 0; // Must return a value in order to compile with VS 2005 385 } 386}; 387 388} // End llvm namespace 389 390#endif 391