TargetInstrInfo.h revision 349c4952009525b27383e2120a6b3c998f39bd09
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class MachineInstr; 26class TargetMachine; 27class TargetRegisterClass; 28class LiveVariables; 29class CalleeSavedInfo; 30class SDNode; 31class SelectionDAG; 32 33template<class T> class SmallVectorImpl; 34 35//===----------------------------------------------------------------------===// 36// struct TargetInstrDescriptor: 37// Predefined information about each machine instruction. 38// Designed to initialized statically. 39// 40 41const unsigned M_BRANCH_FLAG = 1 << 0; 42const unsigned M_CALL_FLAG = 1 << 1; 43const unsigned M_RET_FLAG = 1 << 2; 44const unsigned M_BARRIER_FLAG = 1 << 3; 45const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 46 47/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads 48/// from memory. This should only be set on instructions that load a value from 49/// memory and return it in their only virtual register definition. 50const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5; 51 52/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly 53/// modify memory. Instructions with this flag set are not necessarily simple 54/// store instructions, they may store a modified value based on their operands, 55/// or may not actually modify anything, for example. 56const unsigned M_MAY_STORE_FLAG = 1 << 6; 57 58const unsigned M_INDIRECT_FLAG = 1 << 7; 59const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8; 60 61// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 62// changed into a 3-address instruction if the first two operands cannot be 63// assigned to the same register. The target must implement the 64// TargetInstrInfo::convertToThreeAddress method for this instruction. 65const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9; 66 67// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 68// Z), which produces the same result if Y and Z are exchanged. 69const unsigned M_COMMUTABLE = 1 << 10; 70 71// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 72// block? Typically this is things like return and branch instructions. 73// Various passes use this to insert code into the bottom of a basic block, but 74// before control flow occurs. 75const unsigned M_TERMINATOR_FLAG = 1 << 11; 76 77// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 78// insertion support when the DAG scheduler is inserting it into a machine basic 79// block. 80const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12; 81 82// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 83// operands in addition to the minimum number operands specified. 84const unsigned M_VARIABLE_OPS = 1 << 13; 85 86// M_PREDICABLE - Set if this instruction has a predicate operand that 87// controls execution. It may be set to 'always'. 88const unsigned M_PREDICABLE = 1 << 14; 89 90// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 91// at any time, e.g. constant generation, load from constant pool. 92const unsigned M_REMATERIALIZIBLE = 1 << 15; 93 94// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. 95// (e.g. instructions with unique labels attached). 96const unsigned M_NOT_DUPLICABLE = 1 << 16; 97 98// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g. 99// ARM instructions which can set condition code if 's' bit is set. 100const unsigned M_HAS_OPTIONAL_DEF = 1 << 17; 101 102// M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that 103// are not captured by any operands of the instruction or other flags, and when 104// *all* instances of the instruction of that opcode have no side effects. 105// 106// Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set 107// both! If neither flag is set, then the instruction *always* has side effects. 108const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18; 109 110// M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have 111// side effects. The virtual method "isReallySideEffectFree" is called to 112// determine this. Load instructions are an example of where this is useful. In 113// general, loads always have side effects. However, loads from constant pools 114// don't. We let the specific back end make this determination. 115// 116// Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set 117// both! If neither flag is set, then the instruction *always* has side effects. 118const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19; 119 120 121//===----------------------------------------------------------------------===// 122// Machine operand flags 123//===----------------------------------------------------------------------===// 124 125namespace TOI { 126 // Operand constraints: only "tied_to" for now. 127 enum OperandConstraint { 128 TIED_TO = 0 // Must be allocated the same register as. 129 }; 130 131 /// OperandFlags - These are flags set on operands, but should be considered 132 /// private, all access should go through the TargetOperandInfo accessors. 133 /// See the accessors for a description of what these are. 134 enum OperandFlags { 135 LookupPtrRegClass = 1 << 0, 136 Predicate = 1 << 1, 137 OptionalDef = 1 << 2 138 }; 139} 140 141/// TargetOperandInfo - This holds information about one operand of a machine 142/// instruction, indicating the register class for register operands, etc. 143/// 144class TargetOperandInfo { 145public: 146 /// RegClass - This specifies the register class enumeration of the operand 147 /// if the operand is a register. If not, this contains 0. 148 unsigned short RegClass; 149 unsigned short Flags; 150 /// Lower 16 bits are used to specify which constraints are set. The higher 16 151 /// bits are used to specify the value of constraints (4 bits each). 152 unsigned int Constraints; 153 /// Currently no other information. 154 155 /// isLookupPtrRegClass - Set if this operand is a pointer value and it 156 /// requires a callback to look up its register class. 157 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; } 158 159 /// isPredicate - Set if this is one of the operands that made up of 160 /// the predicate operand that controls an M_PREDICATED instruction. 161 bool isPredicate() const { return Flags & TOI::Predicate; } 162 163 /// isOptionalDef - Set if this operand is a optional def. 164 /// 165 bool isOptionalDef() const { return Flags & TOI::OptionalDef; } 166}; 167 168 169class TargetInstrDescriptor { 170public: 171 unsigned short Opcode; // The opcode. 172 unsigned short NumOperands; // Num of args (may be more if variable_ops). 173 unsigned short NumDefs; // Num of args that are definitions. 174 const char * Name; // Assembly language mnemonic for the opcode. 175 unsigned SchedClass; // enum identifying instr sched class 176 unsigned Flags; // flags identifying machine instr class 177 unsigned TSFlags; // Target Specific Flag values 178 const unsigned *ImplicitUses; // Registers implicitly read by this instr 179 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 180 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 181 182 /// getOperandConstraint - Returns the value of the specific constraint if 183 /// it is set. Returns -1 if it is not set. 184 int getOperandConstraint(unsigned OpNum, 185 TOI::OperandConstraint Constraint) const { 186 assert((OpNum < NumOperands || hasVariableOperands()) && 187 "Invalid operand # of TargetInstrInfo"); 188 if (OpNum < NumOperands && 189 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 190 unsigned Pos = 16 + Constraint * 4; 191 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 192 } 193 return -1; 194 } 195 196 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 197 /// dest operand. Returns -1 if there isn't one. 198 int findTiedToSrcOperand(unsigned OpNum) const; 199 200 const char *getName() const { 201 return Name; 202 } 203 204 unsigned getNumOperands() const { 205 return NumOperands; 206 } 207 208 unsigned getNumDefs() const { 209 return NumDefs; 210 } 211 212 bool hasVariableOperands() const { 213 return Flags & M_VARIABLE_OPS; 214 } 215 216 bool hasOptionalDef() const { 217 return Flags & M_HAS_OPTIONAL_DEF; 218 } 219 220 const unsigned *getImplicitUses() const { 221 return ImplicitUses; 222 } 223 224 const unsigned *getImplicitDefs() const { 225 return ImplicitDefs; 226 } 227 228 bool isReturn() const { 229 return Flags & M_RET_FLAG; 230 } 231 232 bool isCall() const { 233 return Flags & M_CALL_FLAG; 234 } 235 236 bool isTerminator() const { 237 return Flags & M_TERMINATOR_FLAG; 238 } 239 240 bool isBranch() const { 241 return Flags & M_BRANCH_FLAG; 242 } 243 244 bool isIndirectBranch() const { 245 return Flags & M_INDIRECT_FLAG; 246 } 247 248 bool isPredicable() const { 249 return Flags & M_PREDICABLE; 250 } 251 252 bool isNotDuplicable() const { 253 return Flags & M_NOT_DUPLICABLE; 254 } 255 256 bool isCommutableInstr() const { 257 return Flags & M_COMMUTABLE; 258 } 259 260 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 261 /// custom insertion support when the DAG scheduler is inserting it into a 262 /// machine basic block. 263 bool usesCustomDAGSchedInsertionHook() const { 264 return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 265 } 266 267 /// isSimpleLoad - Return true for instructions that are simple loads from 268 /// memory. This should only be set on instructions that load a value from 269 /// memory and return it in their only virtual register definition. 270 /// Instructions that return a value loaded from memory and then modified in 271 /// some way should not return true for this. 272 bool isSimpleLoad() const { 273 return Flags & M_SIMPLE_LOAD_FLAG; 274 } 275 276 /// mayStore - Return true if this instruction could possibly modify memory. 277 /// Instructions with this flag set are not necessarily simple store 278 /// instructions, they may store a modified value based on their operands, or 279 /// may not actually modify anything, for example. 280 bool mayStore() const { 281 return Flags & M_MAY_STORE_FLAG; 282 } 283 284 /// isBarrier - Returns true if the specified instruction stops control flow 285 /// from executing the instruction immediately following it. Examples include 286 /// unconditional branches and return instructions. 287 bool isBarrier() const { 288 return Flags & M_BARRIER_FLAG; 289 } 290 291 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 292 /// which must be filled by the code generator. 293 bool hasDelaySlot() const { 294 return Flags & M_DELAY_SLOT_FLAG; 295 } 296 297 unsigned getSchedClass() const { 298 return SchedClass; 299 } 300}; 301 302 303//--------------------------------------------------------------------------- 304/// 305/// TargetInstrInfo - Interface to description of machine instructions 306/// 307class TargetInstrInfo { 308 const TargetInstrDescriptor* desc; // raw array to allow static init'n 309 unsigned NumOpcodes; // number of entries in the desc array 310 unsigned numRealOpCodes; // number of non-dummy op codes 311 312 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 313 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 314public: 315 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 316 virtual ~TargetInstrInfo(); 317 318 // Invariant opcodes: All instruction sets have these as their low opcodes. 319 enum { 320 PHI = 0, 321 INLINEASM = 1, 322 LABEL = 2, 323 EXTRACT_SUBREG = 3, 324 INSERT_SUBREG = 4 325 }; 326 327 unsigned getNumOpcodes() const { return NumOpcodes; } 328 329 /// get - Return the machine instruction descriptor that corresponds to the 330 /// specified instruction opcode. 331 /// 332 const TargetInstrDescriptor& get(unsigned Opcode) const { 333 assert(Opcode < NumOpcodes); 334 return desc[Opcode]; 335 } 336 337 /// isTriviallyReMaterializable - Return true if the instruction is trivially 338 /// rematerializable, meaning it has no side effects and requires no operands 339 /// that aren't always available. 340 bool isTriviallyReMaterializable(MachineInstr *MI) const { 341 return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) && 342 isReallyTriviallyReMaterializable(MI); 343 } 344 345 /// hasUnmodelledSideEffects - Returns true if the instruction has side 346 /// effects that are not captured by any operands of the instruction or other 347 /// flags. 348 bool hasUnmodelledSideEffects(MachineInstr *MI) const { 349 const TargetInstrDescriptor *TID = MI->getDesc(); 350 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false; 351 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true; 352 return !isReallySideEffectFree(MI); // May have side effects 353 } 354protected: 355 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 356 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 357 /// instruction itself is actually trivially rematerializable, considering 358 /// its operands. This is used for targets that have instructions that are 359 /// only trivially rematerializable for specific uses. This predicate must 360 /// return false if the instruction has any side effects other than 361 /// producing a value, or if it requres any address registers that are not 362 /// always available. 363 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 364 return true; 365 } 366 367 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this 368 /// method is called to determine if the specific instance of this 369 /// instruction has side effects. This is useful in cases of instructions, 370 /// like loads, which generally always have side effects. A load from a 371 /// constant pool doesn't have side effects, though. So we need to 372 /// differentiate it from the general case. 373 virtual bool isReallySideEffectFree(MachineInstr *MI) const { 374 return false; 375 } 376public: 377 /// getOperandConstraint - Returns the value of the specific constraint if 378 /// it is set. Returns -1 if it is not set. 379 int getOperandConstraint(unsigned Opcode, unsigned OpNum, 380 TOI::OperandConstraint Constraint) const { 381 return get(Opcode).getOperandConstraint(OpNum, Constraint); 382 } 383 384 /// Return true if the instruction is a register to register move 385 /// and leave the source and dest operands in the passed parameters. 386 virtual bool isMoveInstr(const MachineInstr& MI, 387 unsigned& sourceReg, 388 unsigned& destReg) const { 389 return false; 390 } 391 392 /// isLoadFromStackSlot - If the specified machine instruction is a direct 393 /// load from a stack slot, return the virtual or physical register number of 394 /// the destination along with the FrameIndex of the loaded stack slot. If 395 /// not, return 0. This predicate must return 0 if the instruction has 396 /// any side effects other than loading from the stack slot. 397 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 398 return 0; 399 } 400 401 /// isStoreToStackSlot - If the specified machine instruction is a direct 402 /// store to a stack slot, return the virtual or physical register number of 403 /// the source reg along with the FrameIndex of the loaded stack slot. If 404 /// not, return 0. This predicate must return 0 if the instruction has 405 /// any side effects other than storing to the stack slot. 406 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 407 return 0; 408 } 409 410 /// convertToThreeAddress - This method must be implemented by targets that 411 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 412 /// may be able to convert a two-address instruction into one or more true 413 /// three-address instructions on demand. This allows the X86 target (for 414 /// example) to convert ADD and SHL instructions into LEA instructions if they 415 /// would require register copies due to two-addressness. 416 /// 417 /// This method returns a null pointer if the transformation cannot be 418 /// performed, otherwise it returns the last new instruction. 419 /// 420 virtual MachineInstr * 421 convertToThreeAddress(MachineFunction::iterator &MFI, 422 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 423 return 0; 424 } 425 426 /// commuteInstruction - If a target has any instructions that are commutable, 427 /// but require converting to a different instruction or making non-trivial 428 /// changes to commute them, this method can overloaded to do this. The 429 /// default implementation of this method simply swaps the first two operands 430 /// of MI and returns it. 431 /// 432 /// If a target wants to make more aggressive changes, they can construct and 433 /// return a new machine instruction. If an instruction cannot commute, it 434 /// can also return null. 435 /// 436 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; 437 438 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 439 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 440 /// implemented for a target). Upon success, this returns false and returns 441 /// with the following information in various cases: 442 /// 443 /// 1. If this block ends with no branches (it just falls through to its succ) 444 /// just return false, leaving TBB/FBB null. 445 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 446 /// the destination block. 447 /// 3. If this block ends with an conditional branch and it falls through to 448 /// an successor block, it sets TBB to be the branch destination block and a 449 /// list of operands that evaluate the condition. These 450 /// operands can be passed to other TargetInstrInfo methods to create new 451 /// branches. 452 /// 4. If this block ends with an conditional branch and an unconditional 453 /// block, it returns the 'true' destination in TBB, the 'false' destination 454 /// in FBB, and a list of operands that evaluate the condition. These 455 /// operands can be passed to other TargetInstrInfo methods to create new 456 /// branches. 457 /// 458 /// Note that RemoveBranch and InsertBranch must be implemented to support 459 /// cases where this method returns success. 460 /// 461 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 462 MachineBasicBlock *&FBB, 463 std::vector<MachineOperand> &Cond) const { 464 return true; 465 } 466 467 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 468 /// this is only invoked in cases where AnalyzeBranch returns success. It 469 /// returns the number of instructions that were removed. 470 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 471 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 472 return 0; 473 } 474 475 /// InsertBranch - Insert a branch into the end of the specified 476 /// MachineBasicBlock. This operands to this method are the same as those 477 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 478 /// returns success and when an unconditional branch (TBB is non-null, FBB is 479 /// null, Cond is empty) needs to be inserted. It returns the number of 480 /// instructions inserted. 481 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 482 MachineBasicBlock *FBB, 483 const std::vector<MachineOperand> &Cond) const { 484 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 485 return 0; 486 } 487 488 /// copyRegToReg - Add a copy between a pair of registers 489 virtual void copyRegToReg(MachineBasicBlock &MBB, 490 MachineBasicBlock::iterator MI, 491 unsigned DestReg, unsigned SrcReg, 492 const TargetRegisterClass *DestRC, 493 const TargetRegisterClass *SrcRC) const { 494 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 495 } 496 497 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 498 MachineBasicBlock::iterator MI, 499 unsigned SrcReg, bool isKill, int FrameIndex, 500 const TargetRegisterClass *RC) const { 501 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 502 } 503 504 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 505 SmallVectorImpl<MachineOperand> &Addr, 506 const TargetRegisterClass *RC, 507 SmallVectorImpl<MachineInstr*> &NewMIs) const { 508 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 509 } 510 511 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 512 MachineBasicBlock::iterator MI, 513 unsigned DestReg, int FrameIndex, 514 const TargetRegisterClass *RC) const { 515 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 516 } 517 518 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 519 SmallVectorImpl<MachineOperand> &Addr, 520 const TargetRegisterClass *RC, 521 SmallVectorImpl<MachineInstr*> &NewMIs) const { 522 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 523 } 524 525 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 526 /// saved registers and returns true if it isn't possible / profitable to do 527 /// so by issuing a series of store instructions via 528 /// storeRegToStackSlot(). Returns false otherwise. 529 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 530 MachineBasicBlock::iterator MI, 531 const std::vector<CalleeSavedInfo> &CSI) const { 532 return false; 533 } 534 535 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 536 /// saved registers and returns true if it isn't possible / profitable to do 537 /// so by issuing a series of load instructions via loadRegToStackSlot(). 538 /// Returns false otherwise. 539 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 540 MachineBasicBlock::iterator MI, 541 const std::vector<CalleeSavedInfo> &CSI) const { 542 return false; 543 } 544 545 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 546 /// slot into the specified machine instruction for the specified operand(s). 547 /// If this is possible, a new instruction is returned with the specified 548 /// operand folded, otherwise NULL is returned. The client is responsible for 549 /// removing the old instruction and adding the new one in the instruction 550 /// stream. 551 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 552 SmallVectorImpl<unsigned> &Ops, 553 int FrameIndex) const { 554 return 0; 555 } 556 557 /// foldMemoryOperand - Same as the previous version except it allows folding 558 /// of any load and store from / to any address, not just from a specific 559 /// stack slot. 560 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 561 SmallVectorImpl<unsigned> &Ops, 562 MachineInstr* LoadMI) const { 563 return 0; 564 } 565 566 /// canFoldMemoryOperand - Returns true if the specified load / store is 567 /// folding is possible. 568 virtual 569 bool canFoldMemoryOperand(MachineInstr *MI, 570 SmallVectorImpl<unsigned> &Ops) const{ 571 return false; 572 } 573 574 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 575 /// a store or a load and a store into two or more instruction. If this is 576 /// possible, returns true as well as the new instructions by reference. 577 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 578 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 579 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 580 return false; 581 } 582 583 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 584 SmallVectorImpl<SDNode*> &NewNodes) const { 585 return false; 586 } 587 588 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 589 /// instruction after load / store are unfolded from an instruction of the 590 /// specified opcode. It returns zero if the specified unfolding is not 591 /// possible. 592 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 593 bool UnfoldLoad, bool UnfoldStore) const { 594 return 0; 595 } 596 597 /// BlockHasNoFallThrough - Return true if the specified block does not 598 /// fall-through into its successor block. This is primarily used when a 599 /// branch is unanalyzable. It is useful for things like unconditional 600 /// indirect branches (jump tables). 601 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 602 return false; 603 } 604 605 /// ReverseBranchCondition - Reverses the branch condition of the specified 606 /// condition list, returning false on success and true if it cannot be 607 /// reversed. 608 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 609 return true; 610 } 611 612 /// insertNoop - Insert a noop into the instruction stream at the specified 613 /// point. 614 virtual void insertNoop(MachineBasicBlock &MBB, 615 MachineBasicBlock::iterator MI) const { 616 assert(0 && "Target didn't implement insertNoop!"); 617 abort(); 618 } 619 620 /// isPredicated - Returns true if the instruction is already predicated. 621 /// 622 virtual bool isPredicated(const MachineInstr *MI) const { 623 return false; 624 } 625 626 /// isUnpredicatedTerminator - Returns true if the instruction is a 627 /// terminator instruction that has not been predicated. 628 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 629 630 /// PredicateInstruction - Convert the instruction into a predicated 631 /// instruction. It returns true if the operation was successful. 632 virtual 633 bool PredicateInstruction(MachineInstr *MI, 634 const std::vector<MachineOperand> &Pred) const = 0; 635 636 /// SubsumesPredicate - Returns true if the first specified predicate 637 /// subsumes the second, e.g. GE subsumes GT. 638 virtual 639 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 640 const std::vector<MachineOperand> &Pred2) const { 641 return false; 642 } 643 644 /// DefinesPredicate - If the specified instruction defines any predicate 645 /// or condition code register(s) used for predication, returns true as well 646 /// as the definition predicate(s) by reference. 647 virtual bool DefinesPredicate(MachineInstr *MI, 648 std::vector<MachineOperand> &Pred) const { 649 return false; 650 } 651 652 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 653 /// values. 654 virtual const TargetRegisterClass *getPointerRegClass() const { 655 assert(0 && "Target didn't implement getPointerRegClass!"); 656 abort(); 657 return 0; // Must return a value in order to compile with VS 2005 658 } 659}; 660 661/// TargetInstrInfoImpl - This is the default implementation of 662/// TargetInstrInfo, which just provides a couple of default implementations 663/// for various methods. This separated out because it is implemented in 664/// libcodegen, not in libtarget. 665class TargetInstrInfoImpl : public TargetInstrInfo { 666protected: 667 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes) 668 : TargetInstrInfo(desc, NumOpcodes) {} 669public: 670 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 671 virtual bool PredicateInstruction(MachineInstr *MI, 672 const std::vector<MachineOperand> &Pred) const; 673 674}; 675 676} // End llvm namespace 677 678#endif 679