TargetInstrInfo.h revision 75e961ae6b2e2801160e560057ad97ece4443986
1//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===---------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "Support/DataTypes.h" 11#include <vector> 12 13class MachineInstrDescriptor; 14class MachineInstr; 15class TargetMachine; 16class Value; 17class Instruction; 18class Constant; 19class Function; 20class MachineCodeForInstruction; 21 22//--------------------------------------------------------------------------- 23// Data types used to define information about a single machine instruction 24//--------------------------------------------------------------------------- 25 26typedef int MachineOpCode; 27typedef unsigned InstrSchedClass; 28 29const MachineOpCode INVALID_MACHINE_OPCODE = -1; 30 31 32//--------------------------------------------------------------------------- 33// struct MachineInstrDescriptor: 34// Predefined information about each machine instruction. 35// Designed to initialized statically. 36// 37// class MachineInstructionInfo 38// Interface to description of machine instructions 39// 40//--------------------------------------------------------------------------- 41 42const unsigned M_NOP_FLAG = 1 << 0; 43const unsigned M_BRANCH_FLAG = 1 << 1; 44const unsigned M_CALL_FLAG = 1 << 2; 45const unsigned M_RET_FLAG = 1 << 3; 46const unsigned M_ARITH_FLAG = 1 << 4; 47const unsigned M_CC_FLAG = 1 << 6; 48const unsigned M_LOGICAL_FLAG = 1 << 6; 49const unsigned M_INT_FLAG = 1 << 7; 50const unsigned M_FLOAT_FLAG = 1 << 8; 51const unsigned M_CONDL_FLAG = 1 << 9; 52const unsigned M_LOAD_FLAG = 1 << 10; 53const unsigned M_PREFETCH_FLAG = 1 << 11; 54const unsigned M_STORE_FLAG = 1 << 12; 55const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 56const unsigned M_PSEUDO_FLAG = 1 << 14; 57 58 59struct MachineInstrDescriptor { 60 const char * Name; // Assembly language mnemonic for the opcode. 61 int numOperands; // Number of args; -1 if variable #args 62 int resultPos; // Position of the result; -1 if no result 63 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 64 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 65 // smallest -ve value is -(maxImmedConst+1). 66 unsigned numDelaySlots; // Number of delay slots after instruction 67 unsigned latency; // Latency in machine cycles 68 InstrSchedClass schedClass; // enum identifying instr sched class 69 unsigned Flags; // flags identifying machine instr class 70 unsigned TSFlags; // Target Specific Flag values 71}; 72 73 74class MachineInstrInfo { 75 const MachineInstrDescriptor* desc; // raw array to allow static init'n 76 unsigned descSize; // number of entries in the desc array 77 unsigned numRealOpCodes; // number of non-dummy op codes 78 79 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT 80 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT 81public: 82 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize, 83 unsigned numRealOpCodes); 84 virtual ~MachineInstrInfo(); 85 86 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 87 unsigned getNumTotalOpCodes() const { return descSize; } 88 89 /// get - Return the machine instruction descriptor that corresponds to the 90 /// specified instruction opcode. 91 /// 92 const MachineInstrDescriptor& get(MachineOpCode opCode) const { 93 assert(opCode >= 0 && opCode < (int)descSize); 94 return desc[opCode]; 95 } 96 97 const char *getName(MachineOpCode opCode) const { 98 return get(opCode).Name; 99 } 100 101 int getNumOperands(MachineOpCode opCode) const { 102 return get(opCode).numOperands; 103 } 104 105 int getResultPos(MachineOpCode opCode) const { 106 return get(opCode).resultPos; 107 } 108 109 unsigned getNumDelaySlots(MachineOpCode opCode) const { 110 return get(opCode).numDelaySlots; 111 } 112 113 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 114 return get(opCode).schedClass; 115 } 116 117 // 118 // Query instruction class flags according to the machine-independent 119 // flags listed above. 120 // 121 bool isNop(MachineOpCode opCode) const { 122 return get(opCode).Flags & M_NOP_FLAG; 123 } 124 bool isBranch(MachineOpCode opCode) const { 125 return get(opCode).Flags & M_BRANCH_FLAG; 126 } 127 bool isCall(MachineOpCode opCode) const { 128 return get(opCode).Flags & M_CALL_FLAG; 129 } 130 bool isReturn(MachineOpCode opCode) const { 131 return get(opCode).Flags & M_RET_FLAG; 132 } 133 bool isControlFlow(MachineOpCode opCode) const { 134 return get(opCode).Flags & M_BRANCH_FLAG 135 || get(opCode).Flags & M_CALL_FLAG 136 || get(opCode).Flags & M_RET_FLAG; 137 } 138 bool isArith(MachineOpCode opCode) const { 139 return get(opCode).Flags & M_ARITH_FLAG; 140 } 141 bool isCCInstr(MachineOpCode opCode) const { 142 return get(opCode).Flags & M_CC_FLAG; 143 } 144 bool isLogical(MachineOpCode opCode) const { 145 return get(opCode).Flags & M_LOGICAL_FLAG; 146 } 147 bool isIntInstr(MachineOpCode opCode) const { 148 return get(opCode).Flags & M_INT_FLAG; 149 } 150 bool isFloatInstr(MachineOpCode opCode) const { 151 return get(opCode).Flags & M_FLOAT_FLAG; 152 } 153 bool isConditional(MachineOpCode opCode) const { 154 return get(opCode).Flags & M_CONDL_FLAG; 155 } 156 bool isLoad(MachineOpCode opCode) const { 157 return get(opCode).Flags & M_LOAD_FLAG; 158 } 159 bool isPrefetch(MachineOpCode opCode) const { 160 return get(opCode).Flags & M_PREFETCH_FLAG; 161 } 162 bool isLoadOrPrefetch(MachineOpCode opCode) const { 163 return get(opCode).Flags & M_LOAD_FLAG 164 || get(opCode).Flags & M_PREFETCH_FLAG; 165 } 166 bool isStore(MachineOpCode opCode) const { 167 return get(opCode).Flags & M_STORE_FLAG; 168 } 169 bool isMemoryAccess(MachineOpCode opCode) const { 170 return get(opCode).Flags & M_LOAD_FLAG 171 || get(opCode).Flags & M_PREFETCH_FLAG 172 || get(opCode).Flags & M_STORE_FLAG; 173 } 174 bool isDummyPhiInstr(const MachineOpCode opCode) const { 175 return get(opCode).Flags & M_DUMMY_PHI_FLAG; 176 } 177 bool isPseudoInstr(const MachineOpCode opCode) const { 178 return get(opCode).Flags & M_PSEUDO_FLAG; 179 } 180 181 // Check if an instruction can be issued before its operands are ready, 182 // or if a subsequent instruction that uses its result can be issued 183 // before the results are ready. 184 // Default to true since most instructions on many architectures allow this. 185 // 186 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 187 return true; 188 } 189 190 virtual bool hasResultInterlock(MachineOpCode opCode) const { 191 return true; 192 } 193 194 // 195 // Latencies for individual instructions and instruction pairs 196 // 197 virtual int minLatency(MachineOpCode opCode) const { 198 return get(opCode).latency; 199 } 200 201 virtual int maxLatency(MachineOpCode opCode) const { 202 return get(opCode).latency; 203 } 204 205 // 206 // Which operand holds an immediate constant? Returns -1 if none 207 // 208 virtual int getImmedConstantPos(MachineOpCode opCode) const { 209 return -1; // immediate position is machine specific, so say -1 == "none" 210 } 211 212 // Check if the specified constant fits in the immediate field 213 // of this machine instruction 214 // 215 virtual bool constantFitsInImmedField(MachineOpCode opCode, 216 int64_t intValue) const; 217 218 // Return the largest +ve constant that can be held in the IMMMED field 219 // of this machine instruction. 220 // isSignExtended is set to true if the value is sign-extended before use 221 // (this is true for all immediate fields in SPARC instructions). 222 // Return 0 if the instruction has no IMMED field. 223 // 224 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 225 bool &isSignExtended) const { 226 isSignExtended = get(opCode).immedIsSignExtended; 227 return get(opCode).maxImmedConst; 228 } 229 230 //------------------------------------------------------------------------- 231 // Queries about representation of LLVM quantities (e.g., constants) 232 //------------------------------------------------------------------------- 233 234 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 235 /// from memory into a register, i.e., cannot be set bitwise in register and 236 /// cannot use immediate fields of instructions. Note that this only makes 237 /// sense for primitive types. 238 /// 239 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 240 241 // Test if this constant may not fit in the immediate field of the 242 // machine instructions (probably) generated for this instruction. 243 // 244 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 245 const Instruction* I) const { 246 return true; // safe but very conservative 247 } 248 249 //------------------------------------------------------------------------- 250 // Code generation support for creating individual machine instructions 251 //------------------------------------------------------------------------- 252 253 // Get certain common op codes for the current target. this and all the 254 // Create* methods below should be moved to a machine code generation class 255 // 256 virtual MachineOpCode getNOPOpCode() const = 0; 257 258 // Create an instruction sequence to put the constant `val' into 259 // the virtual register `dest'. `val' may be a Constant or a 260 // GlobalValue, viz., the constant address of a global variable or function. 261 // The generated instructions are returned in `mvec'. 262 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 263 // Symbolic constants or constants that must be accessed from memory 264 // are added to the constant pool via MachineFunction::get(F). 265 // 266 virtual void CreateCodeToLoadConst(const TargetMachine& target, 267 Function* F, 268 Value* val, 269 Instruction* dest, 270 std::vector<MachineInstr*>& mvec, 271 MachineCodeForInstruction& mcfi) const=0; 272 273 // Create an instruction sequence to copy an integer value `val' 274 // to a floating point value `dest' by copying to memory and back. 275 // val must be an integral type. dest must be a Float or Double. 276 // The generated instructions are returned in `mvec'. 277 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 278 // Any stack space required is allocated via mcff. 279 // 280 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 281 Function* F, 282 Value* val, 283 Instruction* dest, 284 std::vector<MachineInstr*>& mvec, 285 MachineCodeForInstruction& mcfi)const=0; 286 287 // Similarly, create an instruction sequence to copy an FP value 288 // `val' to an integer value `dest' by copying to memory and back. 289 // The generated instructions are returned in `mvec'. 290 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 291 // Any stack space required is allocated via mcff. 292 // 293 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 294 Function* F, 295 Value* val, 296 Instruction* dest, 297 std::vector<MachineInstr*>& mvec, 298 MachineCodeForInstruction& mcfi)const=0; 299 300 // Create instruction(s) to copy src to dest, for arbitrary types 301 // The generated instructions are returned in `mvec'. 302 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 303 // Any stack space required is allocated via mcff. 304 // 305 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 306 Function* F, 307 Value* src, 308 Instruction* dest, 309 std::vector<MachineInstr*>& mvec, 310 MachineCodeForInstruction& mcfi)const=0; 311 312 // Create instruction sequence to produce a sign-extended register value 313 // from an arbitrary sized value (sized in bits, not bytes). 314 // The generated instructions are appended to `mvec'. 315 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 316 // Any stack space required is allocated via mcff. 317 // 318 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 319 Function* F, 320 Value* srcVal, 321 Value* destVal, 322 unsigned numLowBits, 323 std::vector<MachineInstr*>& mvec, 324 MachineCodeForInstruction& mcfi) const=0; 325 326 // Create instruction sequence to produce a zero-extended register value 327 // from an arbitrary sized value (sized in bits, not bytes). 328 // The generated instructions are appended to `mvec'. 329 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 330 // Any stack space required is allocated via mcff. 331 // 332 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 333 Function* F, 334 Value* srcVal, 335 Value* destVal, 336 unsigned srcSizeInBits, 337 std::vector<MachineInstr*>& mvec, 338 MachineCodeForInstruction& mcfi) const=0; 339}; 340 341#endif 342