TargetInstrInfo.h revision 8d3af5e7d082dbd029c3987ceadbdcf9e49af6d7
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32class TargetRegisterClass; 33 34//--------------------------------------------------------------------------- 35// Data types used to define information about a single machine instruction 36//--------------------------------------------------------------------------- 37 38typedef short MachineOpCode; 39typedef unsigned InstrSchedClass; 40 41//--------------------------------------------------------------------------- 42// struct TargetInstrDescriptor: 43// Predefined information about each machine instruction. 44// Designed to initialized statically. 45// 46 47const unsigned M_BRANCH_FLAG = 1 << 0; 48const unsigned M_CALL_FLAG = 1 << 1; 49const unsigned M_RET_FLAG = 1 << 2; 50const unsigned M_BARRIER_FLAG = 1 << 3; 51const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 52const unsigned M_LOAD_FLAG = 1 << 5; 53const unsigned M_STORE_FLAG = 1 << 6; 54 55// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 56const unsigned M_2_ADDR_FLAG = 1 << 7; 57 58// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 59// changed into a 3-address instruction if the first two operands cannot be 60// assigned to the same register. The target must implement the 61// TargetInstrInfo::convertToThreeAddress method for this instruction. 62const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8; 63 64// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 65// Z), which produces the same result if Y and Z are exchanged. 66const unsigned M_COMMUTABLE = 1 << 9; 67 68// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 69// block? Typically this is things like return and branch instructions. 70// Various passes use this to insert code into the bottom of a basic block, but 71// before control flow occurs. 72const unsigned M_TERMINATOR_FLAG = 1 << 10; 73 74// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 75// insertion support when the DAG scheduler is inserting it into a machine basic 76// block. 77const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11; 78 79// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 80// operands in addition to the minimum number operands specified. 81const unsigned M_VARIABLE_OPS = 1 << 12; 82 83// Machine operand flags 84// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 85// requires a callback to look up its register class. 86const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 87 88/// TargetOperandInfo - This holds information about one operand of a machine 89/// instruction, indicating the register class for register operands, etc. 90/// 91class TargetOperandInfo { 92public: 93 /// RegClass - This specifies the register class of the operand if the 94 /// operand is a register. If not, this contains null. 95 const TargetRegisterClass *RegClass; 96 unsigned Flags; 97 /// Currently no other information. 98}; 99 100 101class TargetInstrDescriptor { 102public: 103 const char * Name; // Assembly language mnemonic for the opcode. 104 unsigned numOperands; // Num of args (may be more if variable_ops). 105 InstrSchedClass schedClass; // enum identifying instr sched class 106 unsigned Flags; // flags identifying machine instr class 107 unsigned TSFlags; // Target Specific Flag values 108 const unsigned *ImplicitUses; // Registers implicitly read by this instr 109 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 110 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 111}; 112 113 114//--------------------------------------------------------------------------- 115/// 116/// TargetInstrInfo - Interface to description of machine instructions 117/// 118class TargetInstrInfo { 119 const TargetInstrDescriptor* desc; // raw array to allow static init'n 120 unsigned NumOpcodes; // number of entries in the desc array 121 unsigned numRealOpCodes; // number of non-dummy op codes 122 123 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 124 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 125public: 126 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 127 virtual ~TargetInstrInfo(); 128 129 // Invariant opcodes: All instruction sets have these as their low opcodes. 130 enum { 131 PHI = 0, 132 INLINEASM = 1 133 }; 134 135 unsigned getNumOpcodes() const { return NumOpcodes; } 136 137 /// get - Return the machine instruction descriptor that corresponds to the 138 /// specified instruction opcode. 139 /// 140 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 141 assert((unsigned)Opcode < NumOpcodes); 142 return desc[Opcode]; 143 } 144 145 const char *getName(MachineOpCode Opcode) const { 146 return get(Opcode).Name; 147 } 148 149 const TargetRegisterClass 150 *getInstrOperandRegClass(const TargetInstrDescriptor *II, unsigned Op) const { 151 if (Op >= II->numOperands) { 152 if (II->Flags & M_VARIABLE_OPS) 153 return NULL; 154 assert(false && "Invalid operand # of instruction"); 155 } 156 const TargetOperandInfo &toi = II->OpInfo[Op]; 157 return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS) 158 ? getPointerRegClass() : toi.RegClass; 159 } 160 161 int getNumOperands(MachineOpCode Opcode) const { 162 return get(Opcode).numOperands; 163 } 164 165 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 166 return get(Opcode).schedClass; 167 } 168 169 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 170 return get(Opcode).ImplicitUses; 171 } 172 173 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 174 return get(Opcode).ImplicitDefs; 175 } 176 177 178 // 179 // Query instruction class flags according to the machine-independent 180 // flags listed above. 181 // 182 bool isReturn(MachineOpCode Opcode) const { 183 return get(Opcode).Flags & M_RET_FLAG; 184 } 185 186 bool isTwoAddrInstr(MachineOpCode Opcode) const { 187 return get(Opcode).Flags & M_2_ADDR_FLAG; 188 } 189 bool isCommutableInstr(MachineOpCode Opcode) const { 190 return get(Opcode).Flags & M_COMMUTABLE; 191 } 192 bool isTerminatorInstr(unsigned Opcode) const { 193 return get(Opcode).Flags & M_TERMINATOR_FLAG; 194 } 195 196 bool isBranch(MachineOpCode Opcode) const { 197 return get(Opcode).Flags & M_BRANCH_FLAG; 198 } 199 200 /// isBarrier - Returns true if the specified instruction stops control flow 201 /// from executing the instruction immediately following it. Examples include 202 /// unconditional branches and return instructions. 203 bool isBarrier(MachineOpCode Opcode) const { 204 return get(Opcode).Flags & M_BARRIER_FLAG; 205 } 206 207 bool isCall(MachineOpCode Opcode) const { 208 return get(Opcode).Flags & M_CALL_FLAG; 209 } 210 bool isLoad(MachineOpCode Opcode) const { 211 return get(Opcode).Flags & M_LOAD_FLAG; 212 } 213 bool isStore(MachineOpCode Opcode) const { 214 return get(Opcode).Flags & M_STORE_FLAG; 215 } 216 217 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 218 /// custom insertion support when the DAG scheduler is inserting it into a 219 /// machine basic block. 220 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 221 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 222 } 223 224 bool hasVariableOperands(MachineOpCode Opcode) const { 225 return get(Opcode).Flags & M_VARIABLE_OPS; 226 } 227 228 /// Return true if the instruction is a register to register move 229 /// and leave the source and dest operands in the passed parameters. 230 virtual bool isMoveInstr(const MachineInstr& MI, 231 unsigned& sourceReg, 232 unsigned& destReg) const { 233 return false; 234 } 235 236 /// isLoadFromStackSlot - If the specified machine instruction is a direct 237 /// load from a stack slot, return the virtual or physical register number of 238 /// the destination along with the FrameIndex of the loaded stack slot. If 239 /// not, return 0. This predicate must return 0 if the instruction has 240 /// any side effects other than loading from the stack slot. 241 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 242 return 0; 243 } 244 245 /// isStoreToStackSlot - If the specified machine instruction is a direct 246 /// store to a stack slot, return the virtual or physical register number of 247 /// the source reg along with the FrameIndex of the loaded stack slot. If 248 /// not, return 0. This predicate must return 0 if the instruction has 249 /// any side effects other than storing to the stack slot. 250 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 251 return 0; 252 } 253 254 /// convertToThreeAddress - This method must be implemented by targets that 255 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 256 /// may be able to convert a two-address instruction into a true 257 /// three-address instruction on demand. This allows the X86 target (for 258 /// example) to convert ADD and SHL instructions into LEA instructions if they 259 /// would require register copies due to two-addressness. 260 /// 261 /// This method returns a null pointer if the transformation cannot be 262 /// performed, otherwise it returns the new instruction. 263 /// 264 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 265 return 0; 266 } 267 268 /// commuteInstruction - If a target has any instructions that are commutable, 269 /// but require converting to a different instruction or making non-trivial 270 /// changes to commute them, this method can overloaded to do this. The 271 /// default implementation of this method simply swaps the first two operands 272 /// of MI and returns it. 273 /// 274 /// If a target wants to make more aggressive changes, they can construct and 275 /// return a new machine instruction. If an instruction cannot commute, it 276 /// can also return null. 277 /// 278 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 279 280 /// Insert a goto (unconditional branch) sequence to TMBB, at the 281 /// end of MBB 282 virtual void insertGoto(MachineBasicBlock& MBB, 283 MachineBasicBlock& TMBB) const { 284 assert(0 && "Target didn't implement insertGoto!"); 285 } 286 287 /// Reverses the branch condition of the MachineInstr pointed by 288 /// MI. The instruction is replaced and the new MI is returned. 289 virtual MachineBasicBlock::iterator 290 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 291 assert(0 && "Target didn't implement reverseBranchCondition!"); 292 abort(); 293 return MI; 294 } 295 296 /// insertNoop - Insert a noop into the instruction stream at the specified 297 /// point. 298 virtual void insertNoop(MachineBasicBlock &MBB, 299 MachineBasicBlock::iterator MI) const { 300 assert(0 && "Target didn't implement insertNoop!"); 301 abort(); 302 } 303 304 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 305 /// values. 306 virtual const TargetRegisterClass *getPointerRegClass() const { 307 assert(0 && "Target didn't implement getPointerRegClass!"); 308 abort(); 309 } 310 311 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 312 /// which must be filled by the code generator. 313 bool hasDelaySlot(unsigned Opcode) const { 314 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 315 } 316}; 317 318} // End llvm namespace 319 320#endif 321