TargetInstrInfo.h revision b5cdaa257e167a08a8a54ea9249d847ccc415ce0
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class MachineInstr; 26class TargetMachine; 27class MachineCodeForInstruction; 28class TargetRegisterClass; 29class LiveVariables; 30 31//--------------------------------------------------------------------------- 32// Data types used to define information about a single machine instruction 33//--------------------------------------------------------------------------- 34 35typedef short MachineOpCode; 36typedef unsigned InstrSchedClass; 37 38//--------------------------------------------------------------------------- 39// struct TargetInstrDescriptor: 40// Predefined information about each machine instruction. 41// Designed to initialized statically. 42// 43 44const unsigned M_BRANCH_FLAG = 1 << 0; 45const unsigned M_CALL_FLAG = 1 << 1; 46const unsigned M_RET_FLAG = 1 << 2; 47const unsigned M_BARRIER_FLAG = 1 << 3; 48const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 49const unsigned M_LOAD_FLAG = 1 << 5; 50const unsigned M_STORE_FLAG = 1 << 6; 51 52// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 53// changed into a 3-address instruction if the first two operands cannot be 54// assigned to the same register. The target must implement the 55// TargetInstrInfo::convertToThreeAddress method for this instruction. 56const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 57 58// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 59// Z), which produces the same result if Y and Z are exchanged. 60const unsigned M_COMMUTABLE = 1 << 8; 61 62// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 63// block? Typically this is things like return and branch instructions. 64// Various passes use this to insert code into the bottom of a basic block, but 65// before control flow occurs. 66const unsigned M_TERMINATOR_FLAG = 1 << 9; 67 68// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 69// insertion support when the DAG scheduler is inserting it into a machine basic 70// block. 71const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 72 73// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 74// operands in addition to the minimum number operands specified. 75const unsigned M_VARIABLE_OPS = 1 << 11; 76 77// M_PREDICABLE - Set if this instruction has a predicate operand that 78// controls execution. It may be set to 'always'. 79const unsigned M_PREDICABLE = 1 << 12; 80 81// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 82// at any time, e.g. constant generation, load from constant pool. 83const unsigned M_REMATERIALIZIBLE = 1 << 13; 84 85 86// Machine operand flags 87// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 88// requires a callback to look up its register class. 89const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 90 91/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the 92/// predicate operand that controls an M_PREDICATED instruction. 93const unsigned M_PREDICATE_OPERAND = 1 << 1; 94 95namespace TOI { 96 // Operand constraints: only "tied_to" for now. 97 enum OperandConstraint { 98 TIED_TO = 0 // Must be allocated the same register as. 99 }; 100} 101 102/// TargetOperandInfo - This holds information about one operand of a machine 103/// instruction, indicating the register class for register operands, etc. 104/// 105class TargetOperandInfo { 106public: 107 /// RegClass - This specifies the register class enumeration of the operand 108 /// if the operand is a register. If not, this contains 0. 109 unsigned short RegClass; 110 unsigned short Flags; 111 /// Lower 16 bits are used to specify which constraints are set. The higher 16 112 /// bits are used to specify the value of constraints (4 bits each). 113 unsigned int Constraints; 114 /// Currently no other information. 115}; 116 117 118class TargetInstrDescriptor { 119public: 120 MachineOpCode Opcode; // The opcode. 121 unsigned short numOperands; // Num of args (may be more if variable_ops). 122 const char * Name; // Assembly language mnemonic for the opcode. 123 InstrSchedClass schedClass; // enum identifying instr sched class 124 unsigned Flags; // flags identifying machine instr class 125 unsigned TSFlags; // Target Specific Flag values 126 const unsigned *ImplicitUses; // Registers implicitly read by this instr 127 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 128 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 129 130 /// getOperandConstraint - Returns the value of the specific constraint if 131 /// it is set. Returns -1 if it is not set. 132 int getOperandConstraint(unsigned OpNum, 133 TOI::OperandConstraint Constraint) const { 134 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 135 "Invalid operand # of TargetInstrInfo"); 136 if (OpNum < numOperands && 137 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 138 unsigned Pos = 16 + Constraint * 4; 139 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 140 } 141 return -1; 142 } 143 144 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 145 /// dest operand. Returns -1 if there isn't one. 146 int findTiedToSrcOperand(unsigned OpNum) const; 147}; 148 149 150//--------------------------------------------------------------------------- 151/// 152/// TargetInstrInfo - Interface to description of machine instructions 153/// 154class TargetInstrInfo { 155 const TargetInstrDescriptor* desc; // raw array to allow static init'n 156 unsigned NumOpcodes; // number of entries in the desc array 157 unsigned numRealOpCodes; // number of non-dummy op codes 158 159 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 160 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 161public: 162 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 163 virtual ~TargetInstrInfo(); 164 165 // Invariant opcodes: All instruction sets have these as their low opcodes. 166 enum { 167 PHI = 0, 168 INLINEASM = 1, 169 LABEL = 2 170 }; 171 172 unsigned getNumOpcodes() const { return NumOpcodes; } 173 174 /// get - Return the machine instruction descriptor that corresponds to the 175 /// specified instruction opcode. 176 /// 177 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 178 assert((unsigned)Opcode < NumOpcodes); 179 return desc[Opcode]; 180 } 181 182 const char *getName(MachineOpCode Opcode) const { 183 return get(Opcode).Name; 184 } 185 186 int getNumOperands(MachineOpCode Opcode) const { 187 return get(Opcode).numOperands; 188 } 189 190 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 191 return get(Opcode).schedClass; 192 } 193 194 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 195 return get(Opcode).ImplicitUses; 196 } 197 198 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 199 return get(Opcode).ImplicitDefs; 200 } 201 202 203 // 204 // Query instruction class flags according to the machine-independent 205 // flags listed above. 206 // 207 bool isReturn(MachineOpCode Opcode) const { 208 return get(Opcode).Flags & M_RET_FLAG; 209 } 210 211 bool isPredicable(MachineOpCode Opcode) const { 212 return get(Opcode).Flags & M_PREDICABLE; 213 } 214 bool isReMaterializable(MachineOpCode Opcode) const { 215 return get(Opcode).Flags & M_REMATERIALIZIBLE; 216 } 217 bool isCommutableInstr(MachineOpCode Opcode) const { 218 return get(Opcode).Flags & M_COMMUTABLE; 219 } 220 bool isTerminatorInstr(unsigned Opcode) const { 221 return get(Opcode).Flags & M_TERMINATOR_FLAG; 222 } 223 224 bool isBranch(MachineOpCode Opcode) const { 225 return get(Opcode).Flags & M_BRANCH_FLAG; 226 } 227 228 /// isBarrier - Returns true if the specified instruction stops control flow 229 /// from executing the instruction immediately following it. Examples include 230 /// unconditional branches and return instructions. 231 bool isBarrier(MachineOpCode Opcode) const { 232 return get(Opcode).Flags & M_BARRIER_FLAG; 233 } 234 235 bool isCall(MachineOpCode Opcode) const { 236 return get(Opcode).Flags & M_CALL_FLAG; 237 } 238 bool isLoad(MachineOpCode Opcode) const { 239 return get(Opcode).Flags & M_LOAD_FLAG; 240 } 241 bool isStore(MachineOpCode Opcode) const { 242 return get(Opcode).Flags & M_STORE_FLAG; 243 } 244 245 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 246 /// which must be filled by the code generator. 247 bool hasDelaySlot(unsigned Opcode) const { 248 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 249 } 250 251 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 252 /// custom insertion support when the DAG scheduler is inserting it into a 253 /// machine basic block. 254 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 255 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 256 } 257 258 bool hasVariableOperands(MachineOpCode Opcode) const { 259 return get(Opcode).Flags & M_VARIABLE_OPS; 260 } 261 262 /// getOperandConstraint - Returns the value of the specific constraint if 263 /// it is set. Returns -1 if it is not set. 264 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 265 TOI::OperandConstraint Constraint) const { 266 return get(Opcode).getOperandConstraint(OpNum, Constraint); 267 } 268 269 /// Return true if the instruction is a register to register move 270 /// and leave the source and dest operands in the passed parameters. 271 virtual bool isMoveInstr(const MachineInstr& MI, 272 unsigned& sourceReg, 273 unsigned& destReg) const { 274 return false; 275 } 276 277 /// isLoadFromStackSlot - If the specified machine instruction is a direct 278 /// load from a stack slot, return the virtual or physical register number of 279 /// the destination along with the FrameIndex of the loaded stack slot. If 280 /// not, return 0. This predicate must return 0 if the instruction has 281 /// any side effects other than loading from the stack slot. 282 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 283 return 0; 284 } 285 286 /// isStoreToStackSlot - If the specified machine instruction is a direct 287 /// store to a stack slot, return the virtual or physical register number of 288 /// the source reg along with the FrameIndex of the loaded stack slot. If 289 /// not, return 0. This predicate must return 0 if the instruction has 290 /// any side effects other than storing to the stack slot. 291 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 292 return 0; 293 } 294 295 /// convertToThreeAddress - This method must be implemented by targets that 296 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 297 /// may be able to convert a two-address instruction into one or moretrue 298 /// three-address instructions on demand. This allows the X86 target (for 299 /// example) to convert ADD and SHL instructions into LEA instructions if they 300 /// would require register copies due to two-addressness. 301 /// 302 /// This method returns a null pointer if the transformation cannot be 303 /// performed, otherwise it returns the last new instruction. 304 /// 305 virtual MachineInstr * 306 convertToThreeAddress(MachineFunction::iterator &MFI, 307 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 308 return 0; 309 } 310 311 /// commuteInstruction - If a target has any instructions that are commutable, 312 /// but require converting to a different instruction or making non-trivial 313 /// changes to commute them, this method can overloaded to do this. The 314 /// default implementation of this method simply swaps the first two operands 315 /// of MI and returns it. 316 /// 317 /// If a target wants to make more aggressive changes, they can construct and 318 /// return a new machine instruction. If an instruction cannot commute, it 319 /// can also return null. 320 /// 321 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 322 323 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 324 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 325 /// implemented for a target). Upon success, this returns false and returns 326 /// with the following information in various cases: 327 /// 328 /// 1. If this block ends with no branches (it just falls through to its succ) 329 /// just return false, leaving TBB/FBB null. 330 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 331 /// the destination block. 332 /// 3. If this block ends with an conditional branch and it falls through to 333 /// an successor block, it sets TBB to be the branch destination block and a 334 /// list of operands that evaluate the condition. These 335 /// operands can be passed to other TargetInstrInfo methods to create new 336 /// branches. 337 /// 4. If this block ends with an conditional branch and an unconditional 338 /// block, it returns the 'true' destination in TBB, the 'false' destination 339 /// in FBB, and a list of operands that evaluate the condition. These 340 /// operands can be passed to other TargetInstrInfo methods to create new 341 /// branches. 342 /// 343 /// Note that RemoveBranch and InsertBranch must be implemented to support 344 /// cases where this method returns success. 345 /// 346 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 347 MachineBasicBlock *&FBB, 348 std::vector<MachineOperand> &Cond) const { 349 return true; 350 } 351 352 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 353 /// this is only invoked in cases where AnalyzeBranch returns success. It 354 /// returns the number of instructions that were removed. 355 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 356 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 357 return 0; 358 } 359 360 /// InsertBranch - Insert a branch into the end of the specified 361 /// MachineBasicBlock. This operands to this method are the same as those 362 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 363 /// returns success and when an unconditional branch (TBB is non-null, FBB is 364 /// null, Cond is empty) needs to be inserted. It returns the number of 365 /// instructions inserted. 366 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 367 MachineBasicBlock *FBB, 368 const std::vector<MachineOperand> &Cond) const { 369 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 370 return 0; 371 } 372 373 /// BlockHasNoFallThrough - Return true if the specified block does not 374 /// fall-through into its successor block. This is primarily used when a 375 /// branch is unanalyzable. It is useful for things like unconditional 376 /// indirect branches (jump tables). 377 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 378 return false; 379 } 380 381 /// ReverseBranchCondition - Reverses the branch condition of the specified 382 /// condition list, returning false on success and true if it cannot be 383 /// reversed. 384 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 385 return true; 386 } 387 388 /// insertNoop - Insert a noop into the instruction stream at the specified 389 /// point. 390 virtual void insertNoop(MachineBasicBlock &MBB, 391 MachineBasicBlock::iterator MI) const { 392 assert(0 && "Target didn't implement insertNoop!"); 393 abort(); 394 } 395 396 /// PredicateInstruction - Convert the instruction into a predicated 397 /// instruction. It returns true if the operation was successful. 398 virtual bool PredicateInstruction(MachineInstr *MI, 399 std::vector<MachineOperand> &Cond) const; 400 401 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 402 /// values. 403 virtual const TargetRegisterClass *getPointerRegClass() const { 404 assert(0 && "Target didn't implement getPointerRegClass!"); 405 abort(); 406 return 0; // Must return a value in order to compile with VS 2005 407 } 408}; 409 410} // End llvm namespace 411 412#endif 413