TargetInstrInfo.h revision d7908f679eeadc108e09e2aca5faba0b5410ea4a
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===----------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_TARGETINSTRINFO_H 8#define LLVM_TARGET_TARGETINSTRINFO_H 9 10#include "Support/DataTypes.h" 11#include <vector> 12#include <assert.h> 13 14class MachineInstr; 15class TargetMachine; 16class Value; 17class Instruction; 18class Constant; 19class Function; 20class MachineCodeForInstruction; 21 22//--------------------------------------------------------------------------- 23// Data types used to define information about a single machine instruction 24//--------------------------------------------------------------------------- 25 26typedef int MachineOpCode; 27typedef unsigned InstrSchedClass; 28 29const MachineOpCode INVALID_MACHINE_OPCODE = -1; 30 31 32//--------------------------------------------------------------------------- 33// struct TargetInstrDescriptor: 34// Predefined information about each machine instruction. 35// Designed to initialized statically. 36// 37 38const unsigned M_NOP_FLAG = 1 << 0; 39const unsigned M_BRANCH_FLAG = 1 << 1; 40const unsigned M_CALL_FLAG = 1 << 2; 41const unsigned M_RET_FLAG = 1 << 3; 42const unsigned M_ARITH_FLAG = 1 << 4; 43const unsigned M_CC_FLAG = 1 << 6; 44const unsigned M_LOGICAL_FLAG = 1 << 6; 45const unsigned M_INT_FLAG = 1 << 7; 46const unsigned M_FLOAT_FLAG = 1 << 8; 47const unsigned M_CONDL_FLAG = 1 << 9; 48const unsigned M_LOAD_FLAG = 1 << 10; 49const unsigned M_PREFETCH_FLAG = 1 << 11; 50const unsigned M_STORE_FLAG = 1 << 12; 51const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 52const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction 53// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub 54const unsigned M_2_ADDR_FLAG = 1 << 15; 55 56// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 57// block? Typically this is things like return and branch instructions. 58// Various passes use this to insert code into the bottom of a basic block, but 59// before control flow occurs. 60const unsigned M_TERMINATOR_FLAG = 1 << 16; 61 62struct TargetInstrDescriptor { 63 const char * Name; // Assembly language mnemonic for the opcode. 64 int numOperands; // Number of args; -1 if variable #args 65 int resultPos; // Position of the result; -1 if no result 66 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 67 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 68 // smallest -ve value is -(maxImmedConst+1). 69 unsigned numDelaySlots; // Number of delay slots after instruction 70 unsigned latency; // Latency in machine cycles 71 InstrSchedClass schedClass; // enum identifying instr sched class 72 unsigned Flags; // flags identifying machine instr class 73 unsigned TSFlags; // Target Specific Flag values 74 const unsigned *ImplicitUses; // Registers implicitly read by this instr 75 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 76}; 77 78 79//--------------------------------------------------------------------------- 80/// 81/// TargetInstrInfo - Interface to description of machine instructions 82/// 83class TargetInstrInfo { 84 const TargetInstrDescriptor* desc; // raw array to allow static init'n 85 unsigned descSize; // number of entries in the desc array 86 unsigned numRealOpCodes; // number of non-dummy op codes 87 88 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 89 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 90public: 91 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize, 92 unsigned numRealOpCodes); 93 virtual ~TargetInstrInfo(); 94 95 // Invariant: All instruction sets use opcode #0 as the PHI instruction and 96 // opcode #1 as the noop instruction. 97 enum { 98 PHI = 0, NOOP = 1 99 }; 100 101 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 102 unsigned getNumTotalOpCodes() const { return descSize; } 103 104 /// get - Return the machine instruction descriptor that corresponds to the 105 /// specified instruction opcode. 106 /// 107 const TargetInstrDescriptor& get(MachineOpCode opCode) const { 108 assert(opCode >= 0 && opCode < (int)descSize); 109 return desc[opCode]; 110 } 111 112 const char *getName(MachineOpCode opCode) const { 113 return get(opCode).Name; 114 } 115 116 int getNumOperands(MachineOpCode opCode) const { 117 return get(opCode).numOperands; 118 } 119 120 int getResultPos(MachineOpCode opCode) const { 121 return get(opCode).resultPos; 122 } 123 124 unsigned getNumDelaySlots(MachineOpCode opCode) const { 125 return get(opCode).numDelaySlots; 126 } 127 128 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 129 return get(opCode).schedClass; 130 } 131 132 const unsigned *getImplicitUses(MachineOpCode opCode) const { 133 return get(opCode).ImplicitUses; 134 } 135 136 const unsigned *getImplicitDefs(MachineOpCode opCode) const { 137 return get(opCode).ImplicitDefs; 138 } 139 140 // 141 // Query instruction class flags according to the machine-independent 142 // flags listed above. 143 // 144 bool isNop(MachineOpCode opCode) const { 145 return get(opCode).Flags & M_NOP_FLAG; 146 } 147 bool isBranch(MachineOpCode opCode) const { 148 return get(opCode).Flags & M_BRANCH_FLAG; 149 } 150 bool isCall(MachineOpCode opCode) const { 151 return get(opCode).Flags & M_CALL_FLAG; 152 } 153 bool isReturn(MachineOpCode opCode) const { 154 return get(opCode).Flags & M_RET_FLAG; 155 } 156 bool isControlFlow(MachineOpCode opCode) const { 157 return get(opCode).Flags & M_BRANCH_FLAG 158 || get(opCode).Flags & M_CALL_FLAG 159 || get(opCode).Flags & M_RET_FLAG; 160 } 161 bool isArith(MachineOpCode opCode) const { 162 return get(opCode).Flags & M_ARITH_FLAG; 163 } 164 bool isCCInstr(MachineOpCode opCode) const { 165 return get(opCode).Flags & M_CC_FLAG; 166 } 167 bool isLogical(MachineOpCode opCode) const { 168 return get(opCode).Flags & M_LOGICAL_FLAG; 169 } 170 bool isIntInstr(MachineOpCode opCode) const { 171 return get(opCode).Flags & M_INT_FLAG; 172 } 173 bool isFloatInstr(MachineOpCode opCode) const { 174 return get(opCode).Flags & M_FLOAT_FLAG; 175 } 176 bool isConditional(MachineOpCode opCode) const { 177 return get(opCode).Flags & M_CONDL_FLAG; 178 } 179 bool isLoad(MachineOpCode opCode) const { 180 return get(opCode).Flags & M_LOAD_FLAG; 181 } 182 bool isPrefetch(MachineOpCode opCode) const { 183 return get(opCode).Flags & M_PREFETCH_FLAG; 184 } 185 bool isLoadOrPrefetch(MachineOpCode opCode) const { 186 return get(opCode).Flags & M_LOAD_FLAG 187 || get(opCode).Flags & M_PREFETCH_FLAG; 188 } 189 bool isStore(MachineOpCode opCode) const { 190 return get(opCode).Flags & M_STORE_FLAG; 191 } 192 bool isMemoryAccess(MachineOpCode opCode) const { 193 return get(opCode).Flags & M_LOAD_FLAG 194 || get(opCode).Flags & M_PREFETCH_FLAG 195 || get(opCode).Flags & M_STORE_FLAG; 196 } 197 bool isDummyPhiInstr(MachineOpCode opCode) const { 198 return get(opCode).Flags & M_DUMMY_PHI_FLAG; 199 } 200 bool isPseudoInstr(MachineOpCode opCode) const { 201 return get(opCode).Flags & M_PSEUDO_FLAG; 202 } 203 bool isTwoAddrInstr(MachineOpCode opCode) const { 204 return get(opCode).Flags & M_2_ADDR_FLAG; 205 } 206 bool isTerminatorInstr(unsigned Opcode) const { 207 return get(Opcode).Flags & M_TERMINATOR_FLAG; 208 } 209 210 // Check if an instruction can be issued before its operands are ready, 211 // or if a subsequent instruction that uses its result can be issued 212 // before the results are ready. 213 // Default to true since most instructions on many architectures allow this. 214 // 215 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 216 return true; 217 } 218 219 virtual bool hasResultInterlock(MachineOpCode opCode) const { 220 return true; 221 } 222 223 // 224 // Latencies for individual instructions and instruction pairs 225 // 226 virtual int minLatency(MachineOpCode opCode) const { 227 return get(opCode).latency; 228 } 229 230 virtual int maxLatency(MachineOpCode opCode) const { 231 return get(opCode).latency; 232 } 233 234 // 235 // Which operand holds an immediate constant? Returns -1 if none 236 // 237 virtual int getImmedConstantPos(MachineOpCode opCode) const { 238 return -1; // immediate position is machine specific, so say -1 == "none" 239 } 240 241 // Check if the specified constant fits in the immediate field 242 // of this machine instruction 243 // 244 virtual bool constantFitsInImmedField(MachineOpCode opCode, 245 int64_t intValue) const; 246 247 // Return the largest +ve constant that can be held in the IMMMED field 248 // of this machine instruction. 249 // isSignExtended is set to true if the value is sign-extended before use 250 // (this is true for all immediate fields in SPARC instructions). 251 // Return 0 if the instruction has no IMMED field. 252 // 253 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 254 bool &isSignExtended) const { 255 isSignExtended = get(opCode).immedIsSignExtended; 256 return get(opCode).maxImmedConst; 257 } 258 259 //------------------------------------------------------------------------- 260 // Queries about representation of LLVM quantities (e.g., constants) 261 //------------------------------------------------------------------------- 262 263 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 264 /// from memory into a register, i.e., cannot be set bitwise in register and 265 /// cannot use immediate fields of instructions. Note that this only makes 266 /// sense for primitive types. 267 /// 268 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 269 270 // Test if this constant may not fit in the immediate field of the 271 // machine instructions (probably) generated for this instruction. 272 // 273 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 274 const Instruction* I) const { 275 return true; // safe but very conservative 276 } 277 278 279 /// createNOPinstr - returns the target's implementation of NOP, which is 280 /// usually a pseudo-instruction, implemented by a degenerate version of 281 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0 282 /// 283 virtual MachineInstr* createNOPinstr() const = 0; 284 285 /// isNOPinstr - not having a special NOP opcode, we need to know if a given 286 /// instruction is interpreted as an `official' NOP instr, i.e., there may be 287 /// more than one way to `do nothing' but only one canonical way to slack off. 288 /// 289 virtual bool isNOPinstr(const MachineInstr &MI) const = 0; 290 291 //------------------------------------------------------------------------- 292 // Code generation support for creating individual machine instructions 293 // 294 // WARNING: These methods are Sparc specific 295 // 296 //------------------------------------------------------------------------- 297 298 // Get certain common op codes for the current target. this and all the 299 // Create* methods below should be moved to a machine code generation class 300 // 301 virtual MachineOpCode getNOPOpCode() const { abort(); } 302 303 // Create an instruction sequence to put the constant `val' into 304 // the virtual register `dest'. `val' may be a Constant or a 305 // GlobalValue, viz., the constant address of a global variable or function. 306 // The generated instructions are returned in `mvec'. 307 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 308 // Symbolic constants or constants that must be accessed from memory 309 // are added to the constant pool via MachineFunction::get(F). 310 // 311 virtual void CreateCodeToLoadConst(const TargetMachine& target, 312 Function* F, 313 Value* val, 314 Instruction* dest, 315 std::vector<MachineInstr*>& mvec, 316 MachineCodeForInstruction& mcfi) const { 317 abort(); 318 } 319 320 // Create an instruction sequence to copy an integer value `val' 321 // to a floating point value `dest' by copying to memory and back. 322 // val must be an integral type. dest must be a Float or Double. 323 // The generated instructions are returned in `mvec'. 324 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 325 // Any stack space required is allocated via mcff. 326 // 327 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 328 Function* F, 329 Value* val, 330 Instruction* dest, 331 std::vector<MachineInstr*>& mvec, 332 MachineCodeForInstruction& MI) const { 333 abort(); 334 } 335 336 // Similarly, create an instruction sequence to copy an FP value 337 // `val' to an integer value `dest' by copying to memory and back. 338 // The generated instructions are returned in `mvec'. 339 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 340 // Any stack space required is allocated via mcff. 341 // 342 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 343 Function* F, 344 Value* val, 345 Instruction* dest, 346 std::vector<MachineInstr*>& mvec, 347 MachineCodeForInstruction& MI) const { 348 abort(); 349 } 350 351 // Create instruction(s) to copy src to dest, for arbitrary types 352 // The generated instructions are returned in `mvec'. 353 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 354 // Any stack space required is allocated via mcff. 355 // 356 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 357 Function* F, 358 Value* src, 359 Instruction* dest, 360 std::vector<MachineInstr*>& mvec, 361 MachineCodeForInstruction& MI) const { 362 abort(); 363 } 364 365 // Create instruction sequence to produce a sign-extended register value 366 // from an arbitrary sized value (sized in bits, not bytes). 367 // The generated instructions are appended to `mvec'. 368 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 369 // Any stack space required is allocated via mcff. 370 // 371 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 372 Function* F, 373 Value* srcVal, 374 Value* destVal, 375 unsigned numLowBits, 376 std::vector<MachineInstr*>& mvec, 377 MachineCodeForInstruction& MI) const { 378 abort(); 379 } 380 381 // Create instruction sequence to produce a zero-extended register value 382 // from an arbitrary sized value (sized in bits, not bytes). 383 // The generated instructions are appended to `mvec'. 384 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 385 // Any stack space required is allocated via mcff. 386 // 387 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 388 Function* F, 389 Value* srcVal, 390 Value* destVal, 391 unsigned srcSizeInBits, 392 std::vector<MachineInstr*>& mvec, 393 MachineCodeForInstruction& mcfi) const { 394 abort(); 395 } 396}; 397 398#endif 399