TargetInstrInfo.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/ADT/SmallSet.h" 18#include "llvm/CodeGen/DFAPacketizer.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/MC/MCInstrInfo.h" 21 22namespace llvm { 23 24class InstrItineraryData; 25class LiveVariables; 26class MCAsmInfo; 27class MachineMemOperand; 28class MachineRegisterInfo; 29class MDNode; 30class MCInst; 31class MCSchedModel; 32class SDNode; 33class ScheduleHazardRecognizer; 34class SelectionDAG; 35class ScheduleDAG; 36class TargetRegisterClass; 37class TargetRegisterInfo; 38class BranchProbability; 39 40template<class T> class SmallVectorImpl; 41 42 43//--------------------------------------------------------------------------- 44/// 45/// TargetInstrInfo - Interface to description of machine instruction set 46/// 47class TargetInstrInfo : public MCInstrInfo { 48 TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 49 void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 50public: 51 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) 52 : CallFrameSetupOpcode(CFSetupOpcode), 53 CallFrameDestroyOpcode(CFDestroyOpcode) { 54 } 55 56 virtual ~TargetInstrInfo(); 57 58 /// getRegClass - Givem a machine instruction descriptor, returns the register 59 /// class constraint for OpNum, or NULL. 60 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 61 unsigned OpNum, 62 const TargetRegisterInfo *TRI, 63 const MachineFunction &MF) const; 64 65 /// isTriviallyReMaterializable - Return true if the instruction is trivially 66 /// rematerializable, meaning it has no side effects and requires no operands 67 /// that aren't always available. 68 bool isTriviallyReMaterializable(const MachineInstr *MI, 69 AliasAnalysis *AA = nullptr) const { 70 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 71 (MI->getDesc().isRematerializable() && 72 (isReallyTriviallyReMaterializable(MI, AA) || 73 isReallyTriviallyReMaterializableGeneric(MI, AA))); 74 } 75 76protected: 77 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 78 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 79 /// specify whether the instruction is actually trivially rematerializable, 80 /// taking into consideration its operands. This predicate must return false 81 /// if the instruction has any side effects other than producing a value, or 82 /// if it requres any address registers that are not always available. 83 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 84 AliasAnalysis *AA) const { 85 return false; 86 } 87 88private: 89 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 90 /// for which the M_REMATERIALIZABLE flag is set and the target hook 91 /// isReallyTriviallyReMaterializable returns false, this function does 92 /// target-independent tests to determine if the instruction is really 93 /// trivially rematerializable. 94 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 95 AliasAnalysis *AA) const; 96 97public: 98 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 99 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 100 /// targets use pseudo instructions in order to abstract away the difference 101 /// between operating with a frame pointer and operating without, through the 102 /// use of these two instructions. 103 /// 104 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 105 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 106 107 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 108 /// extension instruction. That is, it's like a copy where it's legal for the 109 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 110 /// true, then it's expected the pre-extension value is available as a subreg 111 /// of the result register. This also returns the sub-register index in 112 /// SubIdx. 113 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 114 unsigned &SrcReg, unsigned &DstReg, 115 unsigned &SubIdx) const { 116 return false; 117 } 118 119 /// isLoadFromStackSlot - If the specified machine instruction is a direct 120 /// load from a stack slot, return the virtual or physical register number of 121 /// the destination along with the FrameIndex of the loaded stack slot. If 122 /// not, return 0. This predicate must return 0 if the instruction has 123 /// any side effects other than loading from the stack slot. 124 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 125 int &FrameIndex) const { 126 return 0; 127 } 128 129 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 130 /// stack locations as well. This uses a heuristic so it isn't 131 /// reliable for correctness. 132 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 133 int &FrameIndex) const { 134 return 0; 135 } 136 137 /// hasLoadFromStackSlot - If the specified machine instruction has 138 /// a load from a stack slot, return true along with the FrameIndex 139 /// of the loaded stack slot and the machine mem operand containing 140 /// the reference. If not, return false. Unlike 141 /// isLoadFromStackSlot, this returns true for any instructions that 142 /// loads from the stack. This is just a hint, as some cases may be 143 /// missed. 144 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 145 const MachineMemOperand *&MMO, 146 int &FrameIndex) const; 147 148 /// isStoreToStackSlot - If the specified machine instruction is a direct 149 /// store to a stack slot, return the virtual or physical register number of 150 /// the source reg along with the FrameIndex of the loaded stack slot. If 151 /// not, return 0. This predicate must return 0 if the instruction has 152 /// any side effects other than storing to the stack slot. 153 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 154 int &FrameIndex) const { 155 return 0; 156 } 157 158 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 159 /// stack locations as well. This uses a heuristic so it isn't 160 /// reliable for correctness. 161 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 162 int &FrameIndex) const { 163 return 0; 164 } 165 166 /// hasStoreToStackSlot - If the specified machine instruction has a 167 /// store to a stack slot, return true along with the FrameIndex of 168 /// the loaded stack slot and the machine mem operand containing the 169 /// reference. If not, return false. Unlike isStoreToStackSlot, 170 /// this returns true for any instructions that stores to the 171 /// stack. This is just a hint, as some cases may be missed. 172 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 173 const MachineMemOperand *&MMO, 174 int &FrameIndex) const; 175 176 /// isStackSlotCopy - Return true if the specified machine instruction 177 /// is a copy of one stack slot to another and has no other effect. 178 /// Provide the identity of the two frame indices. 179 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, 180 int &SrcFrameIndex) const { 181 return false; 182 } 183 184 /// Compute the size in bytes and offset within a stack slot of a spilled 185 /// register or subregister. 186 /// 187 /// \param [out] Size in bytes of the spilled value. 188 /// \param [out] Offset in bytes within the stack slot. 189 /// \returns true if both Size and Offset are successfully computed. 190 /// 191 /// Not all subregisters have computable spill slots. For example, 192 /// subregisters registers may not be byte-sized, and a pair of discontiguous 193 /// subregisters has no single offset. 194 /// 195 /// Targets with nontrivial bigendian implementations may need to override 196 /// this, particularly to support spilled vector registers. 197 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 198 unsigned &Size, unsigned &Offset, 199 const TargetMachine *TM) const; 200 201 /// reMaterialize - Re-issue the specified 'original' instruction at the 202 /// specific location targeting a new destination register. 203 /// The register in Orig->getOperand(0).getReg() will be substituted by 204 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 205 /// SubIdx. 206 virtual void reMaterialize(MachineBasicBlock &MBB, 207 MachineBasicBlock::iterator MI, 208 unsigned DestReg, unsigned SubIdx, 209 const MachineInstr *Orig, 210 const TargetRegisterInfo &TRI) const; 211 212 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 213 /// MachineFunction::CloneMachineInstr(), but the target may update operands 214 /// that are required to be unique. 215 /// 216 /// The instruction must be duplicable as indicated by isNotDuplicable(). 217 virtual MachineInstr *duplicate(MachineInstr *Orig, 218 MachineFunction &MF) const; 219 220 /// convertToThreeAddress - This method must be implemented by targets that 221 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 222 /// may be able to convert a two-address instruction into one or more true 223 /// three-address instructions on demand. This allows the X86 target (for 224 /// example) to convert ADD and SHL instructions into LEA instructions if they 225 /// would require register copies due to two-addressness. 226 /// 227 /// This method returns a null pointer if the transformation cannot be 228 /// performed, otherwise it returns the last new instruction. 229 /// 230 virtual MachineInstr * 231 convertToThreeAddress(MachineFunction::iterator &MFI, 232 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 233 return nullptr; 234 } 235 236 /// commuteInstruction - If a target has any instructions that are 237 /// commutable but require converting to different instructions or making 238 /// non-trivial changes to commute them, this method can overloaded to do 239 /// that. The default implementation simply swaps the commutable operands. 240 /// If NewMI is false, MI is modified in place and returned; otherwise, a 241 /// new machine instruction is created and returned. Do not call this 242 /// method for a non-commutable instruction, but there may be some cases 243 /// where this method fails and returns null. 244 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 245 bool NewMI = false) const; 246 247 /// findCommutedOpIndices - If specified MI is commutable, return the two 248 /// operand indices that would swap value. Return false if the instruction 249 /// is not in a form which this routine understands. 250 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 251 unsigned &SrcOpIdx2) const; 252 253 /// produceSameValue - Return true if two machine instructions would produce 254 /// identical values. By default, this is only true when the two instructions 255 /// are deemed identical except for defs. If this function is called when the 256 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 257 /// aggressive checks. 258 virtual bool produceSameValue(const MachineInstr *MI0, 259 const MachineInstr *MI1, 260 const MachineRegisterInfo *MRI = nullptr) const; 261 262 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 263 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 264 /// implemented for a target). Upon success, this returns false and returns 265 /// with the following information in various cases: 266 /// 267 /// 1. If this block ends with no branches (it just falls through to its succ) 268 /// just return false, leaving TBB/FBB null. 269 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 270 /// the destination block. 271 /// 3. If this block ends with a conditional branch and it falls through to a 272 /// successor block, it sets TBB to be the branch destination block and a 273 /// list of operands that evaluate the condition. These operands can be 274 /// passed to other TargetInstrInfo methods to create new branches. 275 /// 4. If this block ends with a conditional branch followed by an 276 /// unconditional branch, it returns the 'true' destination in TBB, the 277 /// 'false' destination in FBB, and a list of operands that evaluate the 278 /// condition. These operands can be passed to other TargetInstrInfo 279 /// methods to create new branches. 280 /// 281 /// Note that RemoveBranch and InsertBranch must be implemented to support 282 /// cases where this method returns success. 283 /// 284 /// If AllowModify is true, then this routine is allowed to modify the basic 285 /// block (e.g. delete instructions after the unconditional branch). 286 /// 287 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 288 MachineBasicBlock *&FBB, 289 SmallVectorImpl<MachineOperand> &Cond, 290 bool AllowModify = false) const { 291 return true; 292 } 293 294 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 295 /// This is only invoked in cases where AnalyzeBranch returns success. It 296 /// returns the number of instructions that were removed. 297 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 298 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); 299 } 300 301 /// InsertBranch - Insert branch code into the end of the specified 302 /// MachineBasicBlock. The operands to this method are the same as those 303 /// returned by AnalyzeBranch. This is only invoked in cases where 304 /// AnalyzeBranch returns success. It returns the number of instructions 305 /// inserted. 306 /// 307 /// It is also invoked by tail merging to add unconditional branches in 308 /// cases where AnalyzeBranch doesn't apply because there was no original 309 /// branch to analyze. At least this much must be implemented, else tail 310 /// merging needs to be disabled. 311 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 312 MachineBasicBlock *FBB, 313 const SmallVectorImpl<MachineOperand> &Cond, 314 DebugLoc DL) const { 315 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); 316 } 317 318 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 319 /// after it, replacing it with an unconditional branch to NewDest. This is 320 /// used by the tail merging pass. 321 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 322 MachineBasicBlock *NewDest) const; 323 324 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 325 /// block at the specified instruction (i.e. instruction would be the start 326 /// of a new basic block). 327 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 328 MachineBasicBlock::iterator MBBI) const { 329 return true; 330 } 331 332 /// isProfitableToIfCvt - Return true if it's profitable to predicate 333 /// instructions with accumulated instruction latency of "NumCycles" 334 /// of the specified basic block, where the probability of the instructions 335 /// being executed is given by Probability, and Confidence is a measure 336 /// of our confidence that it will be properly predicted. 337 virtual 338 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 339 unsigned ExtraPredCycles, 340 const BranchProbability &Probability) const { 341 return false; 342 } 343 344 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 345 /// checks for the case where two basic blocks from true and false path 346 /// of a if-then-else (diamond) are predicated on mutally exclusive 347 /// predicates, where the probability of the true path being taken is given 348 /// by Probability, and Confidence is a measure of our confidence that it 349 /// will be properly predicted. 350 virtual bool 351 isProfitableToIfCvt(MachineBasicBlock &TMBB, 352 unsigned NumTCycles, unsigned ExtraTCycles, 353 MachineBasicBlock &FMBB, 354 unsigned NumFCycles, unsigned ExtraFCycles, 355 const BranchProbability &Probability) const { 356 return false; 357 } 358 359 /// isProfitableToDupForIfCvt - Return true if it's profitable for 360 /// if-converter to duplicate instructions of specified accumulated 361 /// instruction latencies in the specified MBB to enable if-conversion. 362 /// The probability of the instructions being executed is given by 363 /// Probability, and Confidence is a measure of our confidence that it 364 /// will be properly predicted. 365 virtual bool 366 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 367 const BranchProbability &Probability) const { 368 return false; 369 } 370 371 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate 372 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 373 /// exclusive predicates. 374 /// e.g. 375 /// subeq r0, r1, #1 376 /// addne r0, r1, #1 377 /// => 378 /// sub r0, r1, #1 379 /// addne r0, r1, #1 380 /// 381 /// This may be profitable is conditional instructions are always executed. 382 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 383 MachineBasicBlock &FMBB) const { 384 return false; 385 } 386 387 /// canInsertSelect - Return true if it is possible to insert a select 388 /// instruction that chooses between TrueReg and FalseReg based on the 389 /// condition code in Cond. 390 /// 391 /// When successful, also return the latency in cycles from TrueReg, 392 /// FalseReg, and Cond to the destination register. In most cases, a select 393 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 394 /// 395 /// Some x86 implementations have 2-cycle cmov instructions. 396 /// 397 /// @param MBB Block where select instruction would be inserted. 398 /// @param Cond Condition returned by AnalyzeBranch. 399 /// @param TrueReg Virtual register to select when Cond is true. 400 /// @param FalseReg Virtual register to select when Cond is false. 401 /// @param CondCycles Latency from Cond+Branch to select output. 402 /// @param TrueCycles Latency from TrueReg to select output. 403 /// @param FalseCycles Latency from FalseReg to select output. 404 virtual bool canInsertSelect(const MachineBasicBlock &MBB, 405 const SmallVectorImpl<MachineOperand> &Cond, 406 unsigned TrueReg, unsigned FalseReg, 407 int &CondCycles, 408 int &TrueCycles, int &FalseCycles) const { 409 return false; 410 } 411 412 /// insertSelect - Insert a select instruction into MBB before I that will 413 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when 414 /// Cond is false. 415 /// 416 /// This function can only be called after canInsertSelect() returned true. 417 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed 418 /// that the same flags or registers required by Cond are available at the 419 /// insertion point. 420 /// 421 /// @param MBB Block where select instruction should be inserted. 422 /// @param I Insertion point. 423 /// @param DL Source location for debugging. 424 /// @param DstReg Virtual register to be defined by select instruction. 425 /// @param Cond Condition as computed by AnalyzeBranch. 426 /// @param TrueReg Virtual register to copy when Cond is true. 427 /// @param FalseReg Virtual register to copy when Cons is false. 428 virtual void insertSelect(MachineBasicBlock &MBB, 429 MachineBasicBlock::iterator I, DebugLoc DL, 430 unsigned DstReg, 431 const SmallVectorImpl<MachineOperand> &Cond, 432 unsigned TrueReg, unsigned FalseReg) const { 433 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); 434 } 435 436 /// analyzeSelect - Analyze the given select instruction, returning true if 437 /// it cannot be understood. It is assumed that MI->isSelect() is true. 438 /// 439 /// When successful, return the controlling condition and the operands that 440 /// determine the true and false result values. 441 /// 442 /// Result = SELECT Cond, TrueOp, FalseOp 443 /// 444 /// Some targets can optimize select instructions, for example by predicating 445 /// the instruction defining one of the operands. Such targets should set 446 /// Optimizable. 447 /// 448 /// @param MI Select instruction to analyze. 449 /// @param Cond Condition controlling the select. 450 /// @param TrueOp Operand number of the value selected when Cond is true. 451 /// @param FalseOp Operand number of the value selected when Cond is false. 452 /// @param Optimizable Returned as true if MI is optimizable. 453 /// @returns False on success. 454 virtual bool analyzeSelect(const MachineInstr *MI, 455 SmallVectorImpl<MachineOperand> &Cond, 456 unsigned &TrueOp, unsigned &FalseOp, 457 bool &Optimizable) const { 458 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction"); 459 return true; 460 } 461 462 /// optimizeSelect - Given a select instruction that was understood by 463 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by 464 /// merging it with one of its operands. Returns NULL on failure. 465 /// 466 /// When successful, returns the new select instruction. The client is 467 /// responsible for deleting MI. 468 /// 469 /// If both sides of the select can be optimized, PreferFalse is used to pick 470 /// a side. 471 /// 472 /// @param MI Optimizable select instruction. 473 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. 474 /// @returns Optimized instruction or NULL. 475 virtual MachineInstr *optimizeSelect(MachineInstr *MI, 476 bool PreferFalse = false) const { 477 // This function must be implemented if Optimizable is ever set. 478 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); 479 } 480 481 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 482 /// 483 /// This function should support copies within any legal register class as 484 /// well as any cross-class copies created during instruction selection. 485 /// 486 /// The source and destination registers may overlap, which may require a 487 /// careful implementation when multiple copy instructions are required for 488 /// large registers. See for example the ARM target. 489 virtual void copyPhysReg(MachineBasicBlock &MBB, 490 MachineBasicBlock::iterator MI, DebugLoc DL, 491 unsigned DestReg, unsigned SrcReg, 492 bool KillSrc) const { 493 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 494 } 495 496 /// storeRegToStackSlot - Store the specified register of the given register 497 /// class to the specified stack frame index. The store instruction is to be 498 /// added to the given machine basic block before the specified machine 499 /// instruction. If isKill is true, the register operand is the last use and 500 /// must be marked kill. 501 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 502 MachineBasicBlock::iterator MI, 503 unsigned SrcReg, bool isKill, int FrameIndex, 504 const TargetRegisterClass *RC, 505 const TargetRegisterInfo *TRI) const { 506 llvm_unreachable("Target didn't implement " 507 "TargetInstrInfo::storeRegToStackSlot!"); 508 } 509 510 /// loadRegFromStackSlot - Load the specified register of the given register 511 /// class from the specified stack frame index. The load instruction is to be 512 /// added to the given machine basic block before the specified machine 513 /// instruction. 514 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 515 MachineBasicBlock::iterator MI, 516 unsigned DestReg, int FrameIndex, 517 const TargetRegisterClass *RC, 518 const TargetRegisterInfo *TRI) const { 519 llvm_unreachable("Target didn't implement " 520 "TargetInstrInfo::loadRegFromStackSlot!"); 521 } 522 523 /// expandPostRAPseudo - This function is called for all pseudo instructions 524 /// that remain after register allocation. Many pseudo instructions are 525 /// created to help register allocation. This is the place to convert them 526 /// into real instructions. The target can edit MI in place, or it can insert 527 /// new instructions and erase MI. The function should return true if 528 /// anything was changed. 529 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 530 return false; 531 } 532 533 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 534 /// slot into the specified machine instruction for the specified operand(s). 535 /// If this is possible, a new instruction is returned with the specified 536 /// operand folded, otherwise NULL is returned. 537 /// The new instruction is inserted before MI, and the client is responsible 538 /// for removing the old instruction. 539 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 540 const SmallVectorImpl<unsigned> &Ops, 541 int FrameIndex) const; 542 543 /// foldMemoryOperand - Same as the previous version except it allows folding 544 /// of any load and store from / to any address, not just from a specific 545 /// stack slot. 546 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 547 const SmallVectorImpl<unsigned> &Ops, 548 MachineInstr* LoadMI) const; 549 550protected: 551 /// foldMemoryOperandImpl - Target-dependent implementation for 552 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 553 /// take care of adding a MachineMemOperand to the newly created instruction. 554 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 555 MachineInstr* MI, 556 const SmallVectorImpl<unsigned> &Ops, 557 int FrameIndex) const { 558 return nullptr; 559 } 560 561 /// foldMemoryOperandImpl - Target-dependent implementation for 562 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 563 /// take care of adding a MachineMemOperand to the newly created instruction. 564 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 565 MachineInstr* MI, 566 const SmallVectorImpl<unsigned> &Ops, 567 MachineInstr* LoadMI) const { 568 return nullptr; 569 } 570 571public: 572 /// canFoldMemoryOperand - Returns true for the specified load / store if 573 /// folding is possible. 574 virtual 575 bool canFoldMemoryOperand(const MachineInstr *MI, 576 const SmallVectorImpl<unsigned> &Ops) const; 577 578 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 579 /// a store or a load and a store into two or more instruction. If this is 580 /// possible, returns true as well as the new instructions by reference. 581 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 582 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 583 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 584 return false; 585 } 586 587 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 588 SmallVectorImpl<SDNode*> &NewNodes) const { 589 return false; 590 } 591 592 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 593 /// instruction after load / store are unfolded from an instruction of the 594 /// specified opcode. It returns zero if the specified unfolding is not 595 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 596 /// index of the operand which will hold the register holding the loaded 597 /// value. 598 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 599 bool UnfoldLoad, bool UnfoldStore, 600 unsigned *LoadRegIndex = nullptr) const { 601 return 0; 602 } 603 604 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 605 /// to determine if two loads are loading from the same base address. It 606 /// should only return true if the base pointers are the same and the 607 /// only differences between the two addresses are the offset. It also returns 608 /// the offsets by reference. 609 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 610 int64_t &Offset1, int64_t &Offset2) const { 611 return false; 612 } 613 614 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 615 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 616 /// be scheduled togther. On some targets if two loads are loading from 617 /// addresses in the same cache line, it's better if they are scheduled 618 /// together. This function takes two integers that represent the load offsets 619 /// from the common base address. It returns true if it decides it's desirable 620 /// to schedule the two loads together. "NumLoads" is the number of loads that 621 /// have already been scheduled after Load1. 622 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 623 int64_t Offset1, int64_t Offset2, 624 unsigned NumLoads) const { 625 return false; 626 } 627 628 /// \brief Get the base register and byte offset of a load/store instr. 629 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt, 630 unsigned &BaseReg, unsigned &Offset, 631 const TargetRegisterInfo *TRI) const { 632 return false; 633 } 634 635 virtual bool enableClusterLoads() const { return false; } 636 637 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt, 638 MachineInstr *SecondLdSt, 639 unsigned NumLoads) const { 640 return false; 641 } 642 643 /// \brief Can this target fuse the given instructions if they are scheduled 644 /// adjacent. 645 virtual bool shouldScheduleAdjacent(MachineInstr* First, 646 MachineInstr *Second) const { 647 return false; 648 } 649 650 /// ReverseBranchCondition - Reverses the branch condition of the specified 651 /// condition list, returning false on success and true if it cannot be 652 /// reversed. 653 virtual 654 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 655 return true; 656 } 657 658 /// insertNoop - Insert a noop into the instruction stream at the specified 659 /// point. 660 virtual void insertNoop(MachineBasicBlock &MBB, 661 MachineBasicBlock::iterator MI) const; 662 663 664 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 665 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 666 // Default to just using 'nop' string. 667 } 668 669 670 /// isPredicated - Returns true if the instruction is already predicated. 671 /// 672 virtual bool isPredicated(const MachineInstr *MI) const { 673 return false; 674 } 675 676 /// isUnpredicatedTerminator - Returns true if the instruction is a 677 /// terminator instruction that has not been predicated. 678 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 679 680 /// PredicateInstruction - Convert the instruction into a predicated 681 /// instruction. It returns true if the operation was successful. 682 virtual 683 bool PredicateInstruction(MachineInstr *MI, 684 const SmallVectorImpl<MachineOperand> &Pred) const; 685 686 /// SubsumesPredicate - Returns true if the first specified predicate 687 /// subsumes the second, e.g. GE subsumes GT. 688 virtual 689 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 690 const SmallVectorImpl<MachineOperand> &Pred2) const { 691 return false; 692 } 693 694 /// DefinesPredicate - If the specified instruction defines any predicate 695 /// or condition code register(s) used for predication, returns true as well 696 /// as the definition predicate(s) by reference. 697 virtual bool DefinesPredicate(MachineInstr *MI, 698 std::vector<MachineOperand> &Pred) const { 699 return false; 700 } 701 702 /// isPredicable - Return true if the specified instruction can be predicated. 703 /// By default, this returns true for every instruction with a 704 /// PredicateOperand. 705 virtual bool isPredicable(MachineInstr *MI) const { 706 return MI->getDesc().isPredicable(); 707 } 708 709 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 710 /// instruction that defines the specified register class. 711 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 712 return true; 713 } 714 715 /// isSchedulingBoundary - Test if the given instruction should be 716 /// considered a scheduling boundary. This primarily includes labels and 717 /// terminators. 718 virtual bool isSchedulingBoundary(const MachineInstr *MI, 719 const MachineBasicBlock *MBB, 720 const MachineFunction &MF) const; 721 722 /// Measure the specified inline asm to determine an approximation of its 723 /// length. 724 virtual unsigned getInlineAsmLength(const char *Str, 725 const MCAsmInfo &MAI) const; 726 727 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 728 /// use for this target when scheduling the machine instructions before 729 /// register allocation. 730 virtual ScheduleHazardRecognizer* 731 CreateTargetHazardRecognizer(const TargetMachine *TM, 732 const ScheduleDAG *DAG) const; 733 734 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer 735 /// to use for this target when scheduling the machine instructions before 736 /// register allocation. 737 virtual ScheduleHazardRecognizer* 738 CreateTargetMIHazardRecognizer(const InstrItineraryData*, 739 const ScheduleDAG *DAG) const; 740 741 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 742 /// recognizer to use for this target when scheduling the machine instructions 743 /// after register allocation. 744 virtual ScheduleHazardRecognizer* 745 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 746 const ScheduleDAG *DAG) const; 747 748 /// Provide a global flag for disabling the PreRA hazard recognizer that 749 /// targets may choose to honor. 750 bool usePreRAHazardRecognizer() const; 751 752 /// analyzeCompare - For a comparison instruction, return the source registers 753 /// in SrcReg and SrcReg2 if having two register operands, and the value it 754 /// compares against in CmpValue. Return true if the comparison instruction 755 /// can be analyzed. 756 virtual bool analyzeCompare(const MachineInstr *MI, 757 unsigned &SrcReg, unsigned &SrcReg2, 758 int &Mask, int &Value) const { 759 return false; 760 } 761 762 /// optimizeCompareInstr - See if the comparison instruction can be converted 763 /// into something more efficient. E.g., on ARM most instructions can set the 764 /// flags register, obviating the need for a separate CMP. 765 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 766 unsigned SrcReg, unsigned SrcReg2, 767 int Mask, int Value, 768 const MachineRegisterInfo *MRI) const { 769 return false; 770 } 771 772 /// optimizeLoadInstr - Try to remove the load by folding it to a register 773 /// operand at the use. We fold the load instructions if and only if the 774 /// def and use are in the same BB. We only look at one load and see 775 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 776 /// defined by the load we are trying to fold. DefMI returns the machine 777 /// instruction that defines FoldAsLoadDefReg, and the function returns 778 /// the machine instruction generated due to folding. 779 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI, 780 const MachineRegisterInfo *MRI, 781 unsigned &FoldAsLoadDefReg, 782 MachineInstr *&DefMI) const { 783 return nullptr; 784 } 785 786 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 787 /// instruction, try to fold the immediate into the use instruction. 788 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 789 /// then the caller may assume that DefMI has been erased from its parent 790 /// block. The caller may assume that it will not be erased by this 791 /// function otherwise. 792 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 793 unsigned Reg, MachineRegisterInfo *MRI) const { 794 return false; 795 } 796 797 /// getNumMicroOps - Return the number of u-operations the given machine 798 /// instruction will be decoded to on the target cpu. The itinerary's 799 /// IssueWidth is the number of microops that can be dispatched each 800 /// cycle. An instruction with zero microops takes no dispatch resources. 801 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 802 const MachineInstr *MI) const; 803 804 /// isZeroCost - Return true for pseudo instructions that don't consume any 805 /// machine resources in their current form. These are common cases that the 806 /// scheduler should consider free, rather than conservatively handling them 807 /// as instructions with no itinerary. 808 bool isZeroCost(unsigned Opcode) const { 809 return Opcode <= TargetOpcode::COPY; 810 } 811 812 virtual int getOperandLatency(const InstrItineraryData *ItinData, 813 SDNode *DefNode, unsigned DefIdx, 814 SDNode *UseNode, unsigned UseIdx) const; 815 816 /// getOperandLatency - Compute and return the use operand latency of a given 817 /// pair of def and use. 818 /// In most cases, the static scheduling itinerary was enough to determine the 819 /// operand latency. But it may not be possible for instructions with variable 820 /// number of defs / uses. 821 /// 822 /// This is a raw interface to the itinerary that may be directly overriden by 823 /// a target. Use computeOperandLatency to get the best estimate of latency. 824 virtual int getOperandLatency(const InstrItineraryData *ItinData, 825 const MachineInstr *DefMI, unsigned DefIdx, 826 const MachineInstr *UseMI, 827 unsigned UseIdx) const; 828 829 /// computeOperandLatency - Compute and return the latency of the given data 830 /// dependent def and use when the operand indices are already known. 831 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 832 const MachineInstr *DefMI, unsigned DefIdx, 833 const MachineInstr *UseMI, unsigned UseIdx) 834 const; 835 836 /// getInstrLatency - Compute the instruction latency of a given instruction. 837 /// If the instruction has higher cost when predicated, it's returned via 838 /// PredCost. 839 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 840 const MachineInstr *MI, 841 unsigned *PredCost = nullptr) const; 842 843 virtual unsigned getPredicationCost(const MachineInstr *MI) const; 844 845 virtual int getInstrLatency(const InstrItineraryData *ItinData, 846 SDNode *Node) const; 847 848 /// Return the default expected latency for a def based on it's opcode. 849 unsigned defaultDefLatency(const MCSchedModel *SchedModel, 850 const MachineInstr *DefMI) const; 851 852 int computeDefOperandLatency(const InstrItineraryData *ItinData, 853 const MachineInstr *DefMI) const; 854 855 /// isHighLatencyDef - Return true if this opcode has high latency to its 856 /// result. 857 virtual bool isHighLatencyDef(int opc) const { return false; } 858 859 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 860 /// and an use in the current loop, return true if the target considered 861 /// it 'high'. This is used by optimization passes such as machine LICM to 862 /// determine whether it makes sense to hoist an instruction out even in 863 /// high register pressure situation. 864 virtual 865 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 866 const MachineRegisterInfo *MRI, 867 const MachineInstr *DefMI, unsigned DefIdx, 868 const MachineInstr *UseMI, unsigned UseIdx) const { 869 return false; 870 } 871 872 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 873 /// if the target considered it 'low'. 874 virtual 875 bool hasLowDefLatency(const InstrItineraryData *ItinData, 876 const MachineInstr *DefMI, unsigned DefIdx) const; 877 878 /// verifyInstruction - Perform target specific instruction verification. 879 virtual 880 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { 881 return true; 882 } 883 884 /// getExecutionDomain - Return the current execution domain and bit mask of 885 /// possible domains for instruction. 886 /// 887 /// Some micro-architectures have multiple execution domains, and multiple 888 /// opcodes that perform the same operation in different domains. For 889 /// example, the x86 architecture provides the por, orps, and orpd 890 /// instructions that all do the same thing. There is a latency penalty if a 891 /// register is written in one domain and read in another. 892 /// 893 /// This function returns a pair (domain, mask) containing the execution 894 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 895 /// function can be used to change the opcode to one of the domains in the 896 /// bit mask. Instructions whose execution domain can't be changed should 897 /// return a 0 mask. 898 /// 899 /// The execution domain numbers don't have any special meaning except domain 900 /// 0 is used for instructions that are not associated with any interesting 901 /// execution domain. 902 /// 903 virtual std::pair<uint16_t, uint16_t> 904 getExecutionDomain(const MachineInstr *MI) const { 905 return std::make_pair(0, 0); 906 } 907 908 /// setExecutionDomain - Change the opcode of MI to execute in Domain. 909 /// 910 /// The bit (1 << Domain) must be set in the mask returned from 911 /// getExecutionDomain(MI). 912 /// 913 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} 914 915 916 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance 917 /// before an instruction with an unwanted partial register update. 918 /// 919 /// Some instructions only write part of a register, and implicitly need to 920 /// read the other parts of the register. This may cause unwanted stalls 921 /// preventing otherwise unrelated instructions from executing in parallel in 922 /// an out-of-order CPU. 923 /// 924 /// For example, the x86 instruction cvtsi2ss writes its result to bits 925 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 926 /// the instruction needs to wait for the old value of the register to become 927 /// available: 928 /// 929 /// addps %xmm1, %xmm0 930 /// movaps %xmm0, (%rax) 931 /// cvtsi2ss %rbx, %xmm0 932 /// 933 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 934 /// instruction before it can issue, even though the high bits of %xmm0 935 /// probably aren't needed. 936 /// 937 /// This hook returns the preferred clearance before MI, measured in 938 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 939 /// instructions before MI. It should only return a positive value for 940 /// unwanted dependencies. If the old bits of the defined register have 941 /// useful values, or if MI is determined to otherwise read the dependency, 942 /// the hook should return 0. 943 /// 944 /// The unwanted dependency may be handled by: 945 /// 946 /// 1. Allocating the same register for an MI def and use. That makes the 947 /// unwanted dependency identical to a required dependency. 948 /// 949 /// 2. Allocating a register for the def that has no defs in the previous N 950 /// instructions. 951 /// 952 /// 3. Calling breakPartialRegDependency() with the same arguments. This 953 /// allows the target to insert a dependency breaking instruction. 954 /// 955 virtual unsigned 956 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 957 const TargetRegisterInfo *TRI) const { 958 // The default implementation returns 0 for no partial register dependency. 959 return 0; 960 } 961 962 /// \brief Return the minimum clearance before an instruction that reads an 963 /// unused register. 964 /// 965 /// For example, AVX instructions may copy part of an register operand into 966 /// the unused high bits of the destination register. 967 /// 968 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 969 /// 970 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a 971 /// false dependence on any previous write to %xmm0. 972 /// 973 /// This hook works similarly to getPartialRegUpdateClearance, except that it 974 /// does not take an operand index. Instead sets \p OpNum to the index of the 975 /// unused register. 976 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 977 const TargetRegisterInfo *TRI) const { 978 // The default implementation returns 0 for no undef register dependency. 979 return 0; 980 } 981 982 /// breakPartialRegDependency - Insert a dependency-breaking instruction 983 /// before MI to eliminate an unwanted dependency on OpNum. 984 /// 985 /// If it wasn't possible to avoid a def in the last N instructions before MI 986 /// (see getPartialRegUpdateClearance), this hook will be called to break the 987 /// unwanted dependency. 988 /// 989 /// On x86, an xorps instruction can be used as a dependency breaker: 990 /// 991 /// addps %xmm1, %xmm0 992 /// movaps %xmm0, (%rax) 993 /// xorps %xmm0, %xmm0 994 /// cvtsi2ss %rbx, %xmm0 995 /// 996 /// An <imp-kill> operand should be added to MI if an instruction was 997 /// inserted. This ties the instructions together in the post-ra scheduler. 998 /// 999 virtual void 1000 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 1001 const TargetRegisterInfo *TRI) const {} 1002 1003 /// Create machine specific model for scheduling. 1004 virtual DFAPacketizer* 1005 CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const { 1006 return nullptr; 1007 } 1008 1009private: 1010 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 1011}; 1012 1013} // End llvm namespace 1014 1015#endif 1016