TargetInstrInfo.h revision e05442d50806e2850eae1571958816028093df85
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class CalleeSavedInfo; 23class InstrItineraryData; 24class LiveVariables; 25class MCAsmInfo; 26class MachineMemOperand; 27class MDNode; 28class MCInst; 29class SDNode; 30class ScheduleHazardRecognizer; 31class SelectionDAG; 32class TargetRegisterClass; 33class TargetRegisterInfo; 34 35template<class T> class SmallVectorImpl; 36 37 38//--------------------------------------------------------------------------- 39/// 40/// TargetInstrInfo - Interface to description of machine instruction set 41/// 42class TargetInstrInfo { 43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 44 unsigned NumOpcodes; // Number of entries in the desc array 45 46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 48public: 49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 50 virtual ~TargetInstrInfo(); 51 52 unsigned getNumOpcodes() const { return NumOpcodes; } 53 54 /// get - Return the machine instruction descriptor that corresponds to the 55 /// specified instruction opcode. 56 /// 57 const TargetInstrDesc &get(unsigned Opcode) const { 58 assert(Opcode < NumOpcodes && "Invalid opcode!"); 59 return Descriptors[Opcode]; 60 } 61 62 /// isTriviallyReMaterializable - Return true if the instruction is trivially 63 /// rematerializable, meaning it has no side effects and requires no operands 64 /// that aren't always available. 65 bool isTriviallyReMaterializable(const MachineInstr *MI, 66 AliasAnalysis *AA = 0) const { 67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 68 (MI->getDesc().isRematerializable() && 69 (isReallyTriviallyReMaterializable(MI, AA) || 70 isReallyTriviallyReMaterializableGeneric(MI, AA))); 71 } 72 73protected: 74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 75 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 76 /// specify whether the instruction is actually trivially rematerializable, 77 /// taking into consideration its operands. This predicate must return false 78 /// if the instruction has any side effects other than producing a value, or 79 /// if it requres any address registers that are not always available. 80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 81 AliasAnalysis *AA) const { 82 return false; 83 } 84 85private: 86 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 87 /// for which the M_REMATERIALIZABLE flag is set and the target hook 88 /// isReallyTriviallyReMaterializable returns false, this function does 89 /// target-independent tests to determine if the instruction is really 90 /// trivially rematerializable. 91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 92 AliasAnalysis *AA) const; 93 94public: 95 /// isMoveInstr - Return true if the instruction is a register to register 96 /// move and return the source and dest operands and their sub-register 97 /// indices by reference. 98 virtual bool isMoveInstr(const MachineInstr& MI, 99 unsigned& SrcReg, unsigned& DstReg, 100 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 101 return false; 102 } 103 104 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 105 /// extension instruction. That is, it's like a copy where it's legal for the 106 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 107 /// true, then it's expected the pre-extension value is available as a subreg 108 /// of the result register. This also returns the sub-register index in 109 /// SubIdx. 110 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 111 unsigned &SrcReg, unsigned &DstReg, 112 unsigned &SubIdx) const { 113 return false; 114 } 115 116 /// isIdentityCopy - Return true if the instruction is a copy (or 117 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 118 /// destination registers are the same. 119 bool isIdentityCopy(const MachineInstr &MI) const { 120 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 121 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 122 SrcReg == DstReg) 123 return true; 124 125 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG || 126 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) && 127 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 128 return true; 129 return false; 130 } 131 132 /// isLoadFromStackSlot - If the specified machine instruction is a direct 133 /// load from a stack slot, return the virtual or physical register number of 134 /// the destination along with the FrameIndex of the loaded stack slot. If 135 /// not, return 0. This predicate must return 0 if the instruction has 136 /// any side effects other than loading from the stack slot. 137 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 138 int &FrameIndex) const { 139 return 0; 140 } 141 142 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 143 /// stack locations as well. This uses a heuristic so it isn't 144 /// reliable for correctness. 145 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 146 int &FrameIndex) const { 147 return 0; 148 } 149 150 /// hasLoadFromStackSlot - If the specified machine instruction has 151 /// a load from a stack slot, return true along with the FrameIndex 152 /// of the loaded stack slot and the machine mem operand containing 153 /// the reference. If not, return false. Unlike 154 /// isLoadFromStackSlot, this returns true for any instructions that 155 /// loads from the stack. This is just a hint, as some cases may be 156 /// missed. 157 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 158 const MachineMemOperand *&MMO, 159 int &FrameIndex) const { 160 return 0; 161 } 162 163 /// isStoreToStackSlot - If the specified machine instruction is a direct 164 /// store to a stack slot, return the virtual or physical register number of 165 /// the source reg along with the FrameIndex of the loaded stack slot. If 166 /// not, return 0. This predicate must return 0 if the instruction has 167 /// any side effects other than storing to the stack slot. 168 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 169 int &FrameIndex) const { 170 return 0; 171 } 172 173 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 174 /// stack locations as well. This uses a heuristic so it isn't 175 /// reliable for correctness. 176 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 177 int &FrameIndex) const { 178 return 0; 179 } 180 181 /// hasStoreToStackSlot - If the specified machine instruction has a 182 /// store to a stack slot, return true along with the FrameIndex of 183 /// the loaded stack slot and the machine mem operand containing the 184 /// reference. If not, return false. Unlike isStoreToStackSlot, 185 /// this returns true for any instructions that stores to the 186 /// stack. This is just a hint, as some cases may be missed. 187 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 188 const MachineMemOperand *&MMO, 189 int &FrameIndex) const { 190 return 0; 191 } 192 193 /// reMaterialize - Re-issue the specified 'original' instruction at the 194 /// specific location targeting a new destination register. 195 /// The register in Orig->getOperand(0).getReg() will be substituted by 196 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 197 /// SubIdx. 198 virtual void reMaterialize(MachineBasicBlock &MBB, 199 MachineBasicBlock::iterator MI, 200 unsigned DestReg, unsigned SubIdx, 201 const MachineInstr *Orig, 202 const TargetRegisterInfo &TRI) const = 0; 203 204 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 205 /// two-addrss instruction inserted by two-address pass. 206 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 207 MachineInstr *UseMI, 208 const TargetRegisterInfo &TRI) const { 209 // Do nothing. 210 } 211 212 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 213 /// MachineFunction::CloneMachineInstr(), but the target may update operands 214 /// that are required to be unique. 215 /// 216 /// The instruction must be duplicable as indicated by isNotDuplicable(). 217 virtual MachineInstr *duplicate(MachineInstr *Orig, 218 MachineFunction &MF) const = 0; 219 220 /// convertToThreeAddress - This method must be implemented by targets that 221 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 222 /// may be able to convert a two-address instruction into one or more true 223 /// three-address instructions on demand. This allows the X86 target (for 224 /// example) to convert ADD and SHL instructions into LEA instructions if they 225 /// would require register copies due to two-addressness. 226 /// 227 /// This method returns a null pointer if the transformation cannot be 228 /// performed, otherwise it returns the last new instruction. 229 /// 230 virtual MachineInstr * 231 convertToThreeAddress(MachineFunction::iterator &MFI, 232 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 233 return 0; 234 } 235 236 /// commuteInstruction - If a target has any instructions that are 237 /// commutable but require converting to different instructions or making 238 /// non-trivial changes to commute them, this method can overloaded to do 239 /// that. The default implementation simply swaps the commutable operands. 240 /// If NewMI is false, MI is modified in place and returned; otherwise, a 241 /// new machine instruction is created and returned. Do not call this 242 /// method for a non-commutable instruction, but there may be some cases 243 /// where this method fails and returns null. 244 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 245 bool NewMI = false) const = 0; 246 247 /// findCommutedOpIndices - If specified MI is commutable, return the two 248 /// operand indices that would swap value. Return false if the instruction 249 /// is not in a form which this routine understands. 250 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 251 unsigned &SrcOpIdx2) const = 0; 252 253 /// produceSameValue - Return true if two machine instructions would produce 254 /// identical values. By default, this is only true when the two instructions 255 /// are deemed identical except for defs. 256 virtual bool produceSameValue(const MachineInstr *MI0, 257 const MachineInstr *MI1) const = 0; 258 259 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 260 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 261 /// implemented for a target). Upon success, this returns false and returns 262 /// with the following information in various cases: 263 /// 264 /// 1. If this block ends with no branches (it just falls through to its succ) 265 /// just return false, leaving TBB/FBB null. 266 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 267 /// the destination block. 268 /// 3. If this block ends with a conditional branch and it falls through to a 269 /// successor block, it sets TBB to be the branch destination block and a 270 /// list of operands that evaluate the condition. These operands can be 271 /// passed to other TargetInstrInfo methods to create new branches. 272 /// 4. If this block ends with a conditional branch followed by an 273 /// unconditional branch, it returns the 'true' destination in TBB, the 274 /// 'false' destination in FBB, and a list of operands that evaluate the 275 /// condition. These operands can be passed to other TargetInstrInfo 276 /// methods to create new branches. 277 /// 278 /// Note that RemoveBranch and InsertBranch must be implemented to support 279 /// cases where this method returns success. 280 /// 281 /// If AllowModify is true, then this routine is allowed to modify the basic 282 /// block (e.g. delete instructions after the unconditional branch). 283 /// 284 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 285 MachineBasicBlock *&FBB, 286 SmallVectorImpl<MachineOperand> &Cond, 287 bool AllowModify = false) const { 288 return true; 289 } 290 291 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 292 /// This is only invoked in cases where AnalyzeBranch returns success. It 293 /// returns the number of instructions that were removed. 294 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 295 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 296 return 0; 297 } 298 299 /// InsertBranch - Insert branch code into the end of the specified 300 /// MachineBasicBlock. The operands to this method are the same as those 301 /// returned by AnalyzeBranch. This is only invoked in cases where 302 /// AnalyzeBranch returns success. It returns the number of instructions 303 /// inserted. 304 /// 305 /// It is also invoked by tail merging to add unconditional branches in 306 /// cases where AnalyzeBranch doesn't apply because there was no original 307 /// branch to analyze. At least this much must be implemented, else tail 308 /// merging needs to be disabled. 309 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 310 MachineBasicBlock *FBB, 311 const SmallVectorImpl<MachineOperand> &Cond, 312 DebugLoc DL) const { 313 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 314 return 0; 315 } 316 317 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 318 /// after it, replacing it with an unconditional branch to NewDest. This is 319 /// used by the tail merging pass. 320 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 321 MachineBasicBlock *NewDest) const = 0; 322 323 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 324 /// block at the specified instruction (i.e. instruction would be the start 325 /// of a new basic block). 326 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 327 MachineBasicBlock::iterator MBBI) const { 328 return true; 329 } 330 331 /// isProfitableToIfCvt - Return true if it's profitable to first "NumInstrs" 332 /// of the specified basic block. 333 virtual 334 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const { 335 return false; 336 } 337 338 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 339 /// checks for the case where two basic blocks from true and false path 340 /// of a if-then-else (diamond) are predicated on mutally exclusive 341 /// predicates. 342 virtual bool 343 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs, 344 MachineBasicBlock &FMBB, unsigned NumFInstrs) const { 345 return false; 346 } 347 348 /// isProfitableToDupForIfCvt - Return true if it's profitable for 349 /// if-converter to duplicate a specific number of instructions in the 350 /// specified MBB to enable if-conversion. 351 virtual bool 352 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs) const { 353 return false; 354 } 355 356 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 357 /// returns false if the target does not how to copy between the specified 358 /// registers. 359 virtual bool copyRegToReg(MachineBasicBlock &MBB, 360 MachineBasicBlock::iterator MI, 361 unsigned DestReg, unsigned SrcReg, 362 const TargetRegisterClass *DestRC, 363 const TargetRegisterClass *SrcRC, 364 DebugLoc DL) const { 365 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 366 return false; 367 } 368 369 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 370 virtual void copyPhysReg(MachineBasicBlock &MBB, 371 MachineBasicBlock::iterator MI, DebugLoc DL, 372 unsigned DestReg, unsigned SrcReg, 373 bool KillSrc) const =0; 374 375 /// storeRegToStackSlot - Store the specified register of the given register 376 /// class to the specified stack frame index. The store instruction is to be 377 /// added to the given machine basic block before the specified machine 378 /// instruction. If isKill is true, the register operand is the last use and 379 /// must be marked kill. 380 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 381 MachineBasicBlock::iterator MI, 382 unsigned SrcReg, bool isKill, int FrameIndex, 383 const TargetRegisterClass *RC, 384 const TargetRegisterInfo *TRI) const { 385 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 386 } 387 388 /// loadRegFromStackSlot - Load the specified register of the given register 389 /// class from the specified stack frame index. The load instruction is to be 390 /// added to the given machine basic block before the specified machine 391 /// instruction. 392 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 393 MachineBasicBlock::iterator MI, 394 unsigned DestReg, int FrameIndex, 395 const TargetRegisterClass *RC, 396 const TargetRegisterInfo *TRI) const { 397 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 398 } 399 400 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 401 /// saved registers and returns true if it isn't possible / profitable to do 402 /// so by issuing a series of store instructions via 403 /// storeRegToStackSlot(). Returns false otherwise. 404 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 405 MachineBasicBlock::iterator MI, 406 const std::vector<CalleeSavedInfo> &CSI, 407 const TargetRegisterInfo *TRI) const { 408 return false; 409 } 410 411 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 412 /// saved registers and returns true if it isn't possible / profitable to do 413 /// so by issuing a series of load instructions via loadRegToStackSlot(). 414 /// Returns false otherwise. 415 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 416 MachineBasicBlock::iterator MI, 417 const std::vector<CalleeSavedInfo> &CSI, 418 const TargetRegisterInfo *TRI) const { 419 return false; 420 } 421 422 /// emitFrameIndexDebugValue - Emit a target-dependent form of 423 /// DBG_VALUE encoding the address of a frame index. Addresses would 424 /// normally be lowered the same way as other addresses on the target, 425 /// e.g. in load instructions. For targets that do not support this 426 /// the debug info is simply lost. 427 /// If you add this for a target you should handle this DBG_VALUE in the 428 /// target-specific AsmPrinter code as well; you will probably get invalid 429 /// assembly output if you don't. 430 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 431 int FrameIx, 432 uint64_t Offset, 433 const MDNode *MDPtr, 434 DebugLoc dl) const { 435 return 0; 436 } 437 438 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 439 /// slot into the specified machine instruction for the specified operand(s). 440 /// If this is possible, a new instruction is returned with the specified 441 /// operand folded, otherwise NULL is returned. 442 /// The new instruction is inserted before MI, and the client is responsible 443 /// for removing the old instruction. 444 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 445 const SmallVectorImpl<unsigned> &Ops, 446 int FrameIndex) const; 447 448 /// foldMemoryOperand - Same as the previous version except it allows folding 449 /// of any load and store from / to any address, not just from a specific 450 /// stack slot. 451 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 452 const SmallVectorImpl<unsigned> &Ops, 453 MachineInstr* LoadMI) const; 454 455protected: 456 /// foldMemoryOperandImpl - Target-dependent implementation for 457 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 458 /// take care of adding a MachineMemOperand to the newly created instruction. 459 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 460 MachineInstr* MI, 461 const SmallVectorImpl<unsigned> &Ops, 462 int FrameIndex) const { 463 return 0; 464 } 465 466 /// foldMemoryOperandImpl - Target-dependent implementation for 467 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 468 /// take care of adding a MachineMemOperand to the newly created instruction. 469 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 470 MachineInstr* MI, 471 const SmallVectorImpl<unsigned> &Ops, 472 MachineInstr* LoadMI) const { 473 return 0; 474 } 475 476public: 477 /// canFoldMemoryOperand - Returns true for the specified load / store if 478 /// folding is possible. 479 virtual 480 bool canFoldMemoryOperand(const MachineInstr *MI, 481 const SmallVectorImpl<unsigned> &Ops) const { 482 return false; 483 } 484 485 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 486 /// a store or a load and a store into two or more instruction. If this is 487 /// possible, returns true as well as the new instructions by reference. 488 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 489 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 490 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 491 return false; 492 } 493 494 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 495 SmallVectorImpl<SDNode*> &NewNodes) const { 496 return false; 497 } 498 499 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 500 /// instruction after load / store are unfolded from an instruction of the 501 /// specified opcode. It returns zero if the specified unfolding is not 502 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 503 /// index of the operand which will hold the register holding the loaded 504 /// value. 505 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 506 bool UnfoldLoad, bool UnfoldStore, 507 unsigned *LoadRegIndex = 0) const { 508 return 0; 509 } 510 511 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 512 /// to determine if two loads are loading from the same base address. It 513 /// should only return true if the base pointers are the same and the 514 /// only differences between the two addresses are the offset. It also returns 515 /// the offsets by reference. 516 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 517 int64_t &Offset1, int64_t &Offset2) const { 518 return false; 519 } 520 521 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 522 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 523 /// be scheduled togther. On some targets if two loads are loading from 524 /// addresses in the same cache line, it's better if they are scheduled 525 /// together. This function takes two integers that represent the load offsets 526 /// from the common base address. It returns true if it decides it's desirable 527 /// to schedule the two loads together. "NumLoads" is the number of loads that 528 /// have already been scheduled after Load1. 529 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 530 int64_t Offset1, int64_t Offset2, 531 unsigned NumLoads) const { 532 return false; 533 } 534 535 /// ReverseBranchCondition - Reverses the branch condition of the specified 536 /// condition list, returning false on success and true if it cannot be 537 /// reversed. 538 virtual 539 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 540 return true; 541 } 542 543 /// insertNoop - Insert a noop into the instruction stream at the specified 544 /// point. 545 virtual void insertNoop(MachineBasicBlock &MBB, 546 MachineBasicBlock::iterator MI) const; 547 548 549 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 550 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 551 // Default to just using 'nop' string. 552 } 553 554 555 /// isPredicated - Returns true if the instruction is already predicated. 556 /// 557 virtual bool isPredicated(const MachineInstr *MI) const { 558 return false; 559 } 560 561 /// isUnpredicatedTerminator - Returns true if the instruction is a 562 /// terminator instruction that has not been predicated. 563 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 564 565 /// PredicateInstruction - Convert the instruction into a predicated 566 /// instruction. It returns true if the operation was successful. 567 virtual 568 bool PredicateInstruction(MachineInstr *MI, 569 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 570 571 /// SubsumesPredicate - Returns true if the first specified predicate 572 /// subsumes the second, e.g. GE subsumes GT. 573 virtual 574 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 575 const SmallVectorImpl<MachineOperand> &Pred2) const { 576 return false; 577 } 578 579 /// DefinesPredicate - If the specified instruction defines any predicate 580 /// or condition code register(s) used for predication, returns true as well 581 /// as the definition predicate(s) by reference. 582 virtual bool DefinesPredicate(MachineInstr *MI, 583 std::vector<MachineOperand> &Pred) const { 584 return false; 585 } 586 587 /// isPredicable - Return true if the specified instruction can be predicated. 588 /// By default, this returns true for every instruction with a 589 /// PredicateOperand. 590 virtual bool isPredicable(MachineInstr *MI) const { 591 return MI->getDesc().isPredicable(); 592 } 593 594 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 595 /// instruction that defines the specified register class. 596 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 597 return true; 598 } 599 600 /// isSchedulingBoundary - Test if the given instruction should be 601 /// considered a scheduling boundary. This primarily includes labels and 602 /// terminators. 603 virtual bool isSchedulingBoundary(const MachineInstr *MI, 604 const MachineBasicBlock *MBB, 605 const MachineFunction &MF) const = 0; 606 607 /// GetInstSize - Returns the size of the specified Instruction. 608 /// 609 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 610 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 611 return 0; 612 } 613 614 /// GetFunctionSizeInBytes - Returns the size of the specified 615 /// MachineFunction. 616 /// 617 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 618 619 /// Measure the specified inline asm to determine an approximation of its 620 /// length. 621 virtual unsigned getInlineAsmLength(const char *Str, 622 const MCAsmInfo &MAI) const; 623 624 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer 625 /// to use for this target when scheduling the machine instructions after 626 /// register allocation. 627 virtual ScheduleHazardRecognizer* 628 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0; 629}; 630 631/// TargetInstrInfoImpl - This is the default implementation of 632/// TargetInstrInfo, which just provides a couple of default implementations 633/// for various methods. This separated out because it is implemented in 634/// libcodegen, not in libtarget. 635class TargetInstrInfoImpl : public TargetInstrInfo { 636protected: 637 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 638 : TargetInstrInfo(desc, NumOpcodes) {} 639public: 640 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 641 MachineBasicBlock *NewDest) const; 642 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 643 bool NewMI = false) const; 644 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 645 unsigned &SrcOpIdx2) const; 646 virtual bool PredicateInstruction(MachineInstr *MI, 647 const SmallVectorImpl<MachineOperand> &Pred) const; 648 virtual void reMaterialize(MachineBasicBlock &MBB, 649 MachineBasicBlock::iterator MI, 650 unsigned DestReg, unsigned SubReg, 651 const MachineInstr *Orig, 652 const TargetRegisterInfo &TRI) const; 653 virtual MachineInstr *duplicate(MachineInstr *Orig, 654 MachineFunction &MF) const; 655 virtual bool produceSameValue(const MachineInstr *MI0, 656 const MachineInstr *MI1) const; 657 virtual bool isSchedulingBoundary(const MachineInstr *MI, 658 const MachineBasicBlock *MBB, 659 const MachineFunction &MF) const; 660 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 661 662 virtual ScheduleHazardRecognizer * 663 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const; 664 virtual void copyPhysReg(MachineBasicBlock &MBB, 665 MachineBasicBlock::iterator MI, DebugLoc DL, 666 unsigned DestReg, unsigned SrcReg, 667 bool KillSrc) const; 668}; 669 670} // End llvm namespace 671 672#endif 673