TargetInstrInfo.h revision f6e8e6bace845cbbb6c1f6d859ffd8a3a154222b
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32class TargetRegisterClass; 33 34//--------------------------------------------------------------------------- 35// Data types used to define information about a single machine instruction 36//--------------------------------------------------------------------------- 37 38typedef short MachineOpCode; 39typedef unsigned InstrSchedClass; 40 41//--------------------------------------------------------------------------- 42// struct TargetInstrDescriptor: 43// Predefined information about each machine instruction. 44// Designed to initialized statically. 45// 46 47const unsigned M_BRANCH_FLAG = 1 << 0; 48const unsigned M_CALL_FLAG = 1 << 1; 49const unsigned M_RET_FLAG = 1 << 2; 50const unsigned M_BARRIER_FLAG = 1 << 3; 51const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 52const unsigned M_LOAD_FLAG = 1 << 5; 53const unsigned M_STORE_FLAG = 1 << 6; 54 55// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 56const unsigned M_2_ADDR_FLAG = 1 << 7; 57 58// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 59// changed into a 3-address instruction if the first two operands cannot be 60// assigned to the same register. The target must implement the 61// TargetInstrInfo::convertToThreeAddress method for this instruction. 62const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8; 63 64// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 65// Z), which produces the same result if Y and Z are exchanged. 66const unsigned M_COMMUTABLE = 1 << 9; 67 68// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 69// block? Typically this is things like return and branch instructions. 70// Various passes use this to insert code into the bottom of a basic block, but 71// before control flow occurs. 72const unsigned M_TERMINATOR_FLAG = 1 << 10; 73 74// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 75// insertion support when the DAG scheduler is inserting it into a machine basic 76// block. 77const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11; 78 79// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 80// operands in addition to the minimum number operands specified. 81const unsigned M_VARIABLE_OPS = 1 << 12; 82 83// M_PREDICATED - Set if this instruction has a predicate that controls its 84// execution. 85const unsigned M_PREDICATED = 1 << 13; 86 87 88// Machine operand flags 89// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 90// requires a callback to look up its register class. 91const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 92 93/// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate 94/// operand that controls an M_PREDICATED instruction. 95const unsigned M_PREDICATE_OPERAND = 1 << 1; 96 97 98/// TargetOperandInfo - This holds information about one operand of a machine 99/// instruction, indicating the register class for register operands, etc. 100/// 101class TargetOperandInfo { 102public: 103 /// RegClass - This specifies the register class enumeration of the operand 104 /// if the operand is a register. If not, this contains 0. 105 unsigned short RegClass; 106 unsigned short Flags; 107 /// Lower 16 bits are used to specify which constraints are set. The higher 16 108 /// bits are used to specify the value of constraints (4 bits each). 109 unsigned int Constraints; 110 /// Currently no other information. 111}; 112 113 114class TargetInstrDescriptor { 115public: 116 const char * Name; // Assembly language mnemonic for the opcode. 117 unsigned numOperands; // Num of args (may be more if variable_ops). 118 InstrSchedClass schedClass; // enum identifying instr sched class 119 unsigned Flags; // flags identifying machine instr class 120 unsigned TSFlags; // Target Specific Flag values 121 const unsigned *ImplicitUses; // Registers implicitly read by this instr 122 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 123 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 124}; 125 126 127//--------------------------------------------------------------------------- 128/// 129/// TargetInstrInfo - Interface to description of machine instructions 130/// 131class TargetInstrInfo { 132 const TargetInstrDescriptor* desc; // raw array to allow static init'n 133 unsigned NumOpcodes; // number of entries in the desc array 134 unsigned numRealOpCodes; // number of non-dummy op codes 135 136 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 137 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 138public: 139 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 140 virtual ~TargetInstrInfo(); 141 142 // Invariant opcodes: All instruction sets have these as their low opcodes. 143 enum { 144 PHI = 0, 145 INLINEASM = 1 146 }; 147 148 unsigned getNumOpcodes() const { return NumOpcodes; } 149 150 /// get - Return the machine instruction descriptor that corresponds to the 151 /// specified instruction opcode. 152 /// 153 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 154 assert((unsigned)Opcode < NumOpcodes); 155 return desc[Opcode]; 156 } 157 158 const char *getName(MachineOpCode Opcode) const { 159 return get(Opcode).Name; 160 } 161 162 int getNumOperands(MachineOpCode Opcode) const { 163 return get(Opcode).numOperands; 164 } 165 166 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 167 return get(Opcode).schedClass; 168 } 169 170 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 171 return get(Opcode).ImplicitUses; 172 } 173 174 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 175 return get(Opcode).ImplicitDefs; 176 } 177 178 179 // 180 // Query instruction class flags according to the machine-independent 181 // flags listed above. 182 // 183 bool isReturn(MachineOpCode Opcode) const { 184 return get(Opcode).Flags & M_RET_FLAG; 185 } 186 187 bool isTwoAddrInstr(MachineOpCode Opcode) const { 188 return get(Opcode).Flags & M_2_ADDR_FLAG; 189 } 190 bool isPredicated(MachineOpCode Opcode) const { 191 return get(Opcode).Flags & M_PREDICATED; 192 } 193 bool isCommutableInstr(MachineOpCode Opcode) const { 194 return get(Opcode).Flags & M_COMMUTABLE; 195 } 196 bool isTerminatorInstr(unsigned Opcode) const { 197 return get(Opcode).Flags & M_TERMINATOR_FLAG; 198 } 199 200 bool isBranch(MachineOpCode Opcode) const { 201 return get(Opcode).Flags & M_BRANCH_FLAG; 202 } 203 204 /// isBarrier - Returns true if the specified instruction stops control flow 205 /// from executing the instruction immediately following it. Examples include 206 /// unconditional branches and return instructions. 207 bool isBarrier(MachineOpCode Opcode) const { 208 return get(Opcode).Flags & M_BARRIER_FLAG; 209 } 210 211 bool isCall(MachineOpCode Opcode) const { 212 return get(Opcode).Flags & M_CALL_FLAG; 213 } 214 bool isLoad(MachineOpCode Opcode) const { 215 return get(Opcode).Flags & M_LOAD_FLAG; 216 } 217 bool isStore(MachineOpCode Opcode) const { 218 return get(Opcode).Flags & M_STORE_FLAG; 219 } 220 221 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 222 /// which must be filled by the code generator. 223 bool hasDelaySlot(unsigned Opcode) const { 224 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 225 } 226 227 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 228 /// custom insertion support when the DAG scheduler is inserting it into a 229 /// machine basic block. 230 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 231 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 232 } 233 234 bool hasVariableOperands(MachineOpCode Opcode) const { 235 return get(Opcode).Flags & M_VARIABLE_OPS; 236 } 237 238 // Operand constraints: only "tied_to" for now. 239 enum OperandConstraint { 240 TIED_TO = 0 // Must be allocated the same register as. 241 }; 242 243 /// getOperandConstraint - Returns the value of the specific constraint if 244 /// it is set. Returns -1 if it is not set. 245 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 246 OperandConstraint Constraint) const { 247 assert(OpNum < get(Opcode).numOperands && 248 "Invalid operand # of TargetInstrInfo"); 249 if (get(Opcode).OpInfo[OpNum].Constraints & (1 << Constraint)) { 250 unsigned Pos = 16 + Constraint * 4; 251 return (int)(get(Opcode).OpInfo[OpNum].Constraints >> Pos) & 0xf; 252 } 253 return -1; 254 } 255 256 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 257 /// dest operand. Returns -1 if there isn't one. 258 int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const; 259 260 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL 261 /// instruction if it has one. This is used by codegen passes that update 262 /// DWARF line number info as they modify the code. 263 virtual unsigned getDWARF_LABELOpcode() const { 264 return 0; 265 } 266 267 /// Return true if the instruction is a register to register move 268 /// and leave the source and dest operands in the passed parameters. 269 virtual bool isMoveInstr(const MachineInstr& MI, 270 unsigned& sourceReg, 271 unsigned& destReg) const { 272 return false; 273 } 274 275 /// isLoadFromStackSlot - If the specified machine instruction is a direct 276 /// load from a stack slot, return the virtual or physical register number of 277 /// the destination along with the FrameIndex of the loaded stack slot. If 278 /// not, return 0. This predicate must return 0 if the instruction has 279 /// any side effects other than loading from the stack slot. 280 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 281 return 0; 282 } 283 284 /// isStoreToStackSlot - If the specified machine instruction is a direct 285 /// store to a stack slot, return the virtual or physical register number of 286 /// the source reg along with the FrameIndex of the loaded stack slot. If 287 /// not, return 0. This predicate must return 0 if the instruction has 288 /// any side effects other than storing to the stack slot. 289 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 290 return 0; 291 } 292 293 /// convertToThreeAddress - This method must be implemented by targets that 294 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 295 /// may be able to convert a two-address instruction into a true 296 /// three-address instruction on demand. This allows the X86 target (for 297 /// example) to convert ADD and SHL instructions into LEA instructions if they 298 /// would require register copies due to two-addressness. 299 /// 300 /// This method returns a null pointer if the transformation cannot be 301 /// performed, otherwise it returns the new instruction. 302 /// 303 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 304 return 0; 305 } 306 307 /// commuteInstruction - If a target has any instructions that are commutable, 308 /// but require converting to a different instruction or making non-trivial 309 /// changes to commute them, this method can overloaded to do this. The 310 /// default implementation of this method simply swaps the first two operands 311 /// of MI and returns it. 312 /// 313 /// If a target wants to make more aggressive changes, they can construct and 314 /// return a new machine instruction. If an instruction cannot commute, it 315 /// can also return null. 316 /// 317 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 318 319 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 320 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 321 /// implemented for a target). Upon success, this returns false and returns 322 /// with the following information in various cases: 323 /// 324 /// 1. If this block ends with no branches (it just falls through to its succ) 325 /// just return false, leaving TBB/FBB null. 326 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 327 /// the destination block. 328 /// 3. If this block ends with an conditional branch, it returns the 'true' 329 /// destination in TBB, the 'false' destination in FBB, and a list of 330 /// operands that evaluate the condition. These operands can be passed to 331 /// other TargetInstrInfo methods to create new branches. 332 /// 333 /// Note that RemoveBranch and InsertBranch must be implemented to support 334 /// cases where this method returns success. 335 /// 336 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 337 MachineBasicBlock *&FBB, 338 std::vector<MachineOperand> &Cond) const { 339 return true; 340 } 341 342 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 343 /// this is only invoked in cases where AnalyzeBranch returns success. 344 virtual void RemoveBranch(MachineBasicBlock &MBB) const { 345 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 346 } 347 348 /// InsertBranch - Insert a branch into the end of the specified 349 /// MachineBasicBlock. This operands to this method are the same as those 350 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 351 /// returns success and when an unconditional branch (TBB is non-null, FBB is 352 /// null, Cond is empty) needs to be inserted. 353 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 354 MachineBasicBlock *FBB, 355 const std::vector<MachineOperand> &Cond) const { 356 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 357 } 358 359 /// BlockHasNoFallThrough - Return true if the specified block does not 360 /// fall-through into its successor block. This is primarily used when a 361 /// branch is unanalyzable. It is useful for things like unconditional 362 /// indirect branches (jump tables). 363 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 364 return false; 365 } 366 367 /// ReverseBranchCondition - Reverses the branch condition of the specified 368 /// condition list, returning false on success and true if it cannot be 369 /// reversed. 370 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 371 return true; 372 } 373 374 /// insertNoop - Insert a noop into the instruction stream at the specified 375 /// point. 376 virtual void insertNoop(MachineBasicBlock &MBB, 377 MachineBasicBlock::iterator MI) const { 378 assert(0 && "Target didn't implement insertNoop!"); 379 abort(); 380 } 381 382 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 383 /// values. 384 virtual const TargetRegisterClass *getPointerRegClass() const { 385 assert(0 && "Target didn't implement getPointerRegClass!"); 386 abort(); 387 } 388}; 389 390} // End llvm namespace 391 392#endif 393