1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65/// with length less that of OtherOp, which is a vector type. 66class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69} 70 71// SDTCVecEltisVT - The specified operand is vector type with element type 72// of VT. 73class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 74 ValueType VT = vt; 75} 76 77// SDTCisSameNumEltsAs - The two specified operands have identical number 78// of elements. 79class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 80 int OtherOperandNum = OtherOp; 81} 82 83// SDTCisSameSizeAs - The two specified operands have identical size. 84class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 85 int OtherOperandNum = OtherOp; 86} 87 88//===----------------------------------------------------------------------===// 89// Selection DAG Type Profile definitions. 90// 91// These use the constraints defined above to describe the type requirements of 92// the various nodes. These are not hard coded into tblgen, allowing targets to 93// add their own if needed. 94// 95 96// SDTypeProfile - This profile describes the type requirements of a Selection 97// DAG node. 98class SDTypeProfile<int numresults, int numoperands, 99 list<SDTypeConstraint> constraints> { 100 int NumResults = numresults; 101 int NumOperands = numoperands; 102 list<SDTypeConstraint> Constraints = constraints; 103} 104 105// Builtin profiles. 106def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 107def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 108def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 109def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 110def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 111def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 112 113def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 114 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 115]>; 116def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 117 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 118]>; 119def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift 120 SDTCisSameAs<0, 1>, SDTCisInt<2> 121]>; 122def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 123 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 124]>; 125 126def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 127 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 128]>; 129def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 130 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 131]>; 132def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 133 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 134]>; 135def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 136 SDTCisSameAs<0, 1>, SDTCisInt<0> 137]>; 138def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 139 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 140]>; 141def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 142 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 143]>; 144def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 145 SDTCisSameAs<0, 1>, SDTCisFP<0> 146]>; 147def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 148 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 149]>; 150def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 151 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 152]>; 153def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 154 SDTCisFP<0>, SDTCisInt<1> 155]>; 156def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 157 SDTCisInt<0>, SDTCisFP<1> 158]>; 159def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 160 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 161 SDTCisVTSmallerThanOp<2, 1> 162]>; 163 164def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 165 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 166]>; 167 168def SDTSelect : SDTypeProfile<1, 3, [ // select 169 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 170]>; 171 172def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 173 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1> 174]>; 175 176def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 177 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 178 SDTCisVT<5, OtherVT> 179]>; 180 181def SDTBr : SDTypeProfile<0, 1, [ // br 182 SDTCisVT<0, OtherVT> 183]>; 184 185def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 186 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 187]>; 188 189def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 190 SDTCisInt<0>, SDTCisVT<1, OtherVT> 191]>; 192 193def SDTBrind : SDTypeProfile<0, 1, [ // brind 194 SDTCisPtrTy<0> 195]>; 196 197def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 198 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 199]>; 200 201def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 202 203def SDTLoad : SDTypeProfile<1, 1, [ // load 204 SDTCisPtrTy<1> 205]>; 206 207def SDTStore : SDTypeProfile<0, 2, [ // store 208 SDTCisPtrTy<1> 209]>; 210 211def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 212 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 213]>; 214 215def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store 216 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2> 217]>; 218 219def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load 220 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 221 SDTCisSameNumEltsAs<0, 2> 222]>; 223 224def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather 225 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>, 226 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1> 227]>; 228 229def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter 230 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>, 231 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3> 232]>; 233 234def SDTVecShuffle : SDTypeProfile<1, 2, [ 235 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 236]>; 237def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 238 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 239]>; 240def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 241 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 242]>; 243 244def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 245 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 246]>; 247def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 248 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 249]>; 250 251def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 252 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 253]>; 254 255def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier 256 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 257 SDTCisInt<0> 258]>; 259def SDTAtomicFence : SDTypeProfile<0, 2, [ 260 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 261]>; 262def SDTAtomic3 : SDTypeProfile<1, 3, [ 263 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 264]>; 265def SDTAtomic2 : SDTypeProfile<1, 2, [ 266 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 267]>; 268def SDTAtomicStore : SDTypeProfile<0, 2, [ 269 SDTCisPtrTy<0>, SDTCisInt<1> 270]>; 271def SDTAtomicLoad : SDTypeProfile<1, 1, [ 272 SDTCisInt<0>, SDTCisPtrTy<1> 273]>; 274 275def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 276 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 277]>; 278 279class SDCallSeqStart<list<SDTypeConstraint> constraints> : 280 SDTypeProfile<0, 1, constraints>; 281class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 282 SDTypeProfile<0, 2, constraints>; 283 284//===----------------------------------------------------------------------===// 285// Selection DAG Node Properties. 286// 287// Note: These are hard coded into tblgen. 288// 289class SDNodeProperty; 290def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 291def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 292def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 293def SDNPOutGlue : SDNodeProperty; // Write a flag result 294def SDNPInGlue : SDNodeProperty; // Read a flag operand 295def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 296def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 297def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 298def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 299def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 300def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 301def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 302def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 303 304//===----------------------------------------------------------------------===// 305// Selection DAG Pattern Operations 306class SDPatternOperator { 307 list<SDNodeProperty> Properties = []; 308} 309 310//===----------------------------------------------------------------------===// 311// Selection DAG Node definitions. 312// 313class SDNode<string opcode, SDTypeProfile typeprof, 314 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 315 : SDPatternOperator { 316 string Opcode = opcode; 317 string SDClass = sdclass; 318 let Properties = props; 319 SDTypeProfile TypeProfile = typeprof; 320} 321 322// Special TableGen-recognized dag nodes 323def set; 324def implicit; 325def node; 326def srcvalue; 327 328def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 329def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 330def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 331def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 332def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 333def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 334def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 335def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 336 "GlobalAddressSDNode">; 337def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 338 "GlobalAddressSDNode">; 339def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 340 "GlobalAddressSDNode">; 341def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 342 "GlobalAddressSDNode">; 343def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 344 "ConstantPoolSDNode">; 345def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 346 "ConstantPoolSDNode">; 347def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 348 "JumpTableSDNode">; 349def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 350 "JumpTableSDNode">; 351def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 352 "FrameIndexSDNode">; 353def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 354 "FrameIndexSDNode">; 355def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 356 "ExternalSymbolSDNode">; 357def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 358 "ExternalSymbolSDNode">; 359def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 360def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 361 "BlockAddressSDNode">; 362def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 363 "BlockAddressSDNode">; 364 365def add : SDNode<"ISD::ADD" , SDTIntBinOp , 366 [SDNPCommutative, SDNPAssociative]>; 367def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 368def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 369 [SDNPCommutative, SDNPAssociative]>; 370def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 371def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 372def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 373def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 374def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 375def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 376def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 377def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 378def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 379def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 380def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 381def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 382def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 383def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 384def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 385def and : SDNode<"ISD::AND" , SDTIntBinOp, 386 [SDNPCommutative, SDNPAssociative]>; 387def or : SDNode<"ISD::OR" , SDTIntBinOp, 388 [SDNPCommutative, SDNPAssociative]>; 389def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 390 [SDNPCommutative, SDNPAssociative]>; 391def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 392 [SDNPCommutative, SDNPOutGlue]>; 393def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 394 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 395def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 396 [SDNPOutGlue]>; 397def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 398 [SDNPOutGlue, SDNPInGlue]>; 399def smin : SDNode<"ISD::SMIN" , SDTIntBinOp, 400 [SDNPCommutative, SDNPAssociative]>; 401def smax : SDNode<"ISD::SMAX" , SDTIntBinOp, 402 [SDNPCommutative, SDNPAssociative]>; 403def umin : SDNode<"ISD::UMIN" , SDTIntBinOp, 404 [SDNPCommutative, SDNPAssociative]>; 405def umax : SDNode<"ISD::UMAX" , SDTIntBinOp, 406 [SDNPCommutative, SDNPAssociative]>; 407 408def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 409def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 410def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 411def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 412def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 413def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 414def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>; 415def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>; 416def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 417def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 418def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 419def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 420def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 421def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 422def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 423def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 424 425def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 426def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 427def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 428def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 429def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 430def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 431def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>; 432def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 433def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, 434 [SDNPCommutative, SDNPAssociative]>; 435def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, 436 [SDNPCommutative, SDNPAssociative]>; 437def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>; 438def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>; 439def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 440def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; 441def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 442def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 443def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 444def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 445def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 446def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 447def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 448def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 449def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 450def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 451def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 452def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 453def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 454 455def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 456def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 457def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 458 459def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 460def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 461def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 462def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 463def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 464def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 465 466def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 467def select : SDNode<"ISD::SELECT" , SDTSelect>; 468def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 469def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 470 471def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 472def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 473def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 474def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 475def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 476 [SDNPHasChain, SDNPSideEffect]>; 477def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 478def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone, 479 [SDNPHasChain, SDNPSideEffect]>; 480 481def trap : SDNode<"ISD::TRAP" , SDTNone, 482 [SDNPHasChain, SDNPSideEffect]>; 483def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 484 [SDNPHasChain, SDNPSideEffect]>; 485 486def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 487 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 488 SDNPMemOperand]>; 489 490def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 491 [SDNPHasChain, SDNPSideEffect]>; 492 493def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 494 [SDNPHasChain, SDNPSideEffect]>; 495 496def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 497 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 498def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 499 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 500def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 501 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 502def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 503 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 504def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 505 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 506def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 507 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 508def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 509 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 510def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 511 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 512def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 513 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 514def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 515 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 516def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 517 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 518def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 519 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 520def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 521 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 522def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 523 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 524 525def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore, 526 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 527def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad, 528 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 529def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter, 530 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 531def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather, 532 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 533 534// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 535// and truncst (see below). 536def ld : SDNode<"ISD::LOAD" , SDTLoad, 537 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 538def st : SDNode<"ISD::STORE" , SDTStore, 539 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 540def ist : SDNode<"ISD::STORE" , SDTIStore, 541 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 542 543def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 544def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 545def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 546 []>; 547 548// vector_extract/vector_insert are deprecated. extractelt/insertelt 549// are preferred. 550def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 551 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 552def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 553 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 554def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 555 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 556 557// This operator does not do subvector type checking. The ARM 558// backend, at least, needs it. 559def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 560 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 561 []>; 562 563// This operator does subvector type checking. 564def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 565def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 566 567// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 568// these internally. Don't reference these directly. 569def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 570 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 571 [SDNPHasChain]>; 572def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 573 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 574 [SDNPHasChain]>; 575def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 576 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 577 578// Do not use cvt directly. Use cvt forms below 579def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 580 581def SDT_assertext : SDTypeProfile<1, 1, 582 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 583def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>; 584def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>; 585 586 587//===----------------------------------------------------------------------===// 588// Selection DAG Condition Codes 589 590class CondCode; // ISD::CondCode enums 591def SETOEQ : CondCode; def SETOGT : CondCode; 592def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 593def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 594def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 595def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 596 597def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 598def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 599 600 601//===----------------------------------------------------------------------===// 602// Selection DAG Node Transformation Functions. 603// 604// This mechanism allows targets to manipulate nodes in the output DAG once a 605// match has been formed. This is typically used to manipulate immediate 606// values. 607// 608class SDNodeXForm<SDNode opc, code xformFunction> { 609 SDNode Opcode = opc; 610 code XFormFunction = xformFunction; 611} 612 613def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 614 615//===----------------------------------------------------------------------===// 616// PatPred Subclasses. 617// 618// These allow specifying different sorts of predicates that control whether a 619// node is matched. 620// 621class PatPred; 622 623class CodePatPred<code predicate> : PatPred { 624 code PredicateCode = predicate; 625} 626 627 628//===----------------------------------------------------------------------===// 629// Selection DAG Pattern Fragments. 630// 631// Pattern fragments are reusable chunks of dags that match specific things. 632// They can take arguments and have C++ predicates that control whether they 633// match. They are intended to make the patterns for common instructions more 634// compact and readable. 635// 636 637/// PatFrag - Represents a pattern fragment. This can match something on the 638/// DAG, from a single node to multiple nested other fragments. 639/// 640class PatFrag<dag ops, dag frag, code pred = [{}], 641 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 642 dag Operands = ops; 643 dag Fragment = frag; 644 code PredicateCode = pred; 645 code ImmediateCode = [{}]; 646 SDNodeXForm OperandTransform = xform; 647} 648 649// OutPatFrag is a pattern fragment that is used as part of an output pattern 650// (not an input pattern). These do not have predicates or transforms, but are 651// used to avoid repeated subexpressions in output patterns. 652class OutPatFrag<dag ops, dag frag> 653 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 654 655// PatLeaf's are pattern fragments that have no operands. This is just a helper 656// to define immediates and other common things concisely. 657class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 658 : PatFrag<(ops), frag, pred, xform>; 659 660 661// ImmLeaf is a pattern fragment with a constraint on the immediate. The 662// constraint is a function that is run on the immediate (always with the value 663// sign extended out to an int64_t) as Imm. For example: 664// 665// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 666// 667// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 668// is preferred over using PatLeaf because it allows the code generator to 669// reason more about the constraint. 670// 671// If FastIsel should ignore all instructions that have an operand of this type, 672// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 673// the code size of the generated fast instruction selector. 674class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 675 : PatFrag<(ops), (vt imm), [{}], xform> { 676 let ImmediateCode = pred; 677 bit FastIselShouldIgnore = 0; 678} 679 680 681// Leaf fragments. 682 683def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 684def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 685 686def immAllOnesV: PatLeaf<(build_vector), [{ 687 return ISD::isBuildVectorAllOnes(N); 688}]>; 689def immAllZerosV: PatLeaf<(build_vector), [{ 690 return ISD::isBuildVectorAllZeros(N); 691}]>; 692 693 694 695// Other helper fragments. 696def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 697def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 698def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 699 700// null_frag - The null pattern operator is used in multiclass instantiations 701// which accept an SDPatternOperator for use in matching patterns for internal 702// definitions. When expanding a pattern, if the null fragment is referenced 703// in the expansion, the pattern is discarded and it is as-if '[]' had been 704// specified. This allows multiclasses to have the isel patterns be optional. 705def null_frag : SDPatternOperator; 706 707// load fragments. 708def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 709 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 710}]>; 711def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 712 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 713}]>; 714 715// extending load fragments. 716def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 717 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 718}]>; 719def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 720 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 721}]>; 722def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 723 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 724}]>; 725 726def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 727 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 728}]>; 729def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 730 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 731}]>; 732def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 733 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 734}]>; 735def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 736 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 737}]>; 738def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 739 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 740}]>; 741def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 742 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 743}]>; 744 745def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 746 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 747}]>; 748def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 749 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 750}]>; 751def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 752 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 753}]>; 754def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 755 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 756}]>; 757 758def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 759 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 760}]>; 761def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 762 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 763}]>; 764def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 765 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 766}]>; 767def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 768 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 769}]>; 770 771def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 772 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 773}]>; 774def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 775 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 776}]>; 777def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 778 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 779}]>; 780def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 781 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 782}]>; 783def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 784 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32; 785}]>; 786def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 787 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64; 788}]>; 789 790def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 791 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 792}]>; 793def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 794 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 795}]>; 796def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 797 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 798}]>; 799def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 800 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 801}]>; 802 803def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 804 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 805}]>; 806def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 807 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 808}]>; 809def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 810 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 811}]>; 812def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 813 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 814}]>; 815 816// store fragments. 817def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 818 (st node:$val, node:$ptr), [{ 819 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 820}]>; 821def store : PatFrag<(ops node:$val, node:$ptr), 822 (unindexedstore node:$val, node:$ptr), [{ 823 return !cast<StoreSDNode>(N)->isTruncatingStore(); 824}]>; 825 826// truncstore fragments. 827def truncstore : PatFrag<(ops node:$val, node:$ptr), 828 (unindexedstore node:$val, node:$ptr), [{ 829 return cast<StoreSDNode>(N)->isTruncatingStore(); 830}]>; 831def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 832 (truncstore node:$val, node:$ptr), [{ 833 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 834}]>; 835def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 836 (truncstore node:$val, node:$ptr), [{ 837 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 838}]>; 839def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 840 (truncstore node:$val, node:$ptr), [{ 841 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 842}]>; 843def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 844 (truncstore node:$val, node:$ptr), [{ 845 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 846}]>; 847def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 848 (truncstore node:$val, node:$ptr), [{ 849 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 850}]>; 851 852def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 853 (truncstore node:$val, node:$ptr), [{ 854 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 855}]>; 856 857def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 858 (truncstore node:$val, node:$ptr), [{ 859 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 860}]>; 861 862def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 863 (truncstore node:$val, node:$ptr), [{ 864 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 865}]>; 866 867// indexed store fragments. 868def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 869 (ist node:$val, node:$base, node:$offset), [{ 870 return !cast<StoreSDNode>(N)->isTruncatingStore(); 871}]>; 872 873def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 874 (istore node:$val, node:$base, node:$offset), [{ 875 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 876 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 877}]>; 878 879def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 880 (ist node:$val, node:$base, node:$offset), [{ 881 return cast<StoreSDNode>(N)->isTruncatingStore(); 882}]>; 883def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 884 (itruncstore node:$val, node:$base, node:$offset), [{ 885 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 886 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 887}]>; 888def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 889 (pre_truncst node:$val, node:$base, node:$offset), [{ 890 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 891}]>; 892def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 893 (pre_truncst node:$val, node:$base, node:$offset), [{ 894 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 895}]>; 896def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 897 (pre_truncst node:$val, node:$base, node:$offset), [{ 898 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 899}]>; 900def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 901 (pre_truncst node:$val, node:$base, node:$offset), [{ 902 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 903}]>; 904def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 905 (pre_truncst node:$val, node:$base, node:$offset), [{ 906 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 907}]>; 908 909def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 910 (istore node:$val, node:$ptr, node:$offset), [{ 911 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 912 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 913}]>; 914 915def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 916 (itruncstore node:$val, node:$base, node:$offset), [{ 917 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 918 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 919}]>; 920def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 921 (post_truncst node:$val, node:$base, node:$offset), [{ 922 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 923}]>; 924def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 925 (post_truncst node:$val, node:$base, node:$offset), [{ 926 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 927}]>; 928def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 929 (post_truncst node:$val, node:$base, node:$offset), [{ 930 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 931}]>; 932def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 933 (post_truncst node:$val, node:$base, node:$offset), [{ 934 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 935}]>; 936def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 937 (post_truncst node:$val, node:$base, node:$offset), [{ 938 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 939}]>; 940 941// nontemporal store fragments. 942def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 943 (store node:$val, node:$ptr), [{ 944 return cast<StoreSDNode>(N)->isNonTemporal(); 945}]>; 946 947def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 948 (nontemporalstore node:$val, node:$ptr), [{ 949 StoreSDNode *St = cast<StoreSDNode>(N); 950 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 951}]>; 952 953def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 954 (nontemporalstore node:$val, node:$ptr), [{ 955 StoreSDNode *St = cast<StoreSDNode>(N); 956 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 957}]>; 958 959// nontemporal load fragments. 960def nontemporalload : PatFrag<(ops node:$ptr), 961 (load node:$ptr), [{ 962 return cast<LoadSDNode>(N)->isNonTemporal(); 963}]>; 964 965def alignednontemporalload : PatFrag<(ops node:$ptr), 966 (nontemporalload node:$ptr), [{ 967 LoadSDNode *Ld = cast<LoadSDNode>(N); 968 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 969}]>; 970 971// setcc convenience fragments. 972def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 973 (setcc node:$lhs, node:$rhs, SETOEQ)>; 974def setogt : PatFrag<(ops node:$lhs, node:$rhs), 975 (setcc node:$lhs, node:$rhs, SETOGT)>; 976def setoge : PatFrag<(ops node:$lhs, node:$rhs), 977 (setcc node:$lhs, node:$rhs, SETOGE)>; 978def setolt : PatFrag<(ops node:$lhs, node:$rhs), 979 (setcc node:$lhs, node:$rhs, SETOLT)>; 980def setole : PatFrag<(ops node:$lhs, node:$rhs), 981 (setcc node:$lhs, node:$rhs, SETOLE)>; 982def setone : PatFrag<(ops node:$lhs, node:$rhs), 983 (setcc node:$lhs, node:$rhs, SETONE)>; 984def seto : PatFrag<(ops node:$lhs, node:$rhs), 985 (setcc node:$lhs, node:$rhs, SETO)>; 986def setuo : PatFrag<(ops node:$lhs, node:$rhs), 987 (setcc node:$lhs, node:$rhs, SETUO)>; 988def setueq : PatFrag<(ops node:$lhs, node:$rhs), 989 (setcc node:$lhs, node:$rhs, SETUEQ)>; 990def setugt : PatFrag<(ops node:$lhs, node:$rhs), 991 (setcc node:$lhs, node:$rhs, SETUGT)>; 992def setuge : PatFrag<(ops node:$lhs, node:$rhs), 993 (setcc node:$lhs, node:$rhs, SETUGE)>; 994def setult : PatFrag<(ops node:$lhs, node:$rhs), 995 (setcc node:$lhs, node:$rhs, SETULT)>; 996def setule : PatFrag<(ops node:$lhs, node:$rhs), 997 (setcc node:$lhs, node:$rhs, SETULE)>; 998def setune : PatFrag<(ops node:$lhs, node:$rhs), 999 (setcc node:$lhs, node:$rhs, SETUNE)>; 1000def seteq : PatFrag<(ops node:$lhs, node:$rhs), 1001 (setcc node:$lhs, node:$rhs, SETEQ)>; 1002def setgt : PatFrag<(ops node:$lhs, node:$rhs), 1003 (setcc node:$lhs, node:$rhs, SETGT)>; 1004def setge : PatFrag<(ops node:$lhs, node:$rhs), 1005 (setcc node:$lhs, node:$rhs, SETGE)>; 1006def setlt : PatFrag<(ops node:$lhs, node:$rhs), 1007 (setcc node:$lhs, node:$rhs, SETLT)>; 1008def setle : PatFrag<(ops node:$lhs, node:$rhs), 1009 (setcc node:$lhs, node:$rhs, SETLE)>; 1010def setne : PatFrag<(ops node:$lhs, node:$rhs), 1011 (setcc node:$lhs, node:$rhs, SETNE)>; 1012 1013def atomic_cmp_swap_8 : 1014 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1015 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1016 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1017}]>; 1018def atomic_cmp_swap_16 : 1019 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1020 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1021 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1022}]>; 1023def atomic_cmp_swap_32 : 1024 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1025 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1026 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1027}]>; 1028def atomic_cmp_swap_64 : 1029 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1030 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1031 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1032}]>; 1033 1034multiclass binary_atomic_op<SDNode atomic_op> { 1035 def _8 : PatFrag<(ops node:$ptr, node:$val), 1036 (atomic_op node:$ptr, node:$val), [{ 1037 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1038 }]>; 1039 def _16 : PatFrag<(ops node:$ptr, node:$val), 1040 (atomic_op node:$ptr, node:$val), [{ 1041 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1042 }]>; 1043 def _32 : PatFrag<(ops node:$ptr, node:$val), 1044 (atomic_op node:$ptr, node:$val), [{ 1045 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1046 }]>; 1047 def _64 : PatFrag<(ops node:$ptr, node:$val), 1048 (atomic_op node:$ptr, node:$val), [{ 1049 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1050 }]>; 1051} 1052 1053defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1054defm atomic_swap : binary_atomic_op<atomic_swap>; 1055defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1056defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1057defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1058defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1059defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1060defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1061defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1062defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1063defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1064defm atomic_store : binary_atomic_op<atomic_store>; 1065 1066def atomic_load_8 : 1067 PatFrag<(ops node:$ptr), 1068 (atomic_load node:$ptr), [{ 1069 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1070}]>; 1071def atomic_load_16 : 1072 PatFrag<(ops node:$ptr), 1073 (atomic_load node:$ptr), [{ 1074 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1075}]>; 1076def atomic_load_32 : 1077 PatFrag<(ops node:$ptr), 1078 (atomic_load node:$ptr), [{ 1079 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1080}]>; 1081def atomic_load_64 : 1082 PatFrag<(ops node:$ptr), 1083 (atomic_load node:$ptr), [{ 1084 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1085}]>; 1086 1087//===----------------------------------------------------------------------===// 1088// Selection DAG CONVERT_RNDSAT patterns 1089 1090def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1091 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1092 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 1093 }]>; 1094 1095def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1096 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1097 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 1098 }]>; 1099 1100def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1101 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1102 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 1103 }]>; 1104 1105def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1106 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1107 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 1108 }]>; 1109 1110def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1111 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1112 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 1113 }]>; 1114 1115def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1116 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1117 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 1118 }]>; 1119 1120def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1121 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1122 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 1123 }]>; 1124 1125def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1126 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1127 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 1128 }]>; 1129 1130def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1131 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1132 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 1133 }]>; 1134 1135//===----------------------------------------------------------------------===// 1136// Selection DAG Pattern Support. 1137// 1138// Patterns are what are actually matched against by the target-flavored 1139// instruction selection DAG. Instructions defined by the target implicitly 1140// define patterns in most cases, but patterns can also be explicitly added when 1141// an operation is defined by a sequence of instructions (e.g. loading a large 1142// immediate value on RISC targets that do not support immediates as large as 1143// their GPRs). 1144// 1145 1146class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1147 dag PatternToMatch = patternToMatch; 1148 list<dag> ResultInstrs = resultInstrs; 1149 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1150 int AddedComplexity = 0; // See class Instruction in Target.td. 1151} 1152 1153// Pat - A simple (but common) form of a pattern, which produces a simple result 1154// not needing a full list. 1155class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1156 1157//===----------------------------------------------------------------------===// 1158// Complex pattern definitions. 1159// 1160 1161// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1162// in C++. NumOperands is the number of operands returned by the select function; 1163// SelectFunc is the name of the function used to pattern match the max. pattern; 1164// RootNodes are the list of possible root nodes of the sub-dags to match. 1165// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1166// 1167class ComplexPattern<ValueType ty, int numops, string fn, 1168 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 1169 ValueType Ty = ty; 1170 int NumOperands = numops; 1171 string SelectFunc = fn; 1172 list<SDNode> RootNodes = roots; 1173 list<SDNodeProperty> Properties = props; 1174} 1175