TargetSelectionDAG.td revision 14648468011c92a4210f8118721d58c25043daf8
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65/// with length less that of OtherOp, which is a vector type. 66class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69} 70 71//===----------------------------------------------------------------------===// 72// Selection DAG Type Profile definitions. 73// 74// These use the constraints defined above to describe the type requirements of 75// the various nodes. These are not hard coded into tblgen, allowing targets to 76// add their own if needed. 77// 78 79// SDTypeProfile - This profile describes the type requirements of a Selection 80// DAG node. 81class SDTypeProfile<int numresults, int numoperands, 82 list<SDTypeConstraint> constraints> { 83 int NumResults = numresults; 84 int NumOperands = numoperands; 85 list<SDTypeConstraint> Constraints = constraints; 86} 87 88// Builtin profiles. 89def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 90def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 91def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 92def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 93def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 94def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 95 96def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 98]>; 99def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 101]>; 102def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 104]>; 105 106def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 108]>; 109def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 111]>; 112def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 114]>; 115def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 116 SDTCisSameAs<0, 1>, SDTCisInt<0> 117]>; 118def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 120]>; 121def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 123]>; 124def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 125 SDTCisSameAs<0, 1>, SDTCisFP<0> 126]>; 127def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 129]>; 130def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 132]>; 133def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 134 SDTCisFP<0>, SDTCisInt<1> 135]>; 136def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 137 SDTCisInt<0>, SDTCisFP<1> 138]>; 139def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 141 SDTCisVTSmallerThanOp<2, 1> 142]>; 143 144def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 146]>; 147 148def SDTSelect : SDTypeProfile<1, 3, [ // select 149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 150]>; 151 152def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 153 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 154 SDTCisVT<5, OtherVT> 155]>; 156 157def SDTBr : SDTypeProfile<0, 1, [ // br 158 SDTCisVT<0, OtherVT> 159]>; 160 161def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 162 SDTCisInt<0>, SDTCisVT<1, OtherVT> 163]>; 164 165def SDTBrind : SDTypeProfile<0, 1, [ // brind 166 SDTCisPtrTy<0> 167]>; 168 169def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 170 171def SDTLoad : SDTypeProfile<1, 1, [ // load 172 SDTCisPtrTy<1> 173]>; 174 175def SDTStore : SDTypeProfile<0, 2, [ // store 176 SDTCisPtrTy<1> 177]>; 178 179def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 180 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 181]>; 182 183def SDTVecShuffle : SDTypeProfile<1, 2, [ 184 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 185]>; 186def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 187 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 188]>; 189def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 190 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 191]>; 192 193def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 194 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 195]>; 196def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 197 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 198]>; 199 200def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 201 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 202]>; 203 204def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier 205 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 206 SDTCisInt<0> 207]>; 208def SDTAtomicFence : SDTypeProfile<0, 2, [ 209 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 210]>; 211def SDTAtomic3 : SDTypeProfile<1, 3, [ 212 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 213]>; 214def SDTAtomic2 : SDTypeProfile<1, 2, [ 215 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 216]>; 217 218def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 219 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 220]>; 221 222class SDCallSeqStart<list<SDTypeConstraint> constraints> : 223 SDTypeProfile<0, 1, constraints>; 224class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 225 SDTypeProfile<0, 2, constraints>; 226 227//===----------------------------------------------------------------------===// 228// Selection DAG Node Properties. 229// 230// Note: These are hard coded into tblgen. 231// 232class SDNodeProperty; 233def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 234def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 235def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 236def SDNPOutGlue : SDNodeProperty; // Write a flag result 237def SDNPInGlue : SDNodeProperty; // Read a flag operand 238def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 239def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 240def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 241def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 242def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 243def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 244def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 245def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 246 247//===----------------------------------------------------------------------===// 248// Selection DAG Pattern Operations 249class SDPatternOperator; 250 251//===----------------------------------------------------------------------===// 252// Selection DAG Node definitions. 253// 254class SDNode<string opcode, SDTypeProfile typeprof, 255 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 256 : SDPatternOperator { 257 string Opcode = opcode; 258 string SDClass = sdclass; 259 list<SDNodeProperty> Properties = props; 260 SDTypeProfile TypeProfile = typeprof; 261} 262 263// Special TableGen-recognized dag nodes 264def set; 265def implicit; 266def node; 267def srcvalue; 268 269def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 270def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 271def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 272def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 273def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 274def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 275def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 276def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 277 "GlobalAddressSDNode">; 278def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 279 "GlobalAddressSDNode">; 280def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 281 "GlobalAddressSDNode">; 282def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 283 "GlobalAddressSDNode">; 284def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 285 "ConstantPoolSDNode">; 286def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 287 "ConstantPoolSDNode">; 288def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 289 "JumpTableSDNode">; 290def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 291 "JumpTableSDNode">; 292def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 293 "FrameIndexSDNode">; 294def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 295 "FrameIndexSDNode">; 296def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 297 "ExternalSymbolSDNode">; 298def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 299 "ExternalSymbolSDNode">; 300def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 301 "BlockAddressSDNode">; 302def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 303 "BlockAddressSDNode">; 304 305def add : SDNode<"ISD::ADD" , SDTIntBinOp , 306 [SDNPCommutative, SDNPAssociative]>; 307def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 308def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 309 [SDNPCommutative, SDNPAssociative]>; 310def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 311def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 312def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 313def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 314def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 315def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 316def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 317def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 318def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 319def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 320def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 321def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 322def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 323def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 324def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 325def and : SDNode<"ISD::AND" , SDTIntBinOp, 326 [SDNPCommutative, SDNPAssociative]>; 327def or : SDNode<"ISD::OR" , SDTIntBinOp, 328 [SDNPCommutative, SDNPAssociative]>; 329def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 330 [SDNPCommutative, SDNPAssociative]>; 331def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 332 [SDNPCommutative, SDNPOutGlue]>; 333def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 334 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 335def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 336 [SDNPOutGlue]>; 337def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 338 [SDNPOutGlue, SDNPInGlue]>; 339 340def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 341def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 342def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 343def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 344def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 345def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 346def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 347def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 348def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 349def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 350def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 351def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 352 353 354def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 355def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 356def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 357def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 358def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 359def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 360def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 361def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 362def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 363def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 364def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 365def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 366def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 367def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 368def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 369def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 370def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 371def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 372def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 373 374def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 375def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 376def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 377 378def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 379def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 380def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 381def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 382def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 383def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 384 385def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 386def select : SDNode<"ISD::SELECT" , SDTSelect>; 387def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 388def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 389 390def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 391def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 392def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 393def trap : SDNode<"ISD::TRAP" , SDTNone, 394 [SDNPHasChain, SDNPSideEffect]>; 395 396def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 397 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 398 SDNPMemOperand]>; 399 400def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, 401 [SDNPHasChain, SDNPSideEffect]>; 402 403def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 404 [SDNPHasChain, SDNPSideEffect]>; 405 406def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 407 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 408def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 409 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 410def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 411 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 412def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 413 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 414def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 415 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 416def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 417 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 418def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 419 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 420def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 421 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 422def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 423 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 424def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 425 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 426def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 427 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 428def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 429 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 430 431// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 432// and truncst (see below). 433def ld : SDNode<"ISD::LOAD" , SDTLoad, 434 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 435def st : SDNode<"ISD::STORE" , SDTStore, 436 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 437def ist : SDNode<"ISD::STORE" , SDTIStore, 438 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 439 440def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 441def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 442def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 443 []>; 444def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 445 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 446def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 447 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 448 449// This operator does not do subvector type checking. The ARM 450// backend, at least, needs it. 451def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 452 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 453 []>; 454 455// This operator does subvector type checking. 456def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 457def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 458 459// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 460// these internally. Don't reference these directly. 461def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 462 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 463 [SDNPHasChain]>; 464def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 465 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 466 [SDNPHasChain]>; 467def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 468 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 469 470// Do not use cvt directly. Use cvt forms below 471def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 472 473//===----------------------------------------------------------------------===// 474// Selection DAG Condition Codes 475 476class CondCode; // ISD::CondCode enums 477def SETOEQ : CondCode; def SETOGT : CondCode; 478def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 479def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 480def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 481def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 482 483def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 484def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 485 486 487//===----------------------------------------------------------------------===// 488// Selection DAG Node Transformation Functions. 489// 490// This mechanism allows targets to manipulate nodes in the output DAG once a 491// match has been formed. This is typically used to manipulate immediate 492// values. 493// 494class SDNodeXForm<SDNode opc, code xformFunction> { 495 SDNode Opcode = opc; 496 code XFormFunction = xformFunction; 497} 498 499def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 500 501//===----------------------------------------------------------------------===// 502// PatPred Subclasses. 503// 504// These allow specifying different sorts of predicates that control whether a 505// node is matched. 506// 507class PatPred; 508 509class CodePatPred<code predicate> : PatPred { 510 code PredicateCode = predicate; 511} 512 513 514//===----------------------------------------------------------------------===// 515// Selection DAG Pattern Fragments. 516// 517// Pattern fragments are reusable chunks of dags that match specific things. 518// They can take arguments and have C++ predicates that control whether they 519// match. They are intended to make the patterns for common instructions more 520// compact and readable. 521// 522 523/// PatFrag - Represents a pattern fragment. This can match something on the 524/// DAG, from a single node to multiple nested other fragments. 525/// 526class PatFrag<dag ops, dag frag, code pred = [{}], 527 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 528 dag Operands = ops; 529 dag Fragment = frag; 530 code PredicateCode = pred; 531 code ImmediateCode = [{}]; 532 SDNodeXForm OperandTransform = xform; 533} 534 535// PatLeaf's are pattern fragments that have no operands. This is just a helper 536// to define immediates and other common things concisely. 537class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 538 : PatFrag<(ops), frag, pred, xform>; 539 540 541// ImmLeaf is a pattern fragment with a constraint on the immediate. The 542// constraint is a function that is run on the immediate (always with the value 543// sign extended out to an int64_t) as Imm. For example: 544// 545// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 546// 547// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 548// is preferred over using PatLeaf because it allows the code generator to 549// reason more about the constraint. 550// 551// If FastIsel should ignore all instructions that have an operand of this type, 552// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 553// the code size of the generated fast instruction selector. 554class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 555 : PatFrag<(ops), (vt imm), [{}], xform> { 556 let ImmediateCode = pred; 557 bit FastIselShouldIgnore = 0; 558} 559 560 561// Leaf fragments. 562 563def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 564def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 565 566def immAllOnesV: PatLeaf<(build_vector), [{ 567 return ISD::isBuildVectorAllOnes(N); 568}]>; 569def immAllZerosV: PatLeaf<(build_vector), [{ 570 return ISD::isBuildVectorAllZeros(N); 571}]>; 572 573 574 575// Other helper fragments. 576def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 577def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 578def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 579 580// load fragments. 581def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 582 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 583}]>; 584def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 585 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 586}]>; 587 588// extending load fragments. 589def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 590 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 591}]>; 592def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 593 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 594}]>; 595def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 596 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 597}]>; 598 599def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 600 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 601}]>; 602def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 603 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 604}]>; 605def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 606 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 607}]>; 608def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 609 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 610}]>; 611def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 612 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 613}]>; 614def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 615 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 616}]>; 617 618def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 619 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 620}]>; 621def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 622 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 623}]>; 624def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 625 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 626}]>; 627def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 628 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 629}]>; 630 631def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 632 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 633}]>; 634def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 635 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 636}]>; 637def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 638 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 639}]>; 640def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 641 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 642}]>; 643 644// store fragments. 645def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 646 (st node:$val, node:$ptr), [{ 647 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 648}]>; 649def store : PatFrag<(ops node:$val, node:$ptr), 650 (unindexedstore node:$val, node:$ptr), [{ 651 return !cast<StoreSDNode>(N)->isTruncatingStore(); 652}]>; 653 654// truncstore fragments. 655def truncstore : PatFrag<(ops node:$val, node:$ptr), 656 (unindexedstore node:$val, node:$ptr), [{ 657 return cast<StoreSDNode>(N)->isTruncatingStore(); 658}]>; 659def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 660 (truncstore node:$val, node:$ptr), [{ 661 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 662}]>; 663def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 664 (truncstore node:$val, node:$ptr), [{ 665 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 666}]>; 667def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 668 (truncstore node:$val, node:$ptr), [{ 669 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 670}]>; 671def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 672 (truncstore node:$val, node:$ptr), [{ 673 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 674}]>; 675def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 676 (truncstore node:$val, node:$ptr), [{ 677 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 678}]>; 679 680// indexed store fragments. 681def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 682 (ist node:$val, node:$base, node:$offset), [{ 683 return !cast<StoreSDNode>(N)->isTruncatingStore(); 684}]>; 685 686def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 687 (istore node:$val, node:$base, node:$offset), [{ 688 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 689 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 690}]>; 691 692def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 693 (ist node:$val, node:$base, node:$offset), [{ 694 return cast<StoreSDNode>(N)->isTruncatingStore(); 695}]>; 696def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 697 (itruncstore node:$val, node:$base, node:$offset), [{ 698 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 699 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 700}]>; 701def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 702 (pre_truncst node:$val, node:$base, node:$offset), [{ 703 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 704}]>; 705def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 706 (pre_truncst node:$val, node:$base, node:$offset), [{ 707 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 708}]>; 709def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 710 (pre_truncst node:$val, node:$base, node:$offset), [{ 711 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 712}]>; 713def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 714 (pre_truncst node:$val, node:$base, node:$offset), [{ 715 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 716}]>; 717def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 718 (pre_truncst node:$val, node:$base, node:$offset), [{ 719 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 720}]>; 721 722def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 723 (istore node:$val, node:$ptr, node:$offset), [{ 724 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 725 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 726}]>; 727 728def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 729 (itruncstore node:$val, node:$base, node:$offset), [{ 730 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 731 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 732}]>; 733def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 734 (post_truncst node:$val, node:$base, node:$offset), [{ 735 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 736}]>; 737def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 738 (post_truncst node:$val, node:$base, node:$offset), [{ 739 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 740}]>; 741def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 742 (post_truncst node:$val, node:$base, node:$offset), [{ 743 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 744}]>; 745def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 746 (post_truncst node:$val, node:$base, node:$offset), [{ 747 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 748}]>; 749def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 750 (post_truncst node:$val, node:$base, node:$offset), [{ 751 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 752}]>; 753 754// setcc convenience fragments. 755def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 756 (setcc node:$lhs, node:$rhs, SETOEQ)>; 757def setogt : PatFrag<(ops node:$lhs, node:$rhs), 758 (setcc node:$lhs, node:$rhs, SETOGT)>; 759def setoge : PatFrag<(ops node:$lhs, node:$rhs), 760 (setcc node:$lhs, node:$rhs, SETOGE)>; 761def setolt : PatFrag<(ops node:$lhs, node:$rhs), 762 (setcc node:$lhs, node:$rhs, SETOLT)>; 763def setole : PatFrag<(ops node:$lhs, node:$rhs), 764 (setcc node:$lhs, node:$rhs, SETOLE)>; 765def setone : PatFrag<(ops node:$lhs, node:$rhs), 766 (setcc node:$lhs, node:$rhs, SETONE)>; 767def seto : PatFrag<(ops node:$lhs, node:$rhs), 768 (setcc node:$lhs, node:$rhs, SETO)>; 769def setuo : PatFrag<(ops node:$lhs, node:$rhs), 770 (setcc node:$lhs, node:$rhs, SETUO)>; 771def setueq : PatFrag<(ops node:$lhs, node:$rhs), 772 (setcc node:$lhs, node:$rhs, SETUEQ)>; 773def setugt : PatFrag<(ops node:$lhs, node:$rhs), 774 (setcc node:$lhs, node:$rhs, SETUGT)>; 775def setuge : PatFrag<(ops node:$lhs, node:$rhs), 776 (setcc node:$lhs, node:$rhs, SETUGE)>; 777def setult : PatFrag<(ops node:$lhs, node:$rhs), 778 (setcc node:$lhs, node:$rhs, SETULT)>; 779def setule : PatFrag<(ops node:$lhs, node:$rhs), 780 (setcc node:$lhs, node:$rhs, SETULE)>; 781def setune : PatFrag<(ops node:$lhs, node:$rhs), 782 (setcc node:$lhs, node:$rhs, SETUNE)>; 783def seteq : PatFrag<(ops node:$lhs, node:$rhs), 784 (setcc node:$lhs, node:$rhs, SETEQ)>; 785def setgt : PatFrag<(ops node:$lhs, node:$rhs), 786 (setcc node:$lhs, node:$rhs, SETGT)>; 787def setge : PatFrag<(ops node:$lhs, node:$rhs), 788 (setcc node:$lhs, node:$rhs, SETGE)>; 789def setlt : PatFrag<(ops node:$lhs, node:$rhs), 790 (setcc node:$lhs, node:$rhs, SETLT)>; 791def setle : PatFrag<(ops node:$lhs, node:$rhs), 792 (setcc node:$lhs, node:$rhs, SETLE)>; 793def setne : PatFrag<(ops node:$lhs, node:$rhs), 794 (setcc node:$lhs, node:$rhs, SETNE)>; 795 796def atomic_cmp_swap_8 : 797 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 798 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 799 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 800}]>; 801def atomic_cmp_swap_16 : 802 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 803 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 804 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 805}]>; 806def atomic_cmp_swap_32 : 807 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 808 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 809 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 810}]>; 811def atomic_cmp_swap_64 : 812 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 813 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 814 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 815}]>; 816 817multiclass binary_atomic_op<SDNode atomic_op> { 818 def _8 : PatFrag<(ops node:$ptr, node:$val), 819 (atomic_op node:$ptr, node:$val), [{ 820 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 821 }]>; 822 def _16 : PatFrag<(ops node:$ptr, node:$val), 823 (atomic_op node:$ptr, node:$val), [{ 824 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 825 }]>; 826 def _32 : PatFrag<(ops node:$ptr, node:$val), 827 (atomic_op node:$ptr, node:$val), [{ 828 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 829 }]>; 830 def _64 : PatFrag<(ops node:$ptr, node:$val), 831 (atomic_op node:$ptr, node:$val), [{ 832 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 833 }]>; 834} 835 836defm atomic_load_add : binary_atomic_op<atomic_load_add>; 837defm atomic_swap : binary_atomic_op<atomic_swap>; 838defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 839defm atomic_load_and : binary_atomic_op<atomic_load_and>; 840defm atomic_load_or : binary_atomic_op<atomic_load_or>; 841defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 842defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 843defm atomic_load_min : binary_atomic_op<atomic_load_min>; 844defm atomic_load_max : binary_atomic_op<atomic_load_max>; 845defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 846defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 847 848//===----------------------------------------------------------------------===// 849// Selection DAG CONVERT_RNDSAT patterns 850 851def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 852 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 853 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 854 }]>; 855 856def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 857 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 858 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 859 }]>; 860 861def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 862 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 863 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 864 }]>; 865 866def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 867 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 868 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 869 }]>; 870 871def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 872 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 873 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 874 }]>; 875 876def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 877 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 878 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 879 }]>; 880 881def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 882 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 883 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 884 }]>; 885 886def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 887 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 888 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 889 }]>; 890 891def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 892 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 893 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 894 }]>; 895 896//===----------------------------------------------------------------------===// 897// Selection DAG Pattern Support. 898// 899// Patterns are what are actually matched against by the target-flavored 900// instruction selection DAG. Instructions defined by the target implicitly 901// define patterns in most cases, but patterns can also be explicitly added when 902// an operation is defined by a sequence of instructions (e.g. loading a large 903// immediate value on RISC targets that do not support immediates as large as 904// their GPRs). 905// 906 907class Pattern<dag patternToMatch, list<dag> resultInstrs> { 908 dag PatternToMatch = patternToMatch; 909 list<dag> ResultInstrs = resultInstrs; 910 list<Predicate> Predicates = []; // See class Instruction in Target.td. 911 int AddedComplexity = 0; // See class Instruction in Target.td. 912} 913 914// Pat - A simple (but common) form of a pattern, which produces a simple result 915// not needing a full list. 916class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 917 918//===----------------------------------------------------------------------===// 919// Complex pattern definitions. 920// 921 922// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 923// in C++. NumOperands is the number of operands returned by the select function; 924// SelectFunc is the name of the function used to pattern match the max. pattern; 925// RootNodes are the list of possible root nodes of the sub-dags to match. 926// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 927// 928class ComplexPattern<ValueType ty, int numops, string fn, 929 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 930 ValueType Ty = ty; 931 int NumOperands = numops; 932 string SelectFunc = fn; 933 list<SDNode> RootNodes = roots; 934 list<SDNodeProperty> Properties = props; 935} 936