TargetSelectionDAG.td revision 63974b2144c87c962effdc0508c27643c8ad98b6
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65/// with length less that of OtherOp, which is a vector type. 66class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69} 70 71//===----------------------------------------------------------------------===// 72// Selection DAG Type Profile definitions. 73// 74// These use the constraints defined above to describe the type requirements of 75// the various nodes. These are not hard coded into tblgen, allowing targets to 76// add their own if needed. 77// 78 79// SDTypeProfile - This profile describes the type requirements of a Selection 80// DAG node. 81class SDTypeProfile<int numresults, int numoperands, 82 list<SDTypeConstraint> constraints> { 83 int NumResults = numresults; 84 int NumOperands = numoperands; 85 list<SDTypeConstraint> Constraints = constraints; 86} 87 88// Builtin profiles. 89def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 90def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 91def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 92def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 93def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 94def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 95 96def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 98]>; 99def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 101]>; 102def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 104]>; 105 106def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 108]>; 109def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 111]>; 112def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 114]>; 115def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 116 SDTCisSameAs<0, 1>, SDTCisInt<0> 117]>; 118def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 120]>; 121def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 123]>; 124def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 125 SDTCisSameAs<0, 1>, SDTCisFP<0> 126]>; 127def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 129]>; 130def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 132]>; 133def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 134 SDTCisFP<0>, SDTCisInt<1> 135]>; 136def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 137 SDTCisInt<0>, SDTCisFP<1> 138]>; 139def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 141 SDTCisVTSmallerThanOp<2, 1> 142]>; 143 144def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 146]>; 147 148def SDTSelect : SDTypeProfile<1, 3, [ // select 149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 150]>; 151 152def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 153 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 154]>; 155 156def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 157 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 158 SDTCisVT<5, OtherVT> 159]>; 160 161def SDTBr : SDTypeProfile<0, 1, [ // br 162 SDTCisVT<0, OtherVT> 163]>; 164 165def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 166 SDTCisInt<0>, SDTCisVT<1, OtherVT> 167]>; 168 169def SDTBrind : SDTypeProfile<0, 1, [ // brind 170 SDTCisPtrTy<0> 171]>; 172 173def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 174 175def SDTLoad : SDTypeProfile<1, 1, [ // load 176 SDTCisPtrTy<1> 177]>; 178 179def SDTStore : SDTypeProfile<0, 2, [ // store 180 SDTCisPtrTy<1> 181]>; 182 183def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 184 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 185]>; 186 187def SDTVecShuffle : SDTypeProfile<1, 2, [ 188 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 189]>; 190def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 191 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 192]>; 193def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 194 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 195]>; 196 197def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 198 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 199]>; 200def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 201 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 202]>; 203 204def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 205 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 206]>; 207 208def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier 209 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 210 SDTCisInt<0> 211]>; 212def SDTAtomicFence : SDTypeProfile<0, 2, [ 213 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 214]>; 215def SDTAtomic3 : SDTypeProfile<1, 3, [ 216 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 217]>; 218def SDTAtomic2 : SDTypeProfile<1, 2, [ 219 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 220]>; 221def SDTAtomicStore : SDTypeProfile<0, 2, [ 222 SDTCisPtrTy<0>, SDTCisInt<1> 223]>; 224def SDTAtomicLoad : SDTypeProfile<1, 1, [ 225 SDTCisInt<0>, SDTCisPtrTy<1> 226]>; 227 228def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 229 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 230]>; 231 232class SDCallSeqStart<list<SDTypeConstraint> constraints> : 233 SDTypeProfile<0, 1, constraints>; 234class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 235 SDTypeProfile<0, 2, constraints>; 236 237//===----------------------------------------------------------------------===// 238// Selection DAG Node Properties. 239// 240// Note: These are hard coded into tblgen. 241// 242class SDNodeProperty; 243def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 244def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 245def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 246def SDNPOutGlue : SDNodeProperty; // Write a flag result 247def SDNPInGlue : SDNodeProperty; // Read a flag operand 248def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 249def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 250def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 251def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 252def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 253def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 254def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 255def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 256 257//===----------------------------------------------------------------------===// 258// Selection DAG Pattern Operations 259class SDPatternOperator; 260 261//===----------------------------------------------------------------------===// 262// Selection DAG Node definitions. 263// 264class SDNode<string opcode, SDTypeProfile typeprof, 265 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 266 : SDPatternOperator { 267 string Opcode = opcode; 268 string SDClass = sdclass; 269 list<SDNodeProperty> Properties = props; 270 SDTypeProfile TypeProfile = typeprof; 271} 272 273// Special TableGen-recognized dag nodes 274def set; 275def implicit; 276def node; 277def srcvalue; 278 279def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 280def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 281def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 282def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 283def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 284def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 285def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 286def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 287 "GlobalAddressSDNode">; 288def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 289 "GlobalAddressSDNode">; 290def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 291 "GlobalAddressSDNode">; 292def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 293 "GlobalAddressSDNode">; 294def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 295 "ConstantPoolSDNode">; 296def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 297 "ConstantPoolSDNode">; 298def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 299 "JumpTableSDNode">; 300def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 301 "JumpTableSDNode">; 302def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 303 "FrameIndexSDNode">; 304def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 305 "FrameIndexSDNode">; 306def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 307 "ExternalSymbolSDNode">; 308def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 309 "ExternalSymbolSDNode">; 310def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 311 "BlockAddressSDNode">; 312def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 313 "BlockAddressSDNode">; 314 315def add : SDNode<"ISD::ADD" , SDTIntBinOp , 316 [SDNPCommutative, SDNPAssociative]>; 317def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 318def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 319 [SDNPCommutative, SDNPAssociative]>; 320def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 321def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 322def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 323def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 324def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 325def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 326def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 327def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 328def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 329def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 330def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 331def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 332def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 333def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 334def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 335def and : SDNode<"ISD::AND" , SDTIntBinOp, 336 [SDNPCommutative, SDNPAssociative]>; 337def or : SDNode<"ISD::OR" , SDTIntBinOp, 338 [SDNPCommutative, SDNPAssociative]>; 339def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 340 [SDNPCommutative, SDNPAssociative]>; 341def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 342 [SDNPCommutative, SDNPOutGlue]>; 343def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 344 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 345def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 346 [SDNPOutGlue]>; 347def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 348 [SDNPOutGlue, SDNPInGlue]>; 349 350def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 351def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 352def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 353def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 354def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 355def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>; 356def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>; 357def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 358def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 359def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 360def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 361def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 362def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 363def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 364 365 366def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 367def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 368def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 369def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 370def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 371def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 372def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 373def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 374def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 375def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 376def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 377def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 378def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 379def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 380def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 381def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 382def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 383def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 384def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 385 386def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 387def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 388def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 389 390def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 391def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 392def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 393def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 394def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 395def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 396 397def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 398def select : SDNode<"ISD::SELECT" , SDTSelect>; 399def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 400def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 401 402def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 403def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 404def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 405def trap : SDNode<"ISD::TRAP" , SDTNone, 406 [SDNPHasChain, SDNPSideEffect]>; 407 408def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 409 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 410 SDNPMemOperand]>; 411 412def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, 413 [SDNPHasChain, SDNPSideEffect]>; 414 415def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 416 [SDNPHasChain, SDNPSideEffect]>; 417 418def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 419 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 420def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 421 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 422def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 423 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 424def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 425 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 426def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 427 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 428def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 429 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 430def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 431 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 432def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 433 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 434def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 435 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 436def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 437 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 438def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 439 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 440def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 441 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 442def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 443 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 444def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 445 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 446 447// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 448// and truncst (see below). 449def ld : SDNode<"ISD::LOAD" , SDTLoad, 450 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 451def st : SDNode<"ISD::STORE" , SDTStore, 452 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 453def ist : SDNode<"ISD::STORE" , SDTIStore, 454 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 455 456def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 457def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 458def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 459 []>; 460def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 461 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 462def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 463 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 464 465// This operator does not do subvector type checking. The ARM 466// backend, at least, needs it. 467def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 468 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 469 []>; 470 471// This operator does subvector type checking. 472def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 473def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 474 475// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 476// these internally. Don't reference these directly. 477def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 478 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 479 [SDNPHasChain]>; 480def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 481 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 482 [SDNPHasChain]>; 483def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 484 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 485 486// Do not use cvt directly. Use cvt forms below 487def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 488 489//===----------------------------------------------------------------------===// 490// Selection DAG Condition Codes 491 492class CondCode; // ISD::CondCode enums 493def SETOEQ : CondCode; def SETOGT : CondCode; 494def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 495def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 496def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 497def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 498 499def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 500def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 501 502 503//===----------------------------------------------------------------------===// 504// Selection DAG Node Transformation Functions. 505// 506// This mechanism allows targets to manipulate nodes in the output DAG once a 507// match has been formed. This is typically used to manipulate immediate 508// values. 509// 510class SDNodeXForm<SDNode opc, code xformFunction> { 511 SDNode Opcode = opc; 512 code XFormFunction = xformFunction; 513} 514 515def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 516 517//===----------------------------------------------------------------------===// 518// PatPred Subclasses. 519// 520// These allow specifying different sorts of predicates that control whether a 521// node is matched. 522// 523class PatPred; 524 525class CodePatPred<code predicate> : PatPred { 526 code PredicateCode = predicate; 527} 528 529 530//===----------------------------------------------------------------------===// 531// Selection DAG Pattern Fragments. 532// 533// Pattern fragments are reusable chunks of dags that match specific things. 534// They can take arguments and have C++ predicates that control whether they 535// match. They are intended to make the patterns for common instructions more 536// compact and readable. 537// 538 539/// PatFrag - Represents a pattern fragment. This can match something on the 540/// DAG, from a single node to multiple nested other fragments. 541/// 542class PatFrag<dag ops, dag frag, code pred = [{}], 543 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 544 dag Operands = ops; 545 dag Fragment = frag; 546 code PredicateCode = pred; 547 code ImmediateCode = [{}]; 548 SDNodeXForm OperandTransform = xform; 549} 550 551// PatLeaf's are pattern fragments that have no operands. This is just a helper 552// to define immediates and other common things concisely. 553class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 554 : PatFrag<(ops), frag, pred, xform>; 555 556 557// ImmLeaf is a pattern fragment with a constraint on the immediate. The 558// constraint is a function that is run on the immediate (always with the value 559// sign extended out to an int64_t) as Imm. For example: 560// 561// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 562// 563// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 564// is preferred over using PatLeaf because it allows the code generator to 565// reason more about the constraint. 566// 567// If FastIsel should ignore all instructions that have an operand of this type, 568// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 569// the code size of the generated fast instruction selector. 570class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 571 : PatFrag<(ops), (vt imm), [{}], xform> { 572 let ImmediateCode = pred; 573 bit FastIselShouldIgnore = 0; 574} 575 576 577// Leaf fragments. 578 579def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 580def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 581 582def immAllOnesV: PatLeaf<(build_vector), [{ 583 return ISD::isBuildVectorAllOnes(N); 584}]>; 585def immAllZerosV: PatLeaf<(build_vector), [{ 586 return ISD::isBuildVectorAllZeros(N); 587}]>; 588 589 590 591// Other helper fragments. 592def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 593def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 594def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 595 596// load fragments. 597def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 598 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 599}]>; 600def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 601 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 602}]>; 603 604// extending load fragments. 605def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 606 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 607}]>; 608def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 609 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 610}]>; 611def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 612 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 613}]>; 614 615def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 616 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 617}]>; 618def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 619 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 620}]>; 621def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 622 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 623}]>; 624def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 625 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 626}]>; 627def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 628 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 629}]>; 630def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 631 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 632}]>; 633 634def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 635 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 636}]>; 637def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 638 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 639}]>; 640def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 641 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 642}]>; 643def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 644 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 645}]>; 646 647def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 648 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 649}]>; 650def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 651 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 652}]>; 653def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 654 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 655}]>; 656def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 657 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 658}]>; 659 660// store fragments. 661def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 662 (st node:$val, node:$ptr), [{ 663 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 664}]>; 665def store : PatFrag<(ops node:$val, node:$ptr), 666 (unindexedstore node:$val, node:$ptr), [{ 667 return !cast<StoreSDNode>(N)->isTruncatingStore(); 668}]>; 669 670// truncstore fragments. 671def truncstore : PatFrag<(ops node:$val, node:$ptr), 672 (unindexedstore node:$val, node:$ptr), [{ 673 return cast<StoreSDNode>(N)->isTruncatingStore(); 674}]>; 675def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 676 (truncstore node:$val, node:$ptr), [{ 677 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 678}]>; 679def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 680 (truncstore node:$val, node:$ptr), [{ 681 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 682}]>; 683def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 684 (truncstore node:$val, node:$ptr), [{ 685 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 686}]>; 687def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 688 (truncstore node:$val, node:$ptr), [{ 689 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 690}]>; 691def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 692 (truncstore node:$val, node:$ptr), [{ 693 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 694}]>; 695 696// indexed store fragments. 697def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 698 (ist node:$val, node:$base, node:$offset), [{ 699 return !cast<StoreSDNode>(N)->isTruncatingStore(); 700}]>; 701 702def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 703 (istore node:$val, node:$base, node:$offset), [{ 704 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 705 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 706}]>; 707 708def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 709 (ist node:$val, node:$base, node:$offset), [{ 710 return cast<StoreSDNode>(N)->isTruncatingStore(); 711}]>; 712def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 713 (itruncstore node:$val, node:$base, node:$offset), [{ 714 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 715 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 716}]>; 717def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 718 (pre_truncst node:$val, node:$base, node:$offset), [{ 719 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 720}]>; 721def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 722 (pre_truncst node:$val, node:$base, node:$offset), [{ 723 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 724}]>; 725def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 726 (pre_truncst node:$val, node:$base, node:$offset), [{ 727 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 728}]>; 729def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 730 (pre_truncst node:$val, node:$base, node:$offset), [{ 731 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 732}]>; 733def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 734 (pre_truncst node:$val, node:$base, node:$offset), [{ 735 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 736}]>; 737 738def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 739 (istore node:$val, node:$ptr, node:$offset), [{ 740 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 741 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 742}]>; 743 744def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 745 (itruncstore node:$val, node:$base, node:$offset), [{ 746 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 747 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 748}]>; 749def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 750 (post_truncst node:$val, node:$base, node:$offset), [{ 751 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 752}]>; 753def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 754 (post_truncst node:$val, node:$base, node:$offset), [{ 755 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 756}]>; 757def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 758 (post_truncst node:$val, node:$base, node:$offset), [{ 759 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 760}]>; 761def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 762 (post_truncst node:$val, node:$base, node:$offset), [{ 763 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 764}]>; 765def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 766 (post_truncst node:$val, node:$base, node:$offset), [{ 767 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 768}]>; 769 770// setcc convenience fragments. 771def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 772 (setcc node:$lhs, node:$rhs, SETOEQ)>; 773def setogt : PatFrag<(ops node:$lhs, node:$rhs), 774 (setcc node:$lhs, node:$rhs, SETOGT)>; 775def setoge : PatFrag<(ops node:$lhs, node:$rhs), 776 (setcc node:$lhs, node:$rhs, SETOGE)>; 777def setolt : PatFrag<(ops node:$lhs, node:$rhs), 778 (setcc node:$lhs, node:$rhs, SETOLT)>; 779def setole : PatFrag<(ops node:$lhs, node:$rhs), 780 (setcc node:$lhs, node:$rhs, SETOLE)>; 781def setone : PatFrag<(ops node:$lhs, node:$rhs), 782 (setcc node:$lhs, node:$rhs, SETONE)>; 783def seto : PatFrag<(ops node:$lhs, node:$rhs), 784 (setcc node:$lhs, node:$rhs, SETO)>; 785def setuo : PatFrag<(ops node:$lhs, node:$rhs), 786 (setcc node:$lhs, node:$rhs, SETUO)>; 787def setueq : PatFrag<(ops node:$lhs, node:$rhs), 788 (setcc node:$lhs, node:$rhs, SETUEQ)>; 789def setugt : PatFrag<(ops node:$lhs, node:$rhs), 790 (setcc node:$lhs, node:$rhs, SETUGT)>; 791def setuge : PatFrag<(ops node:$lhs, node:$rhs), 792 (setcc node:$lhs, node:$rhs, SETUGE)>; 793def setult : PatFrag<(ops node:$lhs, node:$rhs), 794 (setcc node:$lhs, node:$rhs, SETULT)>; 795def setule : PatFrag<(ops node:$lhs, node:$rhs), 796 (setcc node:$lhs, node:$rhs, SETULE)>; 797def setune : PatFrag<(ops node:$lhs, node:$rhs), 798 (setcc node:$lhs, node:$rhs, SETUNE)>; 799def seteq : PatFrag<(ops node:$lhs, node:$rhs), 800 (setcc node:$lhs, node:$rhs, SETEQ)>; 801def setgt : PatFrag<(ops node:$lhs, node:$rhs), 802 (setcc node:$lhs, node:$rhs, SETGT)>; 803def setge : PatFrag<(ops node:$lhs, node:$rhs), 804 (setcc node:$lhs, node:$rhs, SETGE)>; 805def setlt : PatFrag<(ops node:$lhs, node:$rhs), 806 (setcc node:$lhs, node:$rhs, SETLT)>; 807def setle : PatFrag<(ops node:$lhs, node:$rhs), 808 (setcc node:$lhs, node:$rhs, SETLE)>; 809def setne : PatFrag<(ops node:$lhs, node:$rhs), 810 (setcc node:$lhs, node:$rhs, SETNE)>; 811 812def atomic_cmp_swap_8 : 813 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 814 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 815 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 816}]>; 817def atomic_cmp_swap_16 : 818 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 819 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 820 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 821}]>; 822def atomic_cmp_swap_32 : 823 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 824 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 825 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 826}]>; 827def atomic_cmp_swap_64 : 828 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 829 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 830 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 831}]>; 832 833multiclass binary_atomic_op<SDNode atomic_op> { 834 def _8 : PatFrag<(ops node:$ptr, node:$val), 835 (atomic_op node:$ptr, node:$val), [{ 836 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 837 }]>; 838 def _16 : PatFrag<(ops node:$ptr, node:$val), 839 (atomic_op node:$ptr, node:$val), [{ 840 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 841 }]>; 842 def _32 : PatFrag<(ops node:$ptr, node:$val), 843 (atomic_op node:$ptr, node:$val), [{ 844 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 845 }]>; 846 def _64 : PatFrag<(ops node:$ptr, node:$val), 847 (atomic_op node:$ptr, node:$val), [{ 848 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 849 }]>; 850} 851 852defm atomic_load_add : binary_atomic_op<atomic_load_add>; 853defm atomic_swap : binary_atomic_op<atomic_swap>; 854defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 855defm atomic_load_and : binary_atomic_op<atomic_load_and>; 856defm atomic_load_or : binary_atomic_op<atomic_load_or>; 857defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 858defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 859defm atomic_load_min : binary_atomic_op<atomic_load_min>; 860defm atomic_load_max : binary_atomic_op<atomic_load_max>; 861defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 862defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 863defm atomic_store : binary_atomic_op<atomic_store>; 864 865def atomic_load_8 : 866 PatFrag<(ops node:$ptr), 867 (atomic_load node:$ptr), [{ 868 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 869}]>; 870def atomic_load_16 : 871 PatFrag<(ops node:$ptr), 872 (atomic_load node:$ptr), [{ 873 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 874}]>; 875def atomic_load_32 : 876 PatFrag<(ops node:$ptr), 877 (atomic_load node:$ptr), [{ 878 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 879}]>; 880def atomic_load_64 : 881 PatFrag<(ops node:$ptr), 882 (atomic_load node:$ptr), [{ 883 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 884}]>; 885 886//===----------------------------------------------------------------------===// 887// Selection DAG CONVERT_RNDSAT patterns 888 889def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 890 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 891 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 892 }]>; 893 894def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 895 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 896 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 897 }]>; 898 899def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 900 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 901 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 902 }]>; 903 904def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 905 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 906 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 907 }]>; 908 909def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 910 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 911 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 912 }]>; 913 914def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 915 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 916 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 917 }]>; 918 919def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 920 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 921 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 922 }]>; 923 924def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 925 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 926 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 927 }]>; 928 929def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 930 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 931 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 932 }]>; 933 934//===----------------------------------------------------------------------===// 935// Selection DAG Pattern Support. 936// 937// Patterns are what are actually matched against by the target-flavored 938// instruction selection DAG. Instructions defined by the target implicitly 939// define patterns in most cases, but patterns can also be explicitly added when 940// an operation is defined by a sequence of instructions (e.g. loading a large 941// immediate value on RISC targets that do not support immediates as large as 942// their GPRs). 943// 944 945class Pattern<dag patternToMatch, list<dag> resultInstrs> { 946 dag PatternToMatch = patternToMatch; 947 list<dag> ResultInstrs = resultInstrs; 948 list<Predicate> Predicates = []; // See class Instruction in Target.td. 949 int AddedComplexity = 0; // See class Instruction in Target.td. 950} 951 952// Pat - A simple (but common) form of a pattern, which produces a simple result 953// not needing a full list. 954class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 955 956//===----------------------------------------------------------------------===// 957// Complex pattern definitions. 958// 959 960// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 961// in C++. NumOperands is the number of operands returned by the select function; 962// SelectFunc is the name of the function used to pattern match the max. pattern; 963// RootNodes are the list of possible root nodes of the sub-dags to match. 964// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 965// 966class ComplexPattern<ValueType ty, int numops, string fn, 967 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 968 ValueType Ty = ty; 969 int NumOperands = numops; 970 string SelectFunc = fn; 971 list<SDNode> RootNodes = roots; 972 list<SDNodeProperty> Properties = props; 973} 974