TargetSelectionDAG.td revision 8cc3474f72388836fa4ca7d3622289fb9ee08b41
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65/// with length less that of OtherOp, which is a vector type. 66class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69} 70 71//===----------------------------------------------------------------------===// 72// Selection DAG Type Profile definitions. 73// 74// These use the constraints defined above to describe the type requirements of 75// the various nodes. These are not hard coded into tblgen, allowing targets to 76// add their own if needed. 77// 78 79// SDTypeProfile - This profile describes the type requirements of a Selection 80// DAG node. 81class SDTypeProfile<int numresults, int numoperands, 82 list<SDTypeConstraint> constraints> { 83 int NumResults = numresults; 84 int NumOperands = numoperands; 85 list<SDTypeConstraint> Constraints = constraints; 86} 87 88// Builtin profiles. 89def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 90def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 91def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 92def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 93def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 94def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 95 96def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 98]>; 99def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 101]>; 102def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 104]>; 105 106def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 108]>; 109def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 111]>; 112def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 114]>; 115def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 116 SDTCisSameAs<0, 1>, SDTCisInt<0> 117]>; 118def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 120]>; 121def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 123]>; 124def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 125 SDTCisSameAs<0, 1>, SDTCisFP<0> 126]>; 127def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 129]>; 130def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 132]>; 133def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 134 SDTCisFP<0>, SDTCisInt<1> 135]>; 136def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 137 SDTCisInt<0>, SDTCisFP<1> 138]>; 139def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 141 SDTCisVTSmallerThanOp<2, 1> 142]>; 143 144def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 146]>; 147 148def SDTSelect : SDTypeProfile<1, 3, [ // select 149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 150]>; 151 152def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 153 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 154]>; 155 156def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 157 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 158 SDTCisVT<5, OtherVT> 159]>; 160 161def SDTBr : SDTypeProfile<0, 1, [ // br 162 SDTCisVT<0, OtherVT> 163]>; 164 165def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 166 SDTCisInt<0>, SDTCisVT<1, OtherVT> 167]>; 168 169def SDTBrind : SDTypeProfile<0, 1, [ // brind 170 SDTCisPtrTy<0> 171]>; 172 173def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 174 175def SDTLoad : SDTypeProfile<1, 1, [ // load 176 SDTCisPtrTy<1> 177]>; 178 179def SDTStore : SDTypeProfile<0, 2, [ // store 180 SDTCisPtrTy<1> 181]>; 182 183def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 184 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 185]>; 186 187def SDTVecShuffle : SDTypeProfile<1, 2, [ 188 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 189]>; 190def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 191 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 192]>; 193def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 194 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 195]>; 196 197def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 198 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 199]>; 200def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 201 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 202]>; 203 204def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 205 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 206]>; 207 208def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier 209 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 210 SDTCisInt<0> 211]>; 212def SDTAtomicFence : SDTypeProfile<0, 2, [ 213 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 214]>; 215def SDTAtomic3 : SDTypeProfile<1, 3, [ 216 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 217]>; 218def SDTAtomic2 : SDTypeProfile<1, 2, [ 219 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 220]>; 221def SDTAtomicStore : SDTypeProfile<0, 2, [ 222 SDTCisPtrTy<0>, SDTCisInt<1> 223]>; 224def SDTAtomicLoad : SDTypeProfile<1, 1, [ 225 SDTCisInt<0>, SDTCisPtrTy<1> 226]>; 227 228def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 229 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 230]>; 231 232class SDCallSeqStart<list<SDTypeConstraint> constraints> : 233 SDTypeProfile<0, 1, constraints>; 234class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 235 SDTypeProfile<0, 2, constraints>; 236 237//===----------------------------------------------------------------------===// 238// Selection DAG Node Properties. 239// 240// Note: These are hard coded into tblgen. 241// 242class SDNodeProperty; 243def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 244def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 245def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 246def SDNPOutGlue : SDNodeProperty; // Write a flag result 247def SDNPInGlue : SDNodeProperty; // Read a flag operand 248def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 249def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 250def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 251def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 252def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 253def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 254def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 255def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 256 257//===----------------------------------------------------------------------===// 258// Selection DAG Pattern Operations 259class SDPatternOperator; 260 261//===----------------------------------------------------------------------===// 262// Selection DAG Node definitions. 263// 264class SDNode<string opcode, SDTypeProfile typeprof, 265 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 266 : SDPatternOperator { 267 string Opcode = opcode; 268 string SDClass = sdclass; 269 list<SDNodeProperty> Properties = props; 270 SDTypeProfile TypeProfile = typeprof; 271} 272 273// Special TableGen-recognized dag nodes 274def set; 275def implicit; 276def node; 277def srcvalue; 278 279def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 280def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 281def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 282def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 283def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 284def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 285def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 286def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 287 "GlobalAddressSDNode">; 288def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 289 "GlobalAddressSDNode">; 290def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 291 "GlobalAddressSDNode">; 292def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 293 "GlobalAddressSDNode">; 294def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 295 "ConstantPoolSDNode">; 296def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 297 "ConstantPoolSDNode">; 298def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 299 "JumpTableSDNode">; 300def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 301 "JumpTableSDNode">; 302def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 303 "FrameIndexSDNode">; 304def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 305 "FrameIndexSDNode">; 306def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 307 "ExternalSymbolSDNode">; 308def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 309 "ExternalSymbolSDNode">; 310def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 311 "BlockAddressSDNode">; 312def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 313 "BlockAddressSDNode">; 314 315def add : SDNode<"ISD::ADD" , SDTIntBinOp , 316 [SDNPCommutative, SDNPAssociative]>; 317def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 318def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 319 [SDNPCommutative, SDNPAssociative]>; 320def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 321def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 322def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 323def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 324def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 325def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 326def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 327def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 328def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 329def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 330def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 331def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 332def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 333def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 334def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 335def and : SDNode<"ISD::AND" , SDTIntBinOp, 336 [SDNPCommutative, SDNPAssociative]>; 337def or : SDNode<"ISD::OR" , SDTIntBinOp, 338 [SDNPCommutative, SDNPAssociative]>; 339def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 340 [SDNPCommutative, SDNPAssociative]>; 341def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 342 [SDNPCommutative, SDNPOutGlue]>; 343def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 344 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 345def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 346 [SDNPOutGlue]>; 347def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 348 [SDNPOutGlue, SDNPInGlue]>; 349 350def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 351def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 352def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 353def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 354def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 355def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>; 356def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>; 357def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 358def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 359def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 360def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 361def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 362def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 363def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 364 365 366def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 367def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 368def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 369def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 370def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 371def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 372def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 373def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 374def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 375def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 376def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 377def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 378def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 379def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 380def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 381def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 382def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 383def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 384def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 385 386def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 387def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 388def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 389 390def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 391def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 392def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 393def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 394def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 395def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 396 397def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 398def select : SDNode<"ISD::SELECT" , SDTSelect>; 399def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 400def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 401 402def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 403def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 404def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 405def trap : SDNode<"ISD::TRAP" , SDTNone, 406 [SDNPHasChain, SDNPSideEffect]>; 407def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 408 [SDNPHasChain, SDNPSideEffect]>; 409 410def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 411 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 412 SDNPMemOperand]>; 413 414def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 415 [SDNPHasChain, SDNPSideEffect]>; 416 417def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, 418 [SDNPHasChain, SDNPSideEffect]>; 419 420def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 421 [SDNPHasChain, SDNPSideEffect]>; 422 423def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 424 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 425def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 426 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 427def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 428 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 429def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 430 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 431def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 432 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 433def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 434 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 435def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 436 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 437def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 438 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 439def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 440 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 441def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 442 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 443def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 444 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 445def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 446 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 447def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 448 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 449def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 450 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 451 452// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 453// and truncst (see below). 454def ld : SDNode<"ISD::LOAD" , SDTLoad, 455 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 456def st : SDNode<"ISD::STORE" , SDTStore, 457 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 458def ist : SDNode<"ISD::STORE" , SDTIStore, 459 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 460 461def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 462def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 463def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 464 []>; 465def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 466 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 467def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 468 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 469 470// This operator does not do subvector type checking. The ARM 471// backend, at least, needs it. 472def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 473 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 474 []>; 475 476// This operator does subvector type checking. 477def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 478def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 479 480// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 481// these internally. Don't reference these directly. 482def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 483 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 484 [SDNPHasChain]>; 485def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 486 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 487 [SDNPHasChain]>; 488def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 489 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 490 491// Do not use cvt directly. Use cvt forms below 492def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 493 494//===----------------------------------------------------------------------===// 495// Selection DAG Condition Codes 496 497class CondCode; // ISD::CondCode enums 498def SETOEQ : CondCode; def SETOGT : CondCode; 499def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 500def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 501def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 502def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 503 504def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 505def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 506 507 508//===----------------------------------------------------------------------===// 509// Selection DAG Node Transformation Functions. 510// 511// This mechanism allows targets to manipulate nodes in the output DAG once a 512// match has been formed. This is typically used to manipulate immediate 513// values. 514// 515class SDNodeXForm<SDNode opc, code xformFunction> { 516 SDNode Opcode = opc; 517 code XFormFunction = xformFunction; 518} 519 520def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 521 522//===----------------------------------------------------------------------===// 523// PatPred Subclasses. 524// 525// These allow specifying different sorts of predicates that control whether a 526// node is matched. 527// 528class PatPred; 529 530class CodePatPred<code predicate> : PatPred { 531 code PredicateCode = predicate; 532} 533 534 535//===----------------------------------------------------------------------===// 536// Selection DAG Pattern Fragments. 537// 538// Pattern fragments are reusable chunks of dags that match specific things. 539// They can take arguments and have C++ predicates that control whether they 540// match. They are intended to make the patterns for common instructions more 541// compact and readable. 542// 543 544/// PatFrag - Represents a pattern fragment. This can match something on the 545/// DAG, from a single node to multiple nested other fragments. 546/// 547class PatFrag<dag ops, dag frag, code pred = [{}], 548 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 549 dag Operands = ops; 550 dag Fragment = frag; 551 code PredicateCode = pred; 552 code ImmediateCode = [{}]; 553 SDNodeXForm OperandTransform = xform; 554} 555 556// PatLeaf's are pattern fragments that have no operands. This is just a helper 557// to define immediates and other common things concisely. 558class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 559 : PatFrag<(ops), frag, pred, xform>; 560 561 562// ImmLeaf is a pattern fragment with a constraint on the immediate. The 563// constraint is a function that is run on the immediate (always with the value 564// sign extended out to an int64_t) as Imm. For example: 565// 566// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 567// 568// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 569// is preferred over using PatLeaf because it allows the code generator to 570// reason more about the constraint. 571// 572// If FastIsel should ignore all instructions that have an operand of this type, 573// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 574// the code size of the generated fast instruction selector. 575class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 576 : PatFrag<(ops), (vt imm), [{}], xform> { 577 let ImmediateCode = pred; 578 bit FastIselShouldIgnore = 0; 579} 580 581 582// Leaf fragments. 583 584def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 585def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 586 587def immAllOnesV: PatLeaf<(build_vector), [{ 588 return ISD::isBuildVectorAllOnes(N); 589}]>; 590def immAllZerosV: PatLeaf<(build_vector), [{ 591 return ISD::isBuildVectorAllZeros(N); 592}]>; 593 594 595 596// Other helper fragments. 597def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 598def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 599def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 600 601// null_frag - The null pattern operator is used in multiclass instantiations 602// which accept an SDPatternOperator for use in matching patterns for internal 603// definitions. When expanding a pattern, if the null fragment is referenced 604// in the expansion, the pattern is discarded and it is as-if '[]' had been 605// specified. This allows multiclasses to have the isel patterns be optional. 606def null_frag : SDPatternOperator; 607 608// load fragments. 609def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 610 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 611}]>; 612def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 613 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 614}]>; 615 616// extending load fragments. 617def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 618 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 619}]>; 620def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 621 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 622}]>; 623def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 624 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 625}]>; 626 627def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 628 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 629}]>; 630def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 631 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 632}]>; 633def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 634 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 635}]>; 636def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 637 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 638}]>; 639def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 640 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 641}]>; 642def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 643 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 644}]>; 645 646def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 647 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 648}]>; 649def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 650 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 651}]>; 652def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 653 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 654}]>; 655def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 656 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 657}]>; 658 659def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 660 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 661}]>; 662def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 663 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 664}]>; 665def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 666 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 667}]>; 668def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 669 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 670}]>; 671 672def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 673 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 674}]>; 675def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 676 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 677}]>; 678def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 679 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 680}]>; 681def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 682 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 683}]>; 684def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 685 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32; 686}]>; 687def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 688 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64; 689}]>; 690 691def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 692 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 693}]>; 694def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 695 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 696}]>; 697def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 698 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 699}]>; 700def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 701 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 702}]>; 703 704def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 705 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 706}]>; 707def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 708 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 709}]>; 710def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 711 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 712}]>; 713def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 714 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 715}]>; 716 717// store fragments. 718def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 719 (st node:$val, node:$ptr), [{ 720 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 721}]>; 722def store : PatFrag<(ops node:$val, node:$ptr), 723 (unindexedstore node:$val, node:$ptr), [{ 724 return !cast<StoreSDNode>(N)->isTruncatingStore(); 725}]>; 726 727// truncstore fragments. 728def truncstore : PatFrag<(ops node:$val, node:$ptr), 729 (unindexedstore node:$val, node:$ptr), [{ 730 return cast<StoreSDNode>(N)->isTruncatingStore(); 731}]>; 732def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 733 (truncstore node:$val, node:$ptr), [{ 734 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 735}]>; 736def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 737 (truncstore node:$val, node:$ptr), [{ 738 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 739}]>; 740def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 741 (truncstore node:$val, node:$ptr), [{ 742 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 743}]>; 744def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 745 (truncstore node:$val, node:$ptr), [{ 746 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 747}]>; 748def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 749 (truncstore node:$val, node:$ptr), [{ 750 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 751}]>; 752 753// indexed store fragments. 754def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 755 (ist node:$val, node:$base, node:$offset), [{ 756 return !cast<StoreSDNode>(N)->isTruncatingStore(); 757}]>; 758 759def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 760 (istore node:$val, node:$base, node:$offset), [{ 761 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 762 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 763}]>; 764 765def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 766 (ist node:$val, node:$base, node:$offset), [{ 767 return cast<StoreSDNode>(N)->isTruncatingStore(); 768}]>; 769def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 770 (itruncstore node:$val, node:$base, node:$offset), [{ 771 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 772 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 773}]>; 774def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 775 (pre_truncst node:$val, node:$base, node:$offset), [{ 776 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 777}]>; 778def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 779 (pre_truncst node:$val, node:$base, node:$offset), [{ 780 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 781}]>; 782def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 783 (pre_truncst node:$val, node:$base, node:$offset), [{ 784 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 785}]>; 786def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 787 (pre_truncst node:$val, node:$base, node:$offset), [{ 788 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 789}]>; 790def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 791 (pre_truncst node:$val, node:$base, node:$offset), [{ 792 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 793}]>; 794 795def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 796 (istore node:$val, node:$ptr, node:$offset), [{ 797 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 798 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 799}]>; 800 801def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 802 (itruncstore node:$val, node:$base, node:$offset), [{ 803 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 804 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 805}]>; 806def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 807 (post_truncst node:$val, node:$base, node:$offset), [{ 808 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 809}]>; 810def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 811 (post_truncst node:$val, node:$base, node:$offset), [{ 812 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 813}]>; 814def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 815 (post_truncst node:$val, node:$base, node:$offset), [{ 816 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 817}]>; 818def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 819 (post_truncst node:$val, node:$base, node:$offset), [{ 820 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 821}]>; 822def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 823 (post_truncst node:$val, node:$base, node:$offset), [{ 824 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 825}]>; 826 827// setcc convenience fragments. 828def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 829 (setcc node:$lhs, node:$rhs, SETOEQ)>; 830def setogt : PatFrag<(ops node:$lhs, node:$rhs), 831 (setcc node:$lhs, node:$rhs, SETOGT)>; 832def setoge : PatFrag<(ops node:$lhs, node:$rhs), 833 (setcc node:$lhs, node:$rhs, SETOGE)>; 834def setolt : PatFrag<(ops node:$lhs, node:$rhs), 835 (setcc node:$lhs, node:$rhs, SETOLT)>; 836def setole : PatFrag<(ops node:$lhs, node:$rhs), 837 (setcc node:$lhs, node:$rhs, SETOLE)>; 838def setone : PatFrag<(ops node:$lhs, node:$rhs), 839 (setcc node:$lhs, node:$rhs, SETONE)>; 840def seto : PatFrag<(ops node:$lhs, node:$rhs), 841 (setcc node:$lhs, node:$rhs, SETO)>; 842def setuo : PatFrag<(ops node:$lhs, node:$rhs), 843 (setcc node:$lhs, node:$rhs, SETUO)>; 844def setueq : PatFrag<(ops node:$lhs, node:$rhs), 845 (setcc node:$lhs, node:$rhs, SETUEQ)>; 846def setugt : PatFrag<(ops node:$lhs, node:$rhs), 847 (setcc node:$lhs, node:$rhs, SETUGT)>; 848def setuge : PatFrag<(ops node:$lhs, node:$rhs), 849 (setcc node:$lhs, node:$rhs, SETUGE)>; 850def setult : PatFrag<(ops node:$lhs, node:$rhs), 851 (setcc node:$lhs, node:$rhs, SETULT)>; 852def setule : PatFrag<(ops node:$lhs, node:$rhs), 853 (setcc node:$lhs, node:$rhs, SETULE)>; 854def setune : PatFrag<(ops node:$lhs, node:$rhs), 855 (setcc node:$lhs, node:$rhs, SETUNE)>; 856def seteq : PatFrag<(ops node:$lhs, node:$rhs), 857 (setcc node:$lhs, node:$rhs, SETEQ)>; 858def setgt : PatFrag<(ops node:$lhs, node:$rhs), 859 (setcc node:$lhs, node:$rhs, SETGT)>; 860def setge : PatFrag<(ops node:$lhs, node:$rhs), 861 (setcc node:$lhs, node:$rhs, SETGE)>; 862def setlt : PatFrag<(ops node:$lhs, node:$rhs), 863 (setcc node:$lhs, node:$rhs, SETLT)>; 864def setle : PatFrag<(ops node:$lhs, node:$rhs), 865 (setcc node:$lhs, node:$rhs, SETLE)>; 866def setne : PatFrag<(ops node:$lhs, node:$rhs), 867 (setcc node:$lhs, node:$rhs, SETNE)>; 868 869def atomic_cmp_swap_8 : 870 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 871 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 872 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 873}]>; 874def atomic_cmp_swap_16 : 875 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 876 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 877 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 878}]>; 879def atomic_cmp_swap_32 : 880 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 881 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 882 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 883}]>; 884def atomic_cmp_swap_64 : 885 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 886 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 887 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 888}]>; 889 890multiclass binary_atomic_op<SDNode atomic_op> { 891 def _8 : PatFrag<(ops node:$ptr, node:$val), 892 (atomic_op node:$ptr, node:$val), [{ 893 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 894 }]>; 895 def _16 : PatFrag<(ops node:$ptr, node:$val), 896 (atomic_op node:$ptr, node:$val), [{ 897 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 898 }]>; 899 def _32 : PatFrag<(ops node:$ptr, node:$val), 900 (atomic_op node:$ptr, node:$val), [{ 901 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 902 }]>; 903 def _64 : PatFrag<(ops node:$ptr, node:$val), 904 (atomic_op node:$ptr, node:$val), [{ 905 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 906 }]>; 907} 908 909defm atomic_load_add : binary_atomic_op<atomic_load_add>; 910defm atomic_swap : binary_atomic_op<atomic_swap>; 911defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 912defm atomic_load_and : binary_atomic_op<atomic_load_and>; 913defm atomic_load_or : binary_atomic_op<atomic_load_or>; 914defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 915defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 916defm atomic_load_min : binary_atomic_op<atomic_load_min>; 917defm atomic_load_max : binary_atomic_op<atomic_load_max>; 918defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 919defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 920defm atomic_store : binary_atomic_op<atomic_store>; 921 922def atomic_load_8 : 923 PatFrag<(ops node:$ptr), 924 (atomic_load node:$ptr), [{ 925 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 926}]>; 927def atomic_load_16 : 928 PatFrag<(ops node:$ptr), 929 (atomic_load node:$ptr), [{ 930 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 931}]>; 932def atomic_load_32 : 933 PatFrag<(ops node:$ptr), 934 (atomic_load node:$ptr), [{ 935 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 936}]>; 937def atomic_load_64 : 938 PatFrag<(ops node:$ptr), 939 (atomic_load node:$ptr), [{ 940 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 941}]>; 942 943//===----------------------------------------------------------------------===// 944// Selection DAG CONVERT_RNDSAT patterns 945 946def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 947 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 948 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 949 }]>; 950 951def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 952 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 953 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 954 }]>; 955 956def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 957 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 958 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 959 }]>; 960 961def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 962 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 963 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 964 }]>; 965 966def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 967 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 968 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 969 }]>; 970 971def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 972 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 973 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 974 }]>; 975 976def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 977 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 978 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 979 }]>; 980 981def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 982 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 983 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 984 }]>; 985 986def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 987 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 988 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 989 }]>; 990 991//===----------------------------------------------------------------------===// 992// Selection DAG Pattern Support. 993// 994// Patterns are what are actually matched against by the target-flavored 995// instruction selection DAG. Instructions defined by the target implicitly 996// define patterns in most cases, but patterns can also be explicitly added when 997// an operation is defined by a sequence of instructions (e.g. loading a large 998// immediate value on RISC targets that do not support immediates as large as 999// their GPRs). 1000// 1001 1002class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1003 dag PatternToMatch = patternToMatch; 1004 list<dag> ResultInstrs = resultInstrs; 1005 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1006 int AddedComplexity = 0; // See class Instruction in Target.td. 1007} 1008 1009// Pat - A simple (but common) form of a pattern, which produces a simple result 1010// not needing a full list. 1011class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1012 1013//===----------------------------------------------------------------------===// 1014// Complex pattern definitions. 1015// 1016 1017// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1018// in C++. NumOperands is the number of operands returned by the select function; 1019// SelectFunc is the name of the function used to pattern match the max. pattern; 1020// RootNodes are the list of possible root nodes of the sub-dags to match. 1021// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1022// 1023class ComplexPattern<ValueType ty, int numops, string fn, 1024 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 1025 ValueType Ty = ty; 1026 int NumOperands = numops; 1027 string SelectFunc = fn; 1028 list<SDNode> RootNodes = roots; 1029 list<SDNodeProperty> Properties = props; 1030} 1031