TargetSelectionDAG.td revision 8f9643f0f768d5dcff0ffea1de6191dba1b5b083
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand is has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand is has floating point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisSameAs - The two specified operands have identical types. 40class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 41 int OtherOperandNum = OtherOp; 42} 43 44// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 45// smaller than the 'Other' operand. 46class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 47 int OtherOperandNum = OtherOp; 48} 49 50class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 51 int BigOperandNum = BigOp; 52} 53 54/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are 55/// vector types, and that ThisOp is the result of 56/// MVT::getIntVectorWithNumElements with the number of elements 57/// that ThisOp has. 58class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp> 59 : SDTypeConstraint<ThisOp> { 60 int OtherOpNum = OtherOp; 61} 62 63/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 64/// type as the element type of OtherOp, which is a vector type. 65class SDTCisEltOfVec<int ThisOp, int OtherOp> 66 : SDTypeConstraint<ThisOp> { 67 int OtherOpNum = OtherOp; 68} 69 70//===----------------------------------------------------------------------===// 71// Selection DAG Type Profile definitions. 72// 73// These use the constraints defined above to describe the type requirements of 74// the various nodes. These are not hard coded into tblgen, allowing targets to 75// add their own if needed. 76// 77 78// SDTypeProfile - This profile describes the type requirements of a Selection 79// DAG node. 80class SDTypeProfile<int numresults, int numoperands, 81 list<SDTypeConstraint> constraints> { 82 int NumResults = numresults; 83 int NumOperands = numoperands; 84 list<SDTypeConstraint> Constraints = constraints; 85} 86 87// Builtin profiles. 88def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 89def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 90def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 91def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 92def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 93def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 94 95def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 97]>; 98def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 100]>; 101def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 103]>; 104def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 106]>; 107def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 109]>; 110def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 111 SDTCisSameAs<0, 1>, SDTCisInt<0> 112]>; 113def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 115]>; 116def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 118]>; 119def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 120 SDTCisSameAs<0, 1>, SDTCisFP<0> 121]>; 122def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 124]>; 125def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 127]>; 128def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 129 SDTCisFP<0>, SDTCisInt<1> 130]>; 131def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 132 SDTCisInt<0>, SDTCisFP<1> 133]>; 134def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 136 SDTCisVTSmallerThanOp<2, 1> 137]>; 138 139def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 141]>; 142 143def SDTSelect : SDTypeProfile<1, 3, [ // select 144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 145]>; 146 147def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 149 SDTCisVT<5, OtherVT> 150]>; 151 152def SDTBr : SDTypeProfile<0, 1, [ // br 153 SDTCisVT<0, OtherVT> 154]>; 155 156def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 157 SDTCisInt<0>, SDTCisVT<1, OtherVT> 158]>; 159 160def SDTBrind : SDTypeProfile<0, 1, [ // brind 161 SDTCisPtrTy<0> 162]>; 163 164def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 165 166def SDTLoad : SDTypeProfile<1, 1, [ // load 167 SDTCisPtrTy<1> 168]>; 169 170def SDTStore : SDTypeProfile<0, 2, [ // store 171 SDTCisPtrTy<1> 172]>; 173 174def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 176]>; 177 178def SDTVecShuffle : SDTypeProfile<1, 3, [ 179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0> 180]>; 181def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 183]>; 184def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 186]>; 187 188def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch 189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 190]>; 191 192def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier 193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 194 SDTCisInt<0> 195]>; 196def STDAtomic3 : SDTypeProfile<1, 3, [ 197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 198]>; 199def STDAtomic2 : SDTypeProfile<1, 2, [ 200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 201]>; 202 203def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 204 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 205]>; 206 207class SDCallSeqStart<list<SDTypeConstraint> constraints> : 208 SDTypeProfile<0, 1, constraints>; 209class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 210 SDTypeProfile<0, 2, constraints>; 211 212//===----------------------------------------------------------------------===// 213// Selection DAG Node Properties. 214// 215// Note: These are hard coded into tblgen. 216// 217class SDNodeProperty; 218def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 219def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 220def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 221def SDNPOutFlag : SDNodeProperty; // Write a flag result 222def SDNPInFlag : SDNodeProperty; // Read a flag operand 223def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand 224def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 225def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 226def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 227def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 228 229//===----------------------------------------------------------------------===// 230// Selection DAG Node definitions. 231// 232class SDNode<string opcode, SDTypeProfile typeprof, 233 list<SDNodeProperty> props = [], string sdclass = "SDNode"> { 234 string Opcode = opcode; 235 string SDClass = sdclass; 236 list<SDNodeProperty> Properties = props; 237 SDTypeProfile TypeProfile = typeprof; 238} 239 240def set; 241def implicit; 242def parallel; 243def node; 244def srcvalue; 245 246def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 247def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 248def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 249def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 250def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 251def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 252def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 253def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 254 "GlobalAddressSDNode">; 255def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 256 "GlobalAddressSDNode">; 257def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 258 "GlobalAddressSDNode">; 259def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 260 "GlobalAddressSDNode">; 261def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 262 "ConstantPoolSDNode">; 263def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 264 "ConstantPoolSDNode">; 265def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 266 "JumpTableSDNode">; 267def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 268 "JumpTableSDNode">; 269def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 270 "FrameIndexSDNode">; 271def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 272 "FrameIndexSDNode">; 273def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 274 "ExternalSymbolSDNode">; 275def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 276 "ExternalSymbolSDNode">; 277 278def add : SDNode<"ISD::ADD" , SDTIntBinOp , 279 [SDNPCommutative, SDNPAssociative]>; 280def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 281def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 282 [SDNPCommutative, SDNPAssociative]>; 283def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 284def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 285def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 286def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 287def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 288def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 289def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 290def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 291def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 292def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 293def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 294def and : SDNode<"ISD::AND" , SDTIntBinOp, 295 [SDNPCommutative, SDNPAssociative]>; 296def or : SDNode<"ISD::OR" , SDTIntBinOp, 297 [SDNPCommutative, SDNPAssociative]>; 298def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 299 [SDNPCommutative, SDNPAssociative]>; 300def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 301 [SDNPCommutative, SDNPOutFlag]>; 302def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 303 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; 304def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 305 [SDNPOutFlag]>; 306def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 307 [SDNPOutFlag, SDNPInFlag]>; 308 309def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 310def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 311def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 312def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 313def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 314def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 315def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 316def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 317def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 318def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; 319def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 320def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 321 322 323def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 324def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 325def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 326def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 327def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 328def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 329def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 330def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 331def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 332def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 333def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 334def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 335def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 336def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 337def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 338 339def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 340def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 341def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 342 343def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 344def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 345def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 346def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 347 348def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 349def select : SDNode<"ISD::SELECT" , SDTSelect>; 350def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 351def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 352 353def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 354def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 355def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 356def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>; 357def trap : SDNode<"ISD::TRAP" , SDTNone, 358 [SDNPHasChain, SDNPSideEffect]>; 359 360def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch, 361 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 362 363def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier, 364 [SDNPHasChain, SDNPSideEffect]>; 365 366def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3, 367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 368def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2, 369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 370def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2, 371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 372def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2, 375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 376def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2, 377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 378def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2, 379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 380def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2, 381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 382def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2, 383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 384def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2, 385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 386def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2, 387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 388def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2, 389 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 390 391// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 392// and truncst (see below). 393def ld : SDNode<"ISD::LOAD" , SDTLoad, 394 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 395def st : SDNode<"ISD::STORE" , SDTStore, 396 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 397def ist : SDNode<"ISD::STORE" , SDTIStore, 398 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 399 400def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 401def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 402def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 403 []>; 404def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 405 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 406def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 407 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 408 409// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 410// these internally. Don't reference these directly. 411def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 412 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 413 [SDNPHasChain]>; 414def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 415 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 416 [SDNPHasChain]>; 417def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 418 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 419 420// Do not use cvt directly. Use cvt forms below 421def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 422 423//===----------------------------------------------------------------------===// 424// Selection DAG Condition Codes 425 426class CondCode; // ISD::CondCode enums 427def SETOEQ : CondCode; def SETOGT : CondCode; 428def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 429def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 430def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 431def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 432 433def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 434def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 435 436 437//===----------------------------------------------------------------------===// 438// Selection DAG Node Transformation Functions. 439// 440// This mechanism allows targets to manipulate nodes in the output DAG once a 441// match has been formed. This is typically used to manipulate immediate 442// values. 443// 444class SDNodeXForm<SDNode opc, code xformFunction> { 445 SDNode Opcode = opc; 446 code XFormFunction = xformFunction; 447} 448 449def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 450 451 452//===----------------------------------------------------------------------===// 453// Selection DAG Pattern Fragments. 454// 455// Pattern fragments are reusable chunks of dags that match specific things. 456// They can take arguments and have C++ predicates that control whether they 457// match. They are intended to make the patterns for common instructions more 458// compact and readable. 459// 460 461/// PatFrag - Represents a pattern fragment. This can match something on the 462/// DAG, frame a single node to multiply nested other fragments. 463/// 464class PatFrag<dag ops, dag frag, code pred = [{}], 465 SDNodeXForm xform = NOOP_SDNodeXForm> { 466 dag Operands = ops; 467 dag Fragment = frag; 468 code Predicate = pred; 469 SDNodeXForm OperandTransform = xform; 470} 471 472// PatLeaf's are pattern fragments that have no operands. This is just a helper 473// to define immediates and other common things concisely. 474class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 475 : PatFrag<(ops), frag, pred, xform>; 476 477// Leaf fragments. 478 479def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 480def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 481 482def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>; 483def immAllOnesV: PatLeaf<(build_vector), [{ 484 return ISD::isBuildVectorAllOnes(N); 485}]>; 486def immAllOnesV_bc: PatLeaf<(bitconvert), [{ 487 return ISD::isBuildVectorAllOnes(N); 488}]>; 489def immAllZerosV: PatLeaf<(build_vector), [{ 490 return ISD::isBuildVectorAllZeros(N); 491}]>; 492def immAllZerosV_bc: PatLeaf<(bitconvert), [{ 493 return ISD::isBuildVectorAllZeros(N); 494}]>; 495 496 497 498// Other helper fragments. 499def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>; 500def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 501def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; 502def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 503 504// load fragments. 505def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 506 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 507}]>; 508def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 509 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 510}]>; 511 512// extending load fragments. 513def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 514 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 515}]>; 516def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 517 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 518}]>; 519def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 520 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 521}]>; 522 523def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 524 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 525}]>; 526def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 527 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 528}]>; 529def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 530 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 531}]>; 532def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 533 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 534}]>; 535def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 536 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 537}]>; 538def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 539 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 540}]>; 541 542def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 543 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 544}]>; 545def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 546 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 547}]>; 548def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 549 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 550}]>; 551def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 552 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 553}]>; 554 555def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 556 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 557}]>; 558def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 559 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 560}]>; 561def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 562 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 563}]>; 564def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 565 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 566}]>; 567 568// store fragments. 569def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 570 (st node:$val, node:$ptr), [{ 571 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 572}]>; 573def store : PatFrag<(ops node:$val, node:$ptr), 574 (unindexedstore node:$val, node:$ptr), [{ 575 return !cast<StoreSDNode>(N)->isTruncatingStore(); 576}]>; 577 578// truncstore fragments. 579def truncstore : PatFrag<(ops node:$val, node:$ptr), 580 (unindexedstore node:$val, node:$ptr), [{ 581 return cast<StoreSDNode>(N)->isTruncatingStore(); 582}]>; 583def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 584 (truncstore node:$val, node:$ptr), [{ 585 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 586}]>; 587def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 588 (truncstore node:$val, node:$ptr), [{ 589 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 590}]>; 591def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 592 (truncstore node:$val, node:$ptr), [{ 593 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 594}]>; 595def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 596 (truncstore node:$val, node:$ptr), [{ 597 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 598}]>; 599def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 600 (truncstore node:$val, node:$ptr), [{ 601 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 602}]>; 603 604// indexed store fragments. 605def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 606 (ist node:$val, node:$base, node:$offset), [{ 607 return !cast<StoreSDNode>(N)->isTruncatingStore(); 608}]>; 609 610def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 611 (istore node:$val, node:$base, node:$offset), [{ 612 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 613 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 614}]>; 615 616def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 617 (ist node:$val, node:$base, node:$offset), [{ 618 return cast<StoreSDNode>(N)->isTruncatingStore(); 619}]>; 620def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 621 (itruncstore node:$val, node:$base, node:$offset), [{ 622 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 623 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 624}]>; 625def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 626 (pre_truncst node:$val, node:$base, node:$offset), [{ 627 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 628}]>; 629def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 630 (pre_truncst node:$val, node:$base, node:$offset), [{ 631 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 632}]>; 633def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 634 (pre_truncst node:$val, node:$base, node:$offset), [{ 635 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 636}]>; 637def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 638 (pre_truncst node:$val, node:$base, node:$offset), [{ 639 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 640}]>; 641def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 642 (pre_truncst node:$val, node:$base, node:$offset), [{ 643 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 644}]>; 645 646def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 647 (istore node:$val, node:$ptr, node:$offset), [{ 648 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 649 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 650}]>; 651 652def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 653 (itruncstore node:$val, node:$base, node:$offset), [{ 654 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 655 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 656}]>; 657def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 658 (post_truncst node:$val, node:$base, node:$offset), [{ 659 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 660}]>; 661def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 662 (post_truncst node:$val, node:$base, node:$offset), [{ 663 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 664}]>; 665def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 666 (post_truncst node:$val, node:$base, node:$offset), [{ 667 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 668}]>; 669def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 670 (post_truncst node:$val, node:$base, node:$offset), [{ 671 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 672}]>; 673def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 674 (post_truncst node:$val, node:$base, node:$offset), [{ 675 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 676}]>; 677 678// setcc convenience fragments. 679def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 680 (setcc node:$lhs, node:$rhs, SETOEQ)>; 681def setogt : PatFrag<(ops node:$lhs, node:$rhs), 682 (setcc node:$lhs, node:$rhs, SETOGT)>; 683def setoge : PatFrag<(ops node:$lhs, node:$rhs), 684 (setcc node:$lhs, node:$rhs, SETOGE)>; 685def setolt : PatFrag<(ops node:$lhs, node:$rhs), 686 (setcc node:$lhs, node:$rhs, SETOLT)>; 687def setole : PatFrag<(ops node:$lhs, node:$rhs), 688 (setcc node:$lhs, node:$rhs, SETOLE)>; 689def setone : PatFrag<(ops node:$lhs, node:$rhs), 690 (setcc node:$lhs, node:$rhs, SETONE)>; 691def seto : PatFrag<(ops node:$lhs, node:$rhs), 692 (setcc node:$lhs, node:$rhs, SETO)>; 693def setuo : PatFrag<(ops node:$lhs, node:$rhs), 694 (setcc node:$lhs, node:$rhs, SETUO)>; 695def setueq : PatFrag<(ops node:$lhs, node:$rhs), 696 (setcc node:$lhs, node:$rhs, SETUEQ)>; 697def setugt : PatFrag<(ops node:$lhs, node:$rhs), 698 (setcc node:$lhs, node:$rhs, SETUGT)>; 699def setuge : PatFrag<(ops node:$lhs, node:$rhs), 700 (setcc node:$lhs, node:$rhs, SETUGE)>; 701def setult : PatFrag<(ops node:$lhs, node:$rhs), 702 (setcc node:$lhs, node:$rhs, SETULT)>; 703def setule : PatFrag<(ops node:$lhs, node:$rhs), 704 (setcc node:$lhs, node:$rhs, SETULE)>; 705def setune : PatFrag<(ops node:$lhs, node:$rhs), 706 (setcc node:$lhs, node:$rhs, SETUNE)>; 707def seteq : PatFrag<(ops node:$lhs, node:$rhs), 708 (setcc node:$lhs, node:$rhs, SETEQ)>; 709def setgt : PatFrag<(ops node:$lhs, node:$rhs), 710 (setcc node:$lhs, node:$rhs, SETGT)>; 711def setge : PatFrag<(ops node:$lhs, node:$rhs), 712 (setcc node:$lhs, node:$rhs, SETGE)>; 713def setlt : PatFrag<(ops node:$lhs, node:$rhs), 714 (setcc node:$lhs, node:$rhs, SETLT)>; 715def setle : PatFrag<(ops node:$lhs, node:$rhs), 716 (setcc node:$lhs, node:$rhs, SETLE)>; 717def setne : PatFrag<(ops node:$lhs, node:$rhs), 718 (setcc node:$lhs, node:$rhs, SETNE)>; 719 720def atomic_cmp_swap_8 : 721 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 722 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 723 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 724}]>; 725def atomic_cmp_swap_16 : 726 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 727 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 728 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 729}]>; 730def atomic_cmp_swap_32 : 731 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 732 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 733 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 734}]>; 735def atomic_cmp_swap_64 : 736 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 737 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 738 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 739}]>; 740 741multiclass binary_atomic_op<SDNode atomic_op> { 742 def _8 : PatFrag<(ops node:$ptr, node:$val), 743 (atomic_op node:$ptr, node:$val), [{ 744 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 745 }]>; 746 def _16 : PatFrag<(ops node:$ptr, node:$val), 747 (atomic_op node:$ptr, node:$val), [{ 748 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 749 }]>; 750 def _32 : PatFrag<(ops node:$ptr, node:$val), 751 (atomic_op node:$ptr, node:$val), [{ 752 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 753 }]>; 754 def _64 : PatFrag<(ops node:$ptr, node:$val), 755 (atomic_op node:$ptr, node:$val), [{ 756 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 757 }]>; 758} 759 760defm atomic_load_add : binary_atomic_op<atomic_load_add>; 761defm atomic_swap : binary_atomic_op<atomic_swap>; 762defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 763defm atomic_load_and : binary_atomic_op<atomic_load_and>; 764defm atomic_load_or : binary_atomic_op<atomic_load_or>; 765defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 766defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 767defm atomic_load_min : binary_atomic_op<atomic_load_min>; 768defm atomic_load_max : binary_atomic_op<atomic_load_max>; 769defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 770defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 771 772//===----------------------------------------------------------------------===// 773// Selection DAG CONVERT_RNDSAT patterns 774 775def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 776 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 777 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 778 }]>; 779 780def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 781 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 782 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 783 }]>; 784 785def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 786 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 787 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 788 }]>; 789 790def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 791 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 792 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 793 }]>; 794 795def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 796 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 797 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 798 }]>; 799 800def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 801 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 802 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 803 }]>; 804 805def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 806 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 807 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 808 }]>; 809 810def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 811 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 812 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 813 }]>; 814 815def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 816 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 817 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 818 }]>; 819 820//===----------------------------------------------------------------------===// 821// Selection DAG Pattern Support. 822// 823// Patterns are what are actually matched against the target-flavored 824// instruction selection DAG. Instructions defined by the target implicitly 825// define patterns in most cases, but patterns can also be explicitly added when 826// an operation is defined by a sequence of instructions (e.g. loading a large 827// immediate value on RISC targets that do not support immediates as large as 828// their GPRs). 829// 830 831class Pattern<dag patternToMatch, list<dag> resultInstrs> { 832 dag PatternToMatch = patternToMatch; 833 list<dag> ResultInstrs = resultInstrs; 834 list<Predicate> Predicates = []; // See class Instruction in Target.td. 835 int AddedComplexity = 0; // See class Instruction in Target.td. 836} 837 838// Pat - A simple (but common) form of a pattern, which produces a simple result 839// not needing a full list. 840class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 841 842//===----------------------------------------------------------------------===// 843// Complex pattern definitions. 844// 845 846class CPAttribute; 847// Pass the parent Operand as root to CP function rather 848// than the root of the sub-DAG 849def CPAttrParentAsRoot : CPAttribute; 850 851// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 852// in C++. NumOperands is the number of operands returned by the select function; 853// SelectFunc is the name of the function used to pattern match the max. pattern; 854// RootNodes are the list of possible root nodes of the sub-dags to match. 855// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 856// 857class ComplexPattern<ValueType ty, int numops, string fn, 858 list<SDNode> roots = [], list<SDNodeProperty> props = [], 859 list<CPAttribute> attrs = []> { 860 ValueType Ty = ty; 861 int NumOperands = numops; 862 string SelectFunc = fn; 863 list<SDNode> RootNodes = roots; 864 list<SDNodeProperty> Properties = props; 865 list<CPAttribute> Attributes = attrs; 866} 867 868//===----------------------------------------------------------------------===// 869// Dwarf support. 870// 871def SDT_dwarf_loc : SDTypeProfile<0, 3, 872 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>; 873def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>; 874