TargetSelectionDAG.td revision b706d29f9c5ed3ed9acc82f7ab46205ba56b92dc
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand is has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand is has floating point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisSameAs - The two specified operands have identical types. 40class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 41 int OtherOperandNum = OtherOp; 42} 43 44// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 45// smaller than the 'Other' operand. 46class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 47 int OtherOperandNum = OtherOp; 48} 49 50class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 51 int BigOperandNum = BigOp; 52} 53 54/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 55/// type as the element type of OtherOp, which is a vector type. 56class SDTCisEltOfVec<int ThisOp, int OtherOp> 57 : SDTypeConstraint<ThisOp> { 58 int OtherOpNum = OtherOp; 59} 60 61//===----------------------------------------------------------------------===// 62// Selection DAG Type Profile definitions. 63// 64// These use the constraints defined above to describe the type requirements of 65// the various nodes. These are not hard coded into tblgen, allowing targets to 66// add their own if needed. 67// 68 69// SDTypeProfile - This profile describes the type requirements of a Selection 70// DAG node. 71class SDTypeProfile<int numresults, int numoperands, 72 list<SDTypeConstraint> constraints> { 73 int NumResults = numresults; 74 int NumOperands = numoperands; 75 list<SDTypeConstraint> Constraints = constraints; 76} 77 78// Builtin profiles. 79def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 80def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 81def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 82def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 83def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 84def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 85 86def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 87 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 88]>; 89def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 90 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 91]>; 92def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 93 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 94]>; 95def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 96 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 97]>; 98def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 99 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 100]>; 101def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 102 SDTCisSameAs<0, 1>, SDTCisInt<0> 103]>; 104def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 105 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 106]>; 107def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 108 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 109]>; 110def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 111 SDTCisSameAs<0, 1>, SDTCisFP<0> 112]>; 113def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 114 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 115]>; 116def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 117 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 118]>; 119def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 120 SDTCisFP<0>, SDTCisInt<1> 121]>; 122def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 123 SDTCisInt<0>, SDTCisFP<1> 124]>; 125def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 126 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 127 SDTCisVTSmallerThanOp<2, 1> 128]>; 129 130def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 131 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 132]>; 133 134def SDTSelect : SDTypeProfile<1, 3, [ // select 135 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 136]>; 137 138def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 139 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 140 SDTCisVT<5, OtherVT> 141]>; 142 143def SDTBr : SDTypeProfile<0, 1, [ // br 144 SDTCisVT<0, OtherVT> 145]>; 146 147def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 148 SDTCisInt<0>, SDTCisVT<1, OtherVT> 149]>; 150 151def SDTBrind : SDTypeProfile<0, 1, [ // brind 152 SDTCisPtrTy<0> 153]>; 154 155def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 156 157def SDTLoad : SDTypeProfile<1, 1, [ // load 158 SDTCisPtrTy<1> 159]>; 160 161def SDTStore : SDTypeProfile<0, 2, [ // store 162 SDTCisPtrTy<1> 163]>; 164 165def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 166 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 167]>; 168 169def SDTVecShuffle : SDTypeProfile<1, 2, [ 170 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 171]>; 172def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 173 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 174]>; 175def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 176 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 177]>; 178 179def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch 180 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 181]>; 182 183def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier 184 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 185 SDTCisInt<0> 186]>; 187def STDAtomic3 : SDTypeProfile<1, 3, [ 188 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 189]>; 190def STDAtomic2 : SDTypeProfile<1, 2, [ 191 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 192]>; 193 194def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 195 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 196]>; 197 198class SDCallSeqStart<list<SDTypeConstraint> constraints> : 199 SDTypeProfile<0, 1, constraints>; 200class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 201 SDTypeProfile<0, 2, constraints>; 202 203//===----------------------------------------------------------------------===// 204// Selection DAG Node Properties. 205// 206// Note: These are hard coded into tblgen. 207// 208class SDNodeProperty; 209def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 210def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 211def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 212def SDNPOutFlag : SDNodeProperty; // Write a flag result 213def SDNPInFlag : SDNodeProperty; // Read a flag operand 214def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand 215def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 216def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 217def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 218def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 219 220//===----------------------------------------------------------------------===// 221// Selection DAG Node definitions. 222// 223class SDNode<string opcode, SDTypeProfile typeprof, 224 list<SDNodeProperty> props = [], string sdclass = "SDNode"> { 225 string Opcode = opcode; 226 string SDClass = sdclass; 227 list<SDNodeProperty> Properties = props; 228 SDTypeProfile TypeProfile = typeprof; 229} 230 231def set; 232def implicit; 233def parallel; 234def node; 235def srcvalue; 236 237def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 238def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 239def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 240def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 241def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 242def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 243def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 244def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 245 "GlobalAddressSDNode">; 246def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 247 "GlobalAddressSDNode">; 248def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 249 "GlobalAddressSDNode">; 250def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 251 "GlobalAddressSDNode">; 252def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 253 "ConstantPoolSDNode">; 254def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 255 "ConstantPoolSDNode">; 256def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 257 "JumpTableSDNode">; 258def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 259 "JumpTableSDNode">; 260def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 261 "FrameIndexSDNode">; 262def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 263 "FrameIndexSDNode">; 264def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 265 "ExternalSymbolSDNode">; 266def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 267 "ExternalSymbolSDNode">; 268 269def add : SDNode<"ISD::ADD" , SDTIntBinOp , 270 [SDNPCommutative, SDNPAssociative]>; 271def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 272def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 273 [SDNPCommutative, SDNPAssociative]>; 274def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 275def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 276def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 277def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 278def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 279def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 280def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 281def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 282def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 283def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 284def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 285def and : SDNode<"ISD::AND" , SDTIntBinOp, 286 [SDNPCommutative, SDNPAssociative]>; 287def or : SDNode<"ISD::OR" , SDTIntBinOp, 288 [SDNPCommutative, SDNPAssociative]>; 289def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 290 [SDNPCommutative, SDNPAssociative]>; 291def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 292 [SDNPCommutative, SDNPOutFlag]>; 293def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 294 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; 295def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 296 [SDNPOutFlag]>; 297def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 298 [SDNPOutFlag, SDNPInFlag]>; 299 300def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 301def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 302def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 303def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 304def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 305def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 306def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 307def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 308def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 309def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; 310def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 311def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 312 313 314def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 315def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 316def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 317def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 318def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 319def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 320def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 321def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 322def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 323def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 324def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 325def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 326def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 327def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 328def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 329 330def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 331def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 332def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 333 334def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 335def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 336def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 337def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 338 339def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 340def select : SDNode<"ISD::SELECT" , SDTSelect>; 341def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 342def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 343 344def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 345def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 346def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 347def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>; 348def trap : SDNode<"ISD::TRAP" , SDTNone, 349 [SDNPHasChain, SDNPSideEffect]>; 350 351def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch, 352 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 353 354def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier, 355 [SDNPHasChain, SDNPSideEffect]>; 356 357def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3, 358 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 359def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2, 360 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 361def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2, 362 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 363def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2, 364 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 365def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2, 366 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 367def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2, 368 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 369def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2, 370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 371def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2, 372 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 373def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2, 374 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 375def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2, 376 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 377def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2, 378 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 379def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2, 380 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 381 382// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 383// and truncst (see below). 384def ld : SDNode<"ISD::LOAD" , SDTLoad, 385 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 386def st : SDNode<"ISD::STORE" , SDTStore, 387 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 388def ist : SDNode<"ISD::STORE" , SDTIStore, 389 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 390 391def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 392def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 393def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 394 []>; 395def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 396 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 397def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 398 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 399 400// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 401// these internally. Don't reference these directly. 402def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 403 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 404 [SDNPHasChain]>; 405def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 406 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 407 [SDNPHasChain]>; 408def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 409 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 410 411// Do not use cvt directly. Use cvt forms below 412def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 413 414//===----------------------------------------------------------------------===// 415// Selection DAG Condition Codes 416 417class CondCode; // ISD::CondCode enums 418def SETOEQ : CondCode; def SETOGT : CondCode; 419def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 420def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 421def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 422def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 423 424def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 425def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 426 427 428//===----------------------------------------------------------------------===// 429// Selection DAG Node Transformation Functions. 430// 431// This mechanism allows targets to manipulate nodes in the output DAG once a 432// match has been formed. This is typically used to manipulate immediate 433// values. 434// 435class SDNodeXForm<SDNode opc, code xformFunction> { 436 SDNode Opcode = opc; 437 code XFormFunction = xformFunction; 438} 439 440def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 441 442 443//===----------------------------------------------------------------------===// 444// Selection DAG Pattern Fragments. 445// 446// Pattern fragments are reusable chunks of dags that match specific things. 447// They can take arguments and have C++ predicates that control whether they 448// match. They are intended to make the patterns for common instructions more 449// compact and readable. 450// 451 452/// PatFrag - Represents a pattern fragment. This can match something on the 453/// DAG, frame a single node to multiply nested other fragments. 454/// 455class PatFrag<dag ops, dag frag, code pred = [{}], 456 SDNodeXForm xform = NOOP_SDNodeXForm> { 457 dag Operands = ops; 458 dag Fragment = frag; 459 code Predicate = pred; 460 SDNodeXForm OperandTransform = xform; 461} 462 463// PatLeaf's are pattern fragments that have no operands. This is just a helper 464// to define immediates and other common things concisely. 465class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 466 : PatFrag<(ops), frag, pred, xform>; 467 468// Leaf fragments. 469 470def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 471def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 472 473def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>; 474def immAllOnesV: PatLeaf<(build_vector), [{ 475 return ISD::isBuildVectorAllOnes(N); 476}]>; 477def immAllOnesV_bc: PatLeaf<(bitconvert), [{ 478 return ISD::isBuildVectorAllOnes(N); 479}]>; 480def immAllZerosV: PatLeaf<(build_vector), [{ 481 return ISD::isBuildVectorAllZeros(N); 482}]>; 483def immAllZerosV_bc: PatLeaf<(bitconvert), [{ 484 return ISD::isBuildVectorAllZeros(N); 485}]>; 486 487 488 489// Other helper fragments. 490def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>; 491def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 492def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; 493def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 494 495// load fragments. 496def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 497 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 498}]>; 499def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 500 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 501}]>; 502 503// extending load fragments. 504def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 505 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 506}]>; 507def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 508 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 509}]>; 510def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 511 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 512}]>; 513 514def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 515 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 516}]>; 517def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 518 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 519}]>; 520def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 521 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 522}]>; 523def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 524 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 525}]>; 526def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 527 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 528}]>; 529def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 530 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 531}]>; 532 533def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 534 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 535}]>; 536def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 537 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 538}]>; 539def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 540 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 541}]>; 542def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 543 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 544}]>; 545 546def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 547 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 548}]>; 549def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 550 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 551}]>; 552def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 553 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 554}]>; 555def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 556 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 557}]>; 558 559// store fragments. 560def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 561 (st node:$val, node:$ptr), [{ 562 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 563}]>; 564def store : PatFrag<(ops node:$val, node:$ptr), 565 (unindexedstore node:$val, node:$ptr), [{ 566 return !cast<StoreSDNode>(N)->isTruncatingStore(); 567}]>; 568 569// truncstore fragments. 570def truncstore : PatFrag<(ops node:$val, node:$ptr), 571 (unindexedstore node:$val, node:$ptr), [{ 572 return cast<StoreSDNode>(N)->isTruncatingStore(); 573}]>; 574def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 575 (truncstore node:$val, node:$ptr), [{ 576 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 577}]>; 578def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 579 (truncstore node:$val, node:$ptr), [{ 580 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 581}]>; 582def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 583 (truncstore node:$val, node:$ptr), [{ 584 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 585}]>; 586def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 587 (truncstore node:$val, node:$ptr), [{ 588 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 589}]>; 590def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 591 (truncstore node:$val, node:$ptr), [{ 592 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 593}]>; 594 595// indexed store fragments. 596def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 597 (ist node:$val, node:$base, node:$offset), [{ 598 return !cast<StoreSDNode>(N)->isTruncatingStore(); 599}]>; 600 601def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 602 (istore node:$val, node:$base, node:$offset), [{ 603 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 604 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 605}]>; 606 607def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 608 (ist node:$val, node:$base, node:$offset), [{ 609 return cast<StoreSDNode>(N)->isTruncatingStore(); 610}]>; 611def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 612 (itruncstore node:$val, node:$base, node:$offset), [{ 613 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 614 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 615}]>; 616def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 617 (pre_truncst node:$val, node:$base, node:$offset), [{ 618 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 619}]>; 620def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 621 (pre_truncst node:$val, node:$base, node:$offset), [{ 622 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 623}]>; 624def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 625 (pre_truncst node:$val, node:$base, node:$offset), [{ 626 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 627}]>; 628def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 629 (pre_truncst node:$val, node:$base, node:$offset), [{ 630 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 631}]>; 632def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 633 (pre_truncst node:$val, node:$base, node:$offset), [{ 634 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 635}]>; 636 637def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 638 (istore node:$val, node:$ptr, node:$offset), [{ 639 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 640 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 641}]>; 642 643def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 644 (itruncstore node:$val, node:$base, node:$offset), [{ 645 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 646 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 647}]>; 648def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 649 (post_truncst node:$val, node:$base, node:$offset), [{ 650 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 651}]>; 652def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 653 (post_truncst node:$val, node:$base, node:$offset), [{ 654 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 655}]>; 656def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 657 (post_truncst node:$val, node:$base, node:$offset), [{ 658 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 659}]>; 660def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 661 (post_truncst node:$val, node:$base, node:$offset), [{ 662 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 663}]>; 664def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 665 (post_truncst node:$val, node:$base, node:$offset), [{ 666 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 667}]>; 668 669// setcc convenience fragments. 670def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 671 (setcc node:$lhs, node:$rhs, SETOEQ)>; 672def setogt : PatFrag<(ops node:$lhs, node:$rhs), 673 (setcc node:$lhs, node:$rhs, SETOGT)>; 674def setoge : PatFrag<(ops node:$lhs, node:$rhs), 675 (setcc node:$lhs, node:$rhs, SETOGE)>; 676def setolt : PatFrag<(ops node:$lhs, node:$rhs), 677 (setcc node:$lhs, node:$rhs, SETOLT)>; 678def setole : PatFrag<(ops node:$lhs, node:$rhs), 679 (setcc node:$lhs, node:$rhs, SETOLE)>; 680def setone : PatFrag<(ops node:$lhs, node:$rhs), 681 (setcc node:$lhs, node:$rhs, SETONE)>; 682def seto : PatFrag<(ops node:$lhs, node:$rhs), 683 (setcc node:$lhs, node:$rhs, SETO)>; 684def setuo : PatFrag<(ops node:$lhs, node:$rhs), 685 (setcc node:$lhs, node:$rhs, SETUO)>; 686def setueq : PatFrag<(ops node:$lhs, node:$rhs), 687 (setcc node:$lhs, node:$rhs, SETUEQ)>; 688def setugt : PatFrag<(ops node:$lhs, node:$rhs), 689 (setcc node:$lhs, node:$rhs, SETUGT)>; 690def setuge : PatFrag<(ops node:$lhs, node:$rhs), 691 (setcc node:$lhs, node:$rhs, SETUGE)>; 692def setult : PatFrag<(ops node:$lhs, node:$rhs), 693 (setcc node:$lhs, node:$rhs, SETULT)>; 694def setule : PatFrag<(ops node:$lhs, node:$rhs), 695 (setcc node:$lhs, node:$rhs, SETULE)>; 696def setune : PatFrag<(ops node:$lhs, node:$rhs), 697 (setcc node:$lhs, node:$rhs, SETUNE)>; 698def seteq : PatFrag<(ops node:$lhs, node:$rhs), 699 (setcc node:$lhs, node:$rhs, SETEQ)>; 700def setgt : PatFrag<(ops node:$lhs, node:$rhs), 701 (setcc node:$lhs, node:$rhs, SETGT)>; 702def setge : PatFrag<(ops node:$lhs, node:$rhs), 703 (setcc node:$lhs, node:$rhs, SETGE)>; 704def setlt : PatFrag<(ops node:$lhs, node:$rhs), 705 (setcc node:$lhs, node:$rhs, SETLT)>; 706def setle : PatFrag<(ops node:$lhs, node:$rhs), 707 (setcc node:$lhs, node:$rhs, SETLE)>; 708def setne : PatFrag<(ops node:$lhs, node:$rhs), 709 (setcc node:$lhs, node:$rhs, SETNE)>; 710 711def atomic_cmp_swap_8 : 712 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 713 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 714 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 715}]>; 716def atomic_cmp_swap_16 : 717 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 718 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 719 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 720}]>; 721def atomic_cmp_swap_32 : 722 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 723 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 724 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 725}]>; 726def atomic_cmp_swap_64 : 727 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 728 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 729 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 730}]>; 731 732multiclass binary_atomic_op<SDNode atomic_op> { 733 def _8 : PatFrag<(ops node:$ptr, node:$val), 734 (atomic_op node:$ptr, node:$val), [{ 735 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 736 }]>; 737 def _16 : PatFrag<(ops node:$ptr, node:$val), 738 (atomic_op node:$ptr, node:$val), [{ 739 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 740 }]>; 741 def _32 : PatFrag<(ops node:$ptr, node:$val), 742 (atomic_op node:$ptr, node:$val), [{ 743 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 744 }]>; 745 def _64 : PatFrag<(ops node:$ptr, node:$val), 746 (atomic_op node:$ptr, node:$val), [{ 747 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 748 }]>; 749} 750 751defm atomic_load_add : binary_atomic_op<atomic_load_add>; 752defm atomic_swap : binary_atomic_op<atomic_swap>; 753defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 754defm atomic_load_and : binary_atomic_op<atomic_load_and>; 755defm atomic_load_or : binary_atomic_op<atomic_load_or>; 756defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 757defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 758defm atomic_load_min : binary_atomic_op<atomic_load_min>; 759defm atomic_load_max : binary_atomic_op<atomic_load_max>; 760defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 761defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 762 763//===----------------------------------------------------------------------===// 764// Selection DAG CONVERT_RNDSAT patterns 765 766def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 767 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 768 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 769 }]>; 770 771def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 772 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 773 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 774 }]>; 775 776def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 777 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 778 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 779 }]>; 780 781def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 782 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 783 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 784 }]>; 785 786def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 787 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 788 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 789 }]>; 790 791def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 792 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 793 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 794 }]>; 795 796def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 797 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 798 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 799 }]>; 800 801def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 802 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 803 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 804 }]>; 805 806def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 807 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 808 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 809 }]>; 810 811//===----------------------------------------------------------------------===// 812// Selection DAG Pattern Support. 813// 814// Patterns are what are actually matched against the target-flavored 815// instruction selection DAG. Instructions defined by the target implicitly 816// define patterns in most cases, but patterns can also be explicitly added when 817// an operation is defined by a sequence of instructions (e.g. loading a large 818// immediate value on RISC targets that do not support immediates as large as 819// their GPRs). 820// 821 822class Pattern<dag patternToMatch, list<dag> resultInstrs> { 823 dag PatternToMatch = patternToMatch; 824 list<dag> ResultInstrs = resultInstrs; 825 list<Predicate> Predicates = []; // See class Instruction in Target.td. 826 int AddedComplexity = 0; // See class Instruction in Target.td. 827} 828 829// Pat - A simple (but common) form of a pattern, which produces a simple result 830// not needing a full list. 831class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 832 833//===----------------------------------------------------------------------===// 834// Complex pattern definitions. 835// 836 837class CPAttribute; 838// Pass the parent Operand as root to CP function rather 839// than the root of the sub-DAG 840def CPAttrParentAsRoot : CPAttribute; 841 842// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 843// in C++. NumOperands is the number of operands returned by the select function; 844// SelectFunc is the name of the function used to pattern match the max. pattern; 845// RootNodes are the list of possible root nodes of the sub-dags to match. 846// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 847// 848class ComplexPattern<ValueType ty, int numops, string fn, 849 list<SDNode> roots = [], list<SDNodeProperty> props = [], 850 list<CPAttribute> attrs = []> { 851 ValueType Ty = ty; 852 int NumOperands = numops; 853 string SelectFunc = fn; 854 list<SDNode> RootNodes = roots; 855 list<SDNodeProperty> Properties = props; 856 list<CPAttribute> Attributes = attrs; 857} 858 859//===----------------------------------------------------------------------===// 860// Dwarf support. 861// 862def SDT_dwarf_loc : SDTypeProfile<0, 3, 863 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>; 864def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>; 865